[PATCH] drivers: mci: rockchip: fix HS400 DLL strobe and clock gate config

[Sascha Hauer <s.hauer@pengutronix.de>]

From: Lucas Sinn <lucas.sinn@wolfvision.net>

Align two register writes with the Linux kernel (sdhci-of-dwcmshc.c):

- DLL_STRBIN_TAPNUM_DEFAULT: 0x8 -> 0x4
  The strobe tap number was twice the value used by Linux, placing the
  DS sampling point at the wrong phase at 200 MHz and causing DMA
  timeouts in HS400/HS400-ES mode.

- DWCMSHC_HOST_CTRL3: also disable the internal clock gate (BIT(4))
  Linux clears both the cmd-conflict-check bit (BIT(0)) and the
  internal-clock-gate bit (BIT(4)). Without disabling the clock gate
  the DLL could stall during high-speed operation.

Assisted-by: Claude Sonnet 4.6
Signed-off-by: Lucas Sinn <lucas.sinn@wolfvision.net>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/mci/rockchip-dwcmshc-sdhci.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/mci/rockchip-dwcmshc-sdhci.c b/drivers/mci/rockchip-dwcmshc-sdhci.c
index 0be5d9ff63..8e828a1f1b 100644
--- a/drivers/mci/rockchip-dwcmshc-sdhci.c
+++ b/drivers/mci/rockchip-dwcmshc-sdhci.c
@@ -40,7 +40,7 @@
 #define DLL_TXCLK_TAPNUM_DEFAULT	0x10
 #define DLL_TXCLK_TAPNUM_90_DEGREES	0xA
 #define DLL_TXCLK_TAPNUM_FROM_SW	BIT(24)
-#define DLL_STRBIN_TAPNUM_DEFAULT	0x8
+#define DLL_STRBIN_TAPNUM_DEFAULT	0x4
 #define DLL_STRBIN_TAPNUM_FROM_SW	BIT(24)
 #define DLL_STRBIN_DELAY_NUM_SEL	BIT(26)
 #define DLL_STRBIN_DELAY_NUM_OFFSET	16
@@ -177,9 +177,10 @@ static void rk_sdhci_set_clock(struct rk_sdhci_host *host, unsigned int clock)
 
 	sdhci_set_clock(&host->sdhci, clock, clk_get_rate(host->clks[CLK_CORE].clk));
 
-	/* Disable cmd conflict check */
+	/* Disable cmd conflict check and internal clock gate */
 	extra = sdhci_read32(&host->sdhci, DWCMSHC_HOST_CTRL3);
 	extra &= ~BIT(0);
+	extra |= BIT(4);
 	sdhci_write32(&host->sdhci, DWCMSHC_HOST_CTRL3, extra);
 
 	/* Disable clock while config DLL */
-- 
2.47.3