[PATCH 1/2] ARM64: mmu: map normal memory Inner Shareable

[Ahmad Fatoum <a.fatoum@pengutronix.de>]

From: Ahmad Fatoum <a.fatoum@barebox.org>

Commit 77446c78219e ("ARM: aarch64: mmu: use PTE_* definitions from
U-Boot") back in 2018 was meant to only switch to the U-Boot macro names,
but it also changed CACHED_MEM from Inner Shareable (PMD_SECT_S, 3 << 8)
to Outer Shareable. TCR was left at Inner Shareable, so since then, the
page table walker reads our translation tables Inner Shareable, while we
write them Outer Shareable.

All of Linux[1], U-Boot's generic ARMv8 code[2] (except for SoC memory maps,
like i.MX8M, which uses Outer Shareable), TF-A[3] and OP-TEE[4] all map
normal memory Inner Shareable. TF-A and OP-TEE run on the same core and
access the memory we pass them without cache maintenance, which the Arm
ARM[5] only guarantees to be coherent if the shareability matches.

Neither mismatch is assumed to have caused issues: we clean and invalidate
page table entries after each update anyway and the Cortex-A53, likely
our most used ARMv8 core, has a PIPT data cache without shareability in
its tags[6], so both mappings hit the same lines.

Hardware-coherent DMA, which we only rely on for Layerscape and virtio
and soon Agilex 5 would be affected if an SoC didn't extend the Inner
Shareable domain to the coherent masters, but this is assumed to be
fine as Linux would also use Inner Shareable for them.

Therefore, let's switch CACHED_MEM back to Inner Shareable.

[1]: Linux v6.18, PTE_SHARED and TCR_SHARED in
     arch/arm64/include/asm/pgtable-hwdef.h
[2]: U-Boot v2026.10, get_tcr() and mmu_map_region() in
     arch/arm/cpu/armv8/cache_v8.c
[3]: TF-A v2.15.0, xlat_desc() in lib/xlat_tables_v2/xlat_tables_core.c
     and setup_mmu_cfg() in lib/xlat_tables_v2/aarch64/xlat_tables_arch.c
[4]: OP-TEE 4.10.0, mattr_to_desc() and core_init_mmu_regs() in
     core/arch/arm/mm/core_mmu_lpae.c
[5]: Arm DDI 0487M.d, B2.11 Mismatched memory attributes, B2-331f.
[6]: Arm DDI 0500J, Cortex-A53 TRM, 2.1.6 Data side memory system, 2-4
     and 6.7.1 Data cache tag and data encoding, 6-14

Fixes: 77446c78219e ("ARM: aarch64: mmu: use PTE_* definitions from U-Boot")
Assisted-by: Claude:opus-5.5
Signed-off-by: Ahmad Fatoum <a.fatoum@barebox.org>
---
While a fix, I am not in a hurry to get this merged. next is fine to get
some more testing.
---
 arch/arm/cpu/mmu_64.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/cpu/mmu_64.h b/arch/arm/cpu/mmu_64.h
index ad7c1bde5631..6cc28908b59a 100644
--- a/arch/arm/cpu/mmu_64.h
+++ b/arch/arm/cpu/mmu_64.h
@@ -5,7 +5,7 @@
 typedef u64 mmu_addr_t;
 
 #define CACHED_MEM      (PTE_BLOCK_MEMTYPE(MT_NORMAL) | \
-			 PTE_BLOCK_OUTER_SHARE | \
+			 PTE_BLOCK_INNER_SHARE | \
 			 PTE_BLOCK_AF)
 #define UNCACHED_MEM    (PTE_BLOCK_MEMTYPE(MT_DEVICE_nGnRnE) | \
 			 PTE_BLOCK_OUTER_SHARE | \
-- 
2.47.3