Re: reset / watchdog on an imx7d soc

[Giorgio Dal Molin <giorgio.nicole@arcor.de>]

Hi,

> On June 29, 2020 at 6:39 PM Fabio Estevam <festevam@gmail.com> wrote:
> 
> 
> Hi Giorgio,
> 
> On Mon, Jun 29, 2020 at 1:33 PM Giorgio Dal Molin
> <giorgio.nicole@arcor.de> wrote:
> 
> > U-Boot configures the ddr3 with c code in its board code 'lowlevel.c'.
> > Looking at the code I noticed this special treatment:
> >
> > static void spl_dram_init(void)
> > {
> > ...
> >         /*
> >          * Make sure that both aresetn/core_ddrc_rstn and preset/PHY reset
> >          * bits are set after WDOG reset event. DDRC_PRST can only be
> >          * released when DDRC clock inputs are stable for at least 30 cycles.
> >          */
> >         writel(SRC_DDRC_RCR_DDRC_CORE_RST_MASK | SRC_DDRC_RCR_DDRC_PRST_MASK, &src_regs->ddrc_rcr);
> >         udelay(500);
> > ...
> >
> > This writel() set both reset bits, the DDRC_CORE (0x2) and the DDRC_PRST (0x1) of the SRC
> > register 0x30391000.
> > Unfortunately, if I try also to set both bits in my DCD table then barebox doesn't boot anymore;
> > I also tried to port the uboot spl_dram_init(void) to my barebox lowlevel.c and I could eventually
> > boot barebox with an empty DCD but still adding the second bit (SRC_DDRC_RCR_DDRC_PRST_MASK)
> > hangs the soc.
> 
> Does it help if you try to apply this U-Boot commit to Barebox?
> https://gitlab.denx.de/u-boot/u-boot/-/commit/0e06d63d195670f5181958f43216d7106c05357f

I've made some more tests with the imx7d and found that the following DCD sequence:

wm 32 0x30391000		0x00000003  // <== added this write
wm 32 0x30391000		0x00000002
...

have an (unreliable) effect: I can now some time reboot barebox with a 'reset'
command and after the reboot I can see the correct reset reason on the serial console:

barebox 2020.06.0-00327-g712fde835-dirty #2 Wed Jul 1 10:21:11 CEST 2020

Board: Kontron SMARC-sAMX7
detected i.MX7d revision 1.3
i.MX reset reason POR (SRSR: 0x00000001)
...

samx7: /
samx7: / reset 

barebox 2020.06.0-00327-g712fde835-dirty #2 Wed Jul 1 10:21:11 CEST 2020

Board: Kontron SMARC-sAMX7
detected i.MX7d revision 1.3
i.MX reset reason WDG (SRSR: 0x00000010)
mdio_bus: miibus0: probed
...

samx7: /


This is the first time I see a reset working on my imx7 module with barebox; the
problem is now that the reboot process is not reliable: it works a couple of times
(not deterministic) and then it hangs the soc forcing me to push the reset button.

As a possible fix I tried adding some 'nop' in the DCD around the two wm 32 to simulate
a delay but it makes no difference.

giorgio

> 
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