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From: Ahmad Fatoum <a.fatoum@pengutronix.de>
To: Michael Riesch <michael.riesch@wolfvision.net>,
	barebox@lists.infradead.org
Cc: Thomas Haemmerle <thomas.haemmerle@wolfvision.net>
Subject: Re: [PATCH 1/2] gpio: add driver for xilinx zynq and zynqmp
Date: Mon, 13 Sep 2021 18:43:34 +0200	[thread overview]
Message-ID: <99e26c81-6233-5708-e850-f2ee0779cca8@pengutronix.de> (raw)
In-Reply-To: <20210913152536.27073-2-michael.riesch@wolfvision.net>

On 13.09.21 17:25, Michael Riesch wrote:
> From: Thomas Haemmerle <thomas.haemmerle@wolfvision.net>
> 
> Port the driver for the Xilinx Zynq/Zynq UltraScale+ MPSoC architecture
> to barebox (based on the Linux driver).
> 
> Signed-off-by: Thomas Haemmerle <thomas.haemmerle@wolfvision.net>
> [apply format fixes]
> Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
> ---
>  arch/arm/Kconfig         |   2 +
>  drivers/gpio/Kconfig     |   6 +
>  drivers/gpio/Makefile    |   1 +
>  drivers/gpio/gpio-zynq.c | 453 +++++++++++++++++++++++++++++++++++++++
>  4 files changed, 462 insertions(+)
>  create mode 100644 drivers/gpio/gpio-zynq.c
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index c7ab16688..a8b7bdeaa 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -248,6 +248,7 @@ config ARCH_ZYNQ
>  	bool "Xilinx Zynq-based boards"
>  	select HAS_DEBUG_LL
>  	select PBL_IMAGE
> +	select GPIOLIB
>  
>  config ARCH_ZYNQMP
>  	bool "Xilinx ZynqMP-based boards"
> @@ -258,6 +259,7 @@ config ARCH_ZYNQMP
>  	select COMMON_CLK
>  	select COMMON_CLK_OF_PROVIDER
>  	select CLKDEV_LOOKUP
> +	select GPIOLIB
>  	select OFDEVICE
>  	select OFTREE
>  	select RELOCATABLE
> diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
> index 98a44fbbb..295426d4b 100644
> --- a/drivers/gpio/Kconfig
> +++ b/drivers/gpio/Kconfig
> @@ -183,6 +183,12 @@ config GPIO_LIBFTDI1
>  	bool "libftdi1 driver"
>  	depends on SANDBOX
>  
> +config GPIO_ZYNQ
> +	tristate "Xilinx Zynq GPIO support"
> +	depends on ARCH_ZYNQ || ARCH_ZYNQMP

|| COMPILE_TEST
depends on OFDEVICE

> +	help
> +	  Say yes here to support Xilinx Zynq GPIO controller.

Could you enable this in the defconfig or add
a default y if ARCH_ZYNQ || ARCH_ZYNQMP?

> +
>  endmenu
>  
>  endif
> diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
> index 638cbb19a..905950a85 100644
> --- a/drivers/gpio/Makefile
> +++ b/drivers/gpio/Makefile
> @@ -25,3 +25,4 @@ obj-$(CONFIG_GPIO_VF610)	+= gpio-vf610.o
>  obj-$(CONFIG_GPIO_RASPBERRYPI_EXP) += gpio-raspberrypi-exp.o
>  obj-$(CONFIG_GPIO_SIFIVE)	+= gpio-sifive.o
>  obj-$(CONFIG_GPIO_STARFIVE)	+= gpio-starfive-vic.o
> +obj-$(CONFIG_GPIO_ZYNQ)		+= gpio-zynq.o
> diff --git a/drivers/gpio/gpio-zynq.c b/drivers/gpio/gpio-zynq.c
> new file mode 100644
> index 000000000..156c2e83f
> --- /dev/null
> +++ b/drivers/gpio/gpio-zynq.c
> @@ -0,0 +1,453 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * Xilinx Zynq GPIO device driver
> + *
> + * Copyright (C) 2009 - 2014 Xilinx, Inc.
> + *
> + * Based on the Linux kernel driver (drivers/gpio/gpio-zynq.c).
> + */
> +
> +#include <common.h>
> +#include <errno.h>
> +#include <gpio.h>
> +#include <init.h>
> +#include <io.h>
> +#include <of.h>
> +
> +/* Maximum banks */
> +#define ZYNQ_GPIO_MAX_BANK	     4
> +#define ZYNQMP_GPIO_MAX_BANK	     6
> +
> +#define ZYNQ_GPIO_BANK0_NGPIO	     32
> +#define ZYNQ_GPIO_BANK1_NGPIO	     22
> +#define ZYNQ_GPIO_BANK2_NGPIO	     32
> +#define ZYNQ_GPIO_BANK3_NGPIO	     32
> +
> +#define ZYNQMP_GPIO_BANK0_NGPIO	     26
> +#define ZYNQMP_GPIO_BANK1_NGPIO	     26
> +#define ZYNQMP_GPIO_BANK2_NGPIO	     26
> +#define ZYNQMP_GPIO_BANK3_NGPIO	     32
> +#define ZYNQMP_GPIO_BANK4_NGPIO	     32
> +#define ZYNQMP_GPIO_BANK5_NGPIO	     32
> +
> +#define ZYNQ_GPIO_NR_GPIOS	     118
> +#define ZYNQMP_GPIO_NR_GPIOS	     174
> +
> +#define ZYNQ_GPIO_BANK0_PIN_MIN(str) 0
> +#define ZYNQ_GPIO_BANK0_PIN_MAX(str)                                           \
> +	(ZYNQ_GPIO_BANK0_PIN_MIN(str) + ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
> +#define ZYNQ_GPIO_BANK1_PIN_MIN(str) (ZYNQ_GPIO_BANK0_PIN_MAX(str) + 1)
> +#define ZYNQ_GPIO_BANK1_PIN_MAX(str)                                           \
> +	(ZYNQ_GPIO_BANK1_PIN_MIN(str) + ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
> +#define ZYNQ_GPIO_BANK2_PIN_MIN(str) (ZYNQ_GPIO_BANK1_PIN_MAX(str) + 1)
> +#define ZYNQ_GPIO_BANK2_PIN_MAX(str)                                           \
> +	(ZYNQ_GPIO_BANK2_PIN_MIN(str) + ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
> +#define ZYNQ_GPIO_BANK3_PIN_MIN(str) (ZYNQ_GPIO_BANK2_PIN_MAX(str) + 1)
> +#define ZYNQ_GPIO_BANK3_PIN_MAX(str)                                           \
> +	(ZYNQ_GPIO_BANK3_PIN_MIN(str) + ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
> +#define ZYNQ_GPIO_BANK4_PIN_MIN(str) (ZYNQ_GPIO_BANK3_PIN_MAX(str) + 1)
> +#define ZYNQ_GPIO_BANK4_PIN_MAX(str)                                           \
> +	(ZYNQ_GPIO_BANK4_PIN_MIN(str) + ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
> +#define ZYNQ_GPIO_BANK5_PIN_MIN(str) (ZYNQ_GPIO_BANK4_PIN_MAX(str) + 1)
> +#define ZYNQ_GPIO_BANK5_PIN_MAX(str)                                           \
> +	(ZYNQ_GPIO_BANK5_PIN_MIN(str) + ZYNQ##str##_GPIO_BANK5_NGPIO - 1)
> +
> +/* Register offsets for the GPIO device */
> +/* LSW Mask & Data -WO */
> +#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK))
> +/* MSW Mask & Data -WO */
> +#define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK))
> +/* Data Register-RW */
> +#define ZYNQ_GPIO_DATA_OFFSET(BANK)	(0x040 + (4 * BANK))
> +#define ZYNQ_GPIO_DATA_RO_OFFSET(BANK)	(0x060 + (4 * BANK))
> +/* Direction mode reg-RW */
> +#define ZYNQ_GPIO_DIRM_OFFSET(BANK)	(0x204 + (0x40 * BANK))
> +/* Output enable reg-RW */
> +#define ZYNQ_GPIO_OUTEN_OFFSET(BANK)	(0x208 + (0x40 * BANK))
> +/* Interrupt mask reg-RO */
> +#define ZYNQ_GPIO_INTMASK_OFFSET(BANK)	(0x20C + (0x40 * BANK))
> +/* Interrupt enable reg-WO */
> +#define ZYNQ_GPIO_INTEN_OFFSET(BANK)	(0x210 + (0x40 * BANK))
> +/* Interrupt disable reg-WO */
> +#define ZYNQ_GPIO_INTDIS_OFFSET(BANK)	(0x214 + (0x40 * BANK))
> +/* Interrupt status reg-RO */
> +#define ZYNQ_GPIO_INTSTS_OFFSET(BANK)	(0x218 + (0x40 * BANK))
> +/* Interrupt type reg-RW */
> +#define ZYNQ_GPIO_INTTYPE_OFFSET(BANK)	(0x21C + (0x40 * BANK))
> +/* Interrupt polarity reg-RW */
> +#define ZYNQ_GPIO_INTPOL_OFFSET(BANK)	(0x220 + (0x40 * BANK))
> +/* Interrupt on any, reg-RW */
> +#define ZYNQ_GPIO_INTANY_OFFSET(BANK)	(0x224 + (0x40 * BANK))
> +
> +/* Disable all interrupts mask */
> +#define ZYNQ_GPIO_IXR_DISABLE_ALL	0xFFFFFFFF
> +
> +/* Mid pin number of a bank */
> +#define ZYNQ_GPIO_MID_PIN_NUM		16
> +
> +/* GPIO upper 16 bit mask */
> +#define ZYNQ_GPIO_UPPER_MASK		0xFFFF0000
> +
> +/* set to differentiate zynq from zynqmp, 0=zynqmp, 1=zynq */
> +#define ZYNQ_GPIO_QUIRK_IS_ZYNQ		BIT(0)
> +#define GPIO_QUIRK_DATA_RO_BUG		BIT(1)
> +
> +/**
> + * struct zynq_gpio - GPIO device private data structure
> + * @chip:	instance of the gpio_chip
> + * @base_addr:	base address of the GPIO device
> + * @p_data:	pointer to platform data
> + */
> +struct zynq_gpio {
> +	struct gpio_chip chip;
> +	void __iomem *base_addr;
> +	const struct zynq_platform_data *p_data;
> +};
> +
> +/**
> + * struct zynq_platform_data - Zynq GPIO platform data structure
> + * @quirks:	Flags is used to identify the platform
> + * @ngpio:	max number of gpio pins
> + * @max_bank:	maximum number of gpio banks
> + * @bank_min:	this array represents bank's min pin
> + * @bank_max:	this array represents bank's max pin
> + */
> +struct zynq_platform_data {
> +	u32 quirks;
> +	u16 ngpio;
> +	int max_bank;
> +	int bank_min[ZYNQMP_GPIO_MAX_BANK];
> +	int bank_max[ZYNQMP_GPIO_MAX_BANK];
> +};
> +
> +/**
> + * zynq_gpio_is_zynq - Test if HW is Zynq or ZynqMP
> + * @gpio:	Pointer to driver data struct
> + *
> + * Return: 0 if ZynqMP, 1 if Zynq.
> + */
> +static int zynq_gpio_is_zynq(struct zynq_gpio *gpio)
> +{
> +	return !!(gpio->p_data->quirks & ZYNQ_GPIO_QUIRK_IS_ZYNQ);
> +}
> +
> +/**
> + * gpio_data_ro_bug - Test if HW bug exists or not
> + * @gpio:       Pointer to driver data struct
> + *
> + * Return: 0 if bug does not exist, 1 if bug exists.
> + */
> +static int gpio_data_ro_bug(struct zynq_gpio *gpio)
> +{
> +	return !!(gpio->p_data->quirks & GPIO_QUIRK_DATA_RO_BUG);
> +}
> +
> +/**
> + * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank
> + * for a given pin in the GPIO device
> + * @pin_num:	gpio pin number within the device
> + * @bank_num:	an output parameter used to return the bank number of the gpio
> + *		pin
> + * @bank_pin_num: an output parameter used to return pin number within a bank
> + *		  for the given gpio pin
> + * @gpio:	gpio device data structure
> + *
> + * Returns the bank number and pin offset within the bank.
> + */
> +static int zynq_gpio_get_bank_pin(unsigned int pin_num, unsigned int *bank_num,
> +				  unsigned int *bank_pin_num,
> +				  struct zynq_gpio *gpio)
> +{
> +	int bank;
> +
> +	for (bank = 0; bank < gpio->p_data->max_bank; bank++) {
> +		if ((pin_num >= gpio->p_data->bank_min[bank]) &&
> +		    (pin_num <= gpio->p_data->bank_max[bank])) {
> +			*bank_num = bank;
> +			*bank_pin_num = pin_num - gpio->p_data->bank_min[bank];
> +			return 0;
> +		}
> +	}
> +
> +	*bank_num = 0;
> +	*bank_pin_num = 0;
> +	return -ENODEV;
> +}
> +
> +/**
> + * zynq_gpio_get_value - Get the state of the specified pin of GPIO device
> + * @chip:	gpio_chip instance to be worked on
> + * @pin:	gpio pin number within the device
> + *
> + * This function reads the state of the specified pin of the GPIO device.
> + *
> + * Return: 0 if the pin is low, 1 if pin is high.
> + */
> +static int zynq_gpio_get_value(struct gpio_chip *chip, unsigned int pin)
> +{
> +	u32 data;
> +	unsigned int bank_num, bank_pin_num;
> +	struct zynq_gpio *gpio = container_of(chip, struct zynq_gpio, chip);
> +
> +	if (zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio) < 0)
> +		return -EINVAL;
> +
> +	if (gpio_data_ro_bug(gpio)) {
> +		if (zynq_gpio_is_zynq(gpio)) {
> +			if (bank_num <= 1) {
> +				data = readl_relaxed(
> +					gpio->base_addr +
> +					ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
> +			} else {
> +				data = readl_relaxed(
> +					gpio->base_addr +
> +					ZYNQ_GPIO_DATA_OFFSET(bank_num));
> +			}
> +		} else {
> +			if (bank_num <= 2) {
> +				data = readl_relaxed(
> +					gpio->base_addr +
> +					ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
> +			} else {
> +				data = readl_relaxed(
> +					gpio->base_addr +
> +					ZYNQ_GPIO_DATA_OFFSET(bank_num));
> +			}
> +		}
> +	} else {
> +		data = readl_relaxed(gpio->base_addr +
> +				     ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
> +	}
> +	return (data >> bank_pin_num) & 1;
> +}
> +
> +/**
> + * zynq_gpio_set_value - Modify the state of the pin with specified value
> + * @chip:	gpio_chip instance to be worked on
> + * @pin:	gpio pin number within the device
> + * @state:	value used to modify the state of the specified pin
> + *
> + * This function calculates the register offset (i.e to lower 16 bits or
> + * upper 16 bits) based on the given pin number and sets the state of a
> + * gpio pin to the specified value. The state is either 0 or non-zero.
> + */
> +static void zynq_gpio_set_value(struct gpio_chip *chip, unsigned int pin,
> +				int state)
> +{
> +	unsigned int reg_offset, bank_num, bank_pin_num;
> +	struct zynq_gpio *gpio = container_of(chip, struct zynq_gpio, chip);
> +
> +	if (zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio) < 0)
> +		return;
> +
> +	if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) {
> +		bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM;
> +		reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num);
> +	} else {
> +		reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num);
> +	}
> +
> +	/*
> +	 * get the 32 bit value to be written to the mask/data register where
> +	 * the upper 16 bits is the mask and lower 16 bits is the data
> +	 */
> +	state = !!state;
> +	state = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) &
> +		((state << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK);
> +
> +	writel_relaxed(state, gpio->base_addr + reg_offset);
> +}
> +
> +/**
> + * zynq_gpio_dir_in - Set the direction of the specified GPIO pin as input
> + * @chip:	gpio_chip instance to be worked on
> + * @pin:	gpio pin number within the device
> + *
> + * This function uses the read-modify-write sequence to set the direction of
> + * the gpio pin as input.
> + *
> + * Return: 0 always
> + */
> +static int zynq_gpio_dir_in(struct gpio_chip *chip, unsigned int pin)
> +{
> +	u32 reg;
> +	unsigned int bank_num, bank_pin_num;
> +	struct zynq_gpio *gpio = container_of(chip, struct zynq_gpio, chip);
> +
> +	if (zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio) < 0)
> +		return -EINVAL;
> +	/*
> +	 * On zynq bank 0 pins 7 and 8 are special and cannot be used
> +	 * as inputs.
> +	 */
> +	if (zynq_gpio_is_zynq(gpio) && bank_num == 0 &&
> +	    (bank_pin_num == 7 || bank_pin_num == 8))
> +		return -EINVAL;
> +
> +	/* clear the bit in direction mode reg to set the pin as input */
> +	reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
> +	reg &= ~BIT(bank_pin_num);
> +	writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
> +
> +	return 0;
> +}
> +
> +/**
> + * zynq_gpio_dir_out - Set the direction of the specified GPIO pin as output
> + * @chip:	gpio_chip instance to be worked on
> + * @pin:	gpio pin number within the device
> + * @state:	value to be written to specified pin
> + *
> + * This function sets the direction of specified GPIO pin as output, configures
> + * the Output Enable register for the pin and uses zynq_gpio_set to set
> + * the state of the pin to the value specified.
> + *
> + * Return: 0 always
> + */
> +static int zynq_gpio_dir_out(struct gpio_chip *chip, unsigned int pin,
> +			     int state)
> +{
> +	u32 reg;
> +	unsigned int bank_num, bank_pin_num;
> +	struct zynq_gpio *gpio = container_of(chip, struct zynq_gpio, chip);
> +
> +	if (zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio) < 0)
> +		return -EINVAL;
> +
> +	/* set the GPIO pin as output */
> +	reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
> +	reg |= BIT(bank_pin_num);
> +	writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
> +
> +	/* configure the output enable reg for the pin */
> +	reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
> +	reg |= BIT(bank_pin_num);
> +	writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
> +
> +	/* set the state of the pin */
> +	zynq_gpio_set_value(chip, pin, state);
> +	return 0;
> +}
> +
> +/**
> + * zynq_gpio_get_direction - Read the direction of the specified GPIO pin
> + * @chip:	gpio_chip instance to be worked on
> + * @pin:	gpio pin number within the device
> + *
> + * This function returns the direction of the specified GPIO.
> + *
> + * Return: 0 for output, 1 for input
> + */
> +static int zynq_gpio_get_direction(struct gpio_chip *chip, unsigned int pin)
> +{
> +	u32 reg;
> +	unsigned int bank_num, bank_pin_num;
> +	struct zynq_gpio *gpio = container_of(chip, struct zynq_gpio, chip);
> +
> +	if (zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio) < 0)
> +		return -EINVAL;
> +
> +	reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
> +
> +	return !(reg & BIT(bank_pin_num));
> +}
> +
> +static struct gpio_ops zynq_gpio_ops = {
> +	.direction_input = zynq_gpio_dir_in,
> +	.direction_output = zynq_gpio_dir_out,
> +	.get = zynq_gpio_get_value,
> +	.set = zynq_gpio_set_value,
> +	.get_direction = zynq_gpio_get_direction,
> +};
> +
> +static int zynqmp_gpio_probe(struct device_d *dev)
> +{
> +	struct resource *iores;
> +	struct zynq_gpio *gpio;
> +	struct zynq_platform_data *p_data;
> +	int ret;
> +
> +	ret = dev_get_drvdata(dev, (const void **)&p_data);
> +	if (ret)
> +		return ret;

Please use device_get_match_data() instead. dev_get_drvdata is
error prone and will eventually be phased out.

> +
> +	gpio = xzalloc(sizeof(*gpio));
> +	iores = dev_request_mem_resource(dev, 0);
> +	if (IS_ERR(iores)) {
> +		printk("dev_request_mem_resource\n");

I'd drop this, an EBUSY is generally understood to mean memory couldn't be reserved.
If you want to keep it, make it a dev_warn and a proper sentence.

> +		return PTR_ERR(iores);
> +	}
> +
> +	if (dev->id < 0) {

This is always true for OF-probed devices, you can remove the check and drop
the other branch.

> +		gpio->chip.base = of_alias_get_id(dev->device_node, "gpio");
> +		if (gpio->chip.base < 0) {

base == -1 means allocating sequentially. That's what the Linux driver
does in absence of aliases.

Why not do it likewise and drop this if condition as well as the
second patch?

> +			ret = gpio->chip.base;
> +			printk("Failed to get GPIO alias\n");

Make it a dev_warn if you decide to keep it.

> +			goto free_gpio;
> +		}
> +	} else {
> +		gpio->chip.base = dev->id;
> +	}
> +
> +	gpio->base_addr = IOMEM(iores->start);
> +	gpio->chip.ops = &zynq_gpio_ops;
> +	gpio->chip.ngpio = p_data->ngpio;
> +	gpio->chip.dev = dev;
> +	gpio->p_data = p_data;
> +
> +	return gpiochip_add(&gpio->chip);
> +free_gpio:
> +	free(gpio);
> +	return ret;
> +}
> +
> +static const struct zynq_platform_data zynqmp_gpio_def = {
> +	.quirks = GPIO_QUIRK_DATA_RO_BUG,
> +	.ngpio = ZYNQMP_GPIO_NR_GPIOS,
> +	.max_bank = ZYNQMP_GPIO_MAX_BANK,
> +	.bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(MP),
> +	.bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(MP),
> +	.bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(MP),
> +	.bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(MP),
> +	.bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(MP),
> +	.bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(MP),
> +	.bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(MP),
> +	.bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(MP),
> +	.bank_min[4] = ZYNQ_GPIO_BANK4_PIN_MIN(MP),
> +	.bank_max[4] = ZYNQ_GPIO_BANK4_PIN_MAX(MP),
> +	.bank_min[5] = ZYNQ_GPIO_BANK5_PIN_MIN(MP),
> +	.bank_max[5] = ZYNQ_GPIO_BANK5_PIN_MAX(MP),
> +};
> +
> +static const struct zynq_platform_data zynq_gpio_def = {
> +	.quirks = ZYNQ_GPIO_QUIRK_IS_ZYNQ | GPIO_QUIRK_DATA_RO_BUG,
> +	.ngpio = ZYNQ_GPIO_NR_GPIOS,
> +	.max_bank = ZYNQ_GPIO_MAX_BANK,
> +	.bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(),
> +	.bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(),
> +	.bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(),
> +	.bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(),
> +	.bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(),
> +	.bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(),
> +	.bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(),
> +	.bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(),
> +};
> +
> +static const struct of_device_id zynq_gpio_of_match[] = {
> +	{ .compatible = "xlnx,zynq-gpio-1.0", .data = &zynq_gpio_def },
> +	{ .compatible = "xlnx,zynqmp-gpio-1.0", .data = &zynqmp_gpio_def },
> +	{ /* end of table */ }
> +};
> +
> +static struct driver_d zynqmp_gpio_driver = {
> +	.name = "zynqmp-gpio",
> +	.probe = zynqmp_gpio_probe,
> +	.of_compatible = DRV_OF_COMPAT(zynq_gpio_of_match),

DRV_OF_COMPAT is not needed for OF-only driver.

> +};
> +
> +static int gpio_zynqmp_init(void)
> +{
> +	platform_driver_register(&zynqmp_gpio_driver);
> +	return 0;
> +}
> +postcore_initcall(gpio_zynqmp_init);

postcore_platform_driver can be used here.

> 


Cheers,
Ahmad


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  reply	other threads:[~2021-09-13 17:02 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-13 15:25 [PATCH 0/2] " Michael Riesch
2021-09-13 15:25 ` [PATCH 1/2] " Michael Riesch
2021-09-13 16:43   ` Ahmad Fatoum [this message]
2021-09-13 15:25 ` [PATCH 2/2] arm: dts: zynqmp: add alias gpio0 to zcu104 and zcu106 boards Michael Riesch
2021-09-13 16:23   ` Ahmad Fatoum

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