From: Ahmad Fatoum <a.fatoum@pengutronix.de>
To: Sascha Hauer <sha@pengutronix.de>, Ahmad Fatoum <ahmad@a3f.at>
Cc: barebox@lists.infradead.org, Yann Sionneau <ysionneau@kalray.eu>
Subject: Re: [PATCH master] RISC-V: cpu: fix build with CONFIG_RISCV_EXCEPTIONS=n
Date: Mon, 3 Jan 2022 11:25:47 +0100 [thread overview]
Message-ID: <d7b38b7a-e6ef-d96d-557d-1fa25a979276@pengutronix.de> (raw)
In-Reply-To: <20211207090615.GF28260@pengutronix.de>
Hello Sascha,
On 07.12.21 10:06, Sascha Hauer wrote:
> On Sat, Dec 04, 2021 at 02:08:54PM +0100, Ahmad Fatoum wrote:
>> Building without CONFIG_RISCV_EXCEPTIONS causes a compile error, because
>> of a definition mismatch. data_abort_mask is a no-op without exception
>> support, but interrupt.c defines it as a different type of symbol. Skip
>> interrupt.c compilation to fix the build error.
I don't find this patch in either master or next.
Can you push it?
Thanks,
Ahmad
>>
>> Reported-by: Yann Sionneau <ysionneau@kalray.eu>
>> Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
>> ---
>> arch/riscv/cpu/Makefile | 2 ++
>> 1 file changed, 2 insertions(+)
>
> Applied, thanks
>
> Sascha
>
>>
>> diff --git a/arch/riscv/cpu/Makefile b/arch/riscv/cpu/Makefile
>> index 717baaaaa727..d79bafc6f142 100644
>> --- a/arch/riscv/cpu/Makefile
>> +++ b/arch/riscv/cpu/Makefile
>> @@ -2,6 +2,8 @@
>>
>> obj-y += core.o time.o
>> obj-$(CONFIG_HAS_DMA) += dma.o
>> +ifeq ($(CONFIG_RISCV_EXCEPTIONS),y)
>> obj-pbl-$(CONFIG_RISCV_M_MODE) += mtrap.o
>> obj-pbl-$(CONFIG_RISCV_S_MODE) += strap.o
>> obj-pbl-y += interrupts.o
>> +endif
>> --
>> 2.33.0
>>
>>
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>> http://lists.infradead.org/mailman/listinfo/barebox
>>
>
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prev parent reply other threads:[~2022-01-03 10:27 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-04 13:08 Ahmad Fatoum
2021-12-07 9:06 ` Sascha Hauer
2022-01-03 10:25 ` Ahmad Fatoum [this message]
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