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From: Ahmad Fatoum <a.fatoum@pengutronix.de>
To: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Barebox List <barebox@lists.infradead.org>
Subject: Re: [PATCH 3/3] arm64: Set PXN/UXN attributes for uncached mem
Date: Tue, 31 Mar 2020 12:10:24 +0200	[thread overview]
Message-ID: <dfd65e1d-59cd-58f6-8810-4e2cfbec5d5c@pengutronix.de> (raw)
In-Reply-To: <20200331092047.GN27288@pengutronix.de>

Hi,

On 3/31/20 11:20 AM, Sascha Hauer wrote:
> On Tue, Mar 31, 2020 at 11:01:35AM +0200, Sascha Hauer wrote:
>> On Tue, Mar 31, 2020 at 10:33:54AM +0200, Ahmad Fatoum wrote:
>>>
>>>
>>> On 3/31/20 10:01 AM, Sascha Hauer wrote:
>>>> The attributes should be set to avoid speculative access to memory-mapped
>>>> peripherals.
>>>>
>>>> The patch has been tested with:
>>>>
>>>> noinline unsigned long nox(void)
>>>> {
>>>> 	return get_pc();
>>>> }
>>>>
>>>> static void xn_test(void)
>>>> {
>>>> 	void *adr = (void *)SOME_SRAM_ADDRESS;
>>>> 	unsigned long ret;
>>>> 	unsigned long (*fn)(void) = adr;
>>>>
>>>> 	memcpy(adr, nox, 0x1000);
>>>>
>>>> 	sync_caches_for_execution();
>>>>
>>>> 	ret = fn();
>>>> 	printf("pc: 0x%08lx\n", ret);
>>>> }
>>>>
>>>> Without this patch nox() gets executed in SRAM, with it runs into a
>>>> abort as expected.
>>>>
>>>> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
>>>> ---
>>>>  arch/arm/cpu/mmu_64.h | 3 ++-
>>>>  1 file changed, 2 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/arch/arm/cpu/mmu_64.h b/arch/arm/cpu/mmu_64.h
>>>> index a2a5477569..f5b7624037 100644
>>>> --- a/arch/arm/cpu/mmu_64.h
>>>> +++ b/arch/arm/cpu/mmu_64.h
>>>> @@ -6,7 +6,8 @@
>>>>  			 PTE_BLOCK_AF)
>>>>  #define UNCACHED_MEM    (PTE_BLOCK_MEMTYPE(MT_DEVICE_nGnRnE) | \
>>>>  			 PTE_BLOCK_OUTER_SHARE | \
>>>> -			 PTE_BLOCK_AF)
>>>> +			 PTE_BLOCK_AF | \
>>>> +			 PTE_BLOCK_UXN)
>>>
>>> Don't we need PXN in EL1?
>>
>> We are not in EL1 currently. What happens if we change the exception
>> level after the MMU setup? In that case we would have to adjust the
>> attributes of the existing page tables when doing so. We are currently
>> not prepared for that so I am not sure how much sense it makes to test
>> for the EL here.
> 
> Hm, this is no reason for not honoring the current EL in the first
> place, I'll update the patch accordingly.

Not understanding what you mean here, but I'll see in v2. :-)

Cheers,
Ahmad

> 
> Sascha
> 
> 

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  reply	other threads:[~2020-03-31 10:10 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-31  8:01 [PATCH 1/3] ARM64: Setup vectors in all lower execption levels Sascha Hauer
2020-03-31  8:01 ` [PATCH 2/3] ARM64: attribute argument to create_sections() is 64bit Sascha Hauer
2020-03-31  8:01 ` [PATCH 3/3] arm64: Set PXN/UXN attributes for uncached mem Sascha Hauer
2020-03-31  8:33   ` Ahmad Fatoum
2020-03-31  9:01     ` Sascha Hauer
2020-03-31  9:20       ` Sascha Hauer
2020-03-31 10:10         ` Ahmad Fatoum [this message]
2020-03-31 10:12   ` [PATCH v2] " Sascha Hauer
2020-03-31 10:18     ` Sascha Hauer
2020-03-31 10:17   ` Sascha Hauer
2020-03-31 10:27     ` Ahmad Fatoum

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