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From: Renaud Barbier <renaud.barbier@abaco.com>
To: barebox@lists.infradead.org
Cc: Renaud Barbier <renaud.barbier@abaco.com>
Subject: [PATCH 1/4] ARM: atomic.h: add 64-bit counter support
Date: Wed, 28 Jul 2021 13:47:05 +0100	[thread overview]
Message-ID: <1627476428-16318-2-git-send-email-renaud.barbier@abaco.com> (raw)
In-Reply-To: <1627476428-16318-1-git-send-email-renaud.barbier@abaco.com>

In preparation for the introduction of the FSL IFC nand driver
for the layerscape CPU, add 64-bit counter support.

Signed-off-by: Renaud Barbier <renaud.barbier@abaco.com>
---
 include/asm-generic/atomic-long.h |  3 +-
 include/asm-generic/atomic.h      | 49 +++++++++++++++++++++++++++++++
 2 files changed, 51 insertions(+), 1 deletion(-)

diff --git a/include/asm-generic/atomic-long.h b/include/asm-generic/atomic-long.h
index 322d510f38..dbb503e758 100644
--- a/include/asm-generic/atomic-long.h
+++ b/include/asm-generic/atomic-long.h
@@ -65,7 +65,7 @@ static inline void atomic_long_sub(long i, atomic_long_t *l)
 
 	atomic64_sub(i, v);
 }
-
+#if 0
 static inline int atomic_long_sub_and_test(long i, atomic_long_t *l)
 {
 	atomic64_t *v = (atomic64_t *)l;
@@ -128,6 +128,7 @@ static inline long atomic_long_add_unless(atomic_long_t *l, long a, long u)
 
 	return (long)atomic64_add_unless(v, a, u);
 }
+#endif
 
 #define atomic_long_inc_not_zero(l) atomic64_inc_not_zero((atomic64_t *)(l))
 
diff --git a/include/asm-generic/atomic.h b/include/asm-generic/atomic.h
index 449cecaabc..6e63b8e8e7 100644
--- a/include/asm-generic/atomic.h
+++ b/include/asm-generic/atomic.h
@@ -11,7 +11,55 @@
 #ifdef CONFIG_SMP
 #error SMP not supported
 #endif
+#define ATOMIC_INIT(i)	{ (i) }
+
+#ifdef CONFIG_64BIT
+typedef struct { s64 counter; } atomic64_t;
+
+#define atomic64_read(v)	((v)->counter)
+#define atomic64_set(v, i)	(((v)->counter) = (i))
+
+static inline void atomic64_add(s64 i, volatile atomic64_t *v)
+{
+	v->counter += i;
+}
+
+static inline void atomic64_sub(s64 i, volatile atomic64_t *v)
+{
+	v->counter -= i;
+}
+
+static inline void atomic64_inc(volatile atomic64_t *v)
+{
+	v->counter += 1;
+}
+
+static inline void atomic64_dec(volatile atomic64_t *v)
+{
+	v->counter -= 1;
+}
+
+static inline int atomic64_dec_and_test(volatile atomic64_t *v)
+{
+	s64 val;
+
+	val = v->counter;
+	v->counter = val -= 1;
+
+	return val == 0;
+}
 
+static inline int atomic64_add_negative(s64 i, volatile atomic64_t *v)
+{
+	s64 val;
+
+	val = v->counter;
+	v->counter = val += i;
+
+	return val < 0;
+}
+
+#else
 typedef struct { volatile int counter; } atomic_t;
 
 #define ATOMIC_INIT(i)	{ (i) }
@@ -63,6 +111,7 @@ static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
 {
 	*addr &= ~mask;
 }
+#endif
 
 /* Atomic operations are already serializing on ARM */
 #define smp_mb__before_atomic_dec()	barrier()
-- 
2.27.0


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  reply	other threads:[~2021-07-28 12:49 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-28 12:47 [PATCH 0/4] NXP IFC nand driver Renaud Barbier
2021-07-28 12:47 ` Renaud Barbier [this message]
2021-07-29  9:58   ` [PATCH 1/4] ARM: atomic.h: add 64-bit counter support Ahmad Fatoum
2021-07-28 12:47 ` [PATCH 2/4] arm: 64-bit device specific operation Renaud Barbier
2021-07-29 10:00   ` Ahmad Fatoum
2021-07-28 12:47 ` [PATCH 3/4] nand: add NXP IFC nand driver Renaud Barbier
2021-07-29 10:11   ` Ahmad Fatoum
2021-07-28 12:47 ` [PATCH 4/4] ls1046ardb: enable IFC NAND Renaud Barbier
2021-07-29 10:13   ` Ahmad Fatoum
2021-07-29 18:19     ` Barbier, Renaud

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