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From: Renaud Barbier <renaud.barbier@abaco.com>
To: barebox@lists.infradead.org
Cc: Renaud Barbier <renaud.barbier@abaco.com>
Subject: [PATCH 4/4] ls1046ardb: enable IFC NAND.
Date: Wed, 28 Jul 2021 13:47:08 +0100
Message-ID: <1627476428-16318-5-git-send-email-renaud.barbier@abaco.com> (raw)
In-Reply-To: <1627476428-16318-1-git-send-email-renaud.barbier@abaco.com>

Set the NAND timings and enable the IFC NAND driver.

Signed-off-by: Renaud Barbier <renaud.barbier@abaco.com>
---
 arch/arm/boards/ls1046ardb/board.c    | 26 ++++++++++++++++++++++++++
 arch/arm/configs/layerscape_defconfig | 12 ++++++++++++
 2 files changed, 38 insertions(+)

diff --git a/arch/arm/boards/ls1046ardb/board.c b/arch/arm/boards/ls1046ardb/board.c
index ef68e9c7f9..5573d5b486 100644
--- a/arch/arm/boards/ls1046ardb/board.c
+++ b/arch/arm/boards/ls1046ardb/board.c
@@ -12,6 +12,7 @@
 #include <linux/sizes.h>
 #include <linux/clk.h>
 #include <linux/clkdev.h>
+#include <linux/fsl_ifc.h>
 #include <asm/system.h>
 #include <mach/layerscape.h>
 #include <mach/bbu.h>
@@ -147,6 +148,31 @@ static int rdb_mem_init(void)
 }
 mem_initcall(rdb_mem_init);
 
+static int rdb_nand_init(void)
+{
+	/* NAND mapping and timings. Only for Linux use. */
+	set_ifc_cspr(IFC_CS0, CSPR_PHYS_ADDR(0x7e800000) | CSPR_PORT_SIZE_8 |
+				CSPR_MSEL_NAND | CSPR_V);
+	set_ifc_csor(IFC_CS0, CSOR_NAND_ECC_ENC_EN | CSOR_NAND_ECC_DEC_EN |
+			CSOR_NAND_ECC_MODE_8 |
+			CSOR_NAND_RAL_3 | CSOR_NAND_PGS_4K |
+			CSOR_NAND_SPRZ_224 |  CSOR_NAND_PB(64) |
+			CSOR_NAND_TRHZ_20);
+	set_ifc_amask(IFC_CS0, IFC_AMASK(64*1024));
+	set_ifc_ftim(IFC_CS0, IFC_FTIM0, FTIM0_NAND_TCCST(0x07) |
+			FTIM0_NAND_TWP(0x18) | FTIM0_NAND_TWCHT(0x07) |
+			FTIM0_NAND_TWH(0x0a));
+	set_ifc_ftim(IFC_CS0, IFC_FTIM1, FTIM1_NAND_TADLE(0x32) |
+			FTIM1_NAND_TWBE(0x39) | FTIM1_NAND_TRR(0x0e)|
+			FTIM1_NAND_TRP(0x18));
+	set_ifc_ftim(IFC_CS0, IFC_FTIM2, FTIM2_NAND_TRAD(0xf) |
+			FTIM2_NAND_TREH(0xa) | FTIM2_NAND_TWHRE(0x1e));
+	set_ifc_ftim(IFC_CS0, IFC_FTIM3, 0);
+
+	return 0;
+}
+core_initcall(rdb_nand_init);
+
 static int rdb_postcore_init(void)
 {
 	if (!of_machine_is_compatible("fsl,ls1046a-rdb"))
diff --git a/arch/arm/configs/layerscape_defconfig b/arch/arm/configs/layerscape_defconfig
index 394cd95c98..5c31c9319d 100644
--- a/arch/arm/configs/layerscape_defconfig
+++ b/arch/arm/configs/layerscape_defconfig
@@ -34,6 +34,10 @@ CONFIG_CMD_GO=y
 CONFIG_CMD_RESET=y
 CONFIG_CMD_UIMAGE=y
 CONFIG_CMD_PARTITION=y
+CONFIG_CMD_MOUNT=y
+CONFIG_CMD_UBI=y
+CONFIG_CMD_UBIFORMAT=y
+CONFIG_CMD_UMOUNT=y
 CONFIG_CMD_EXPORT=y
 CONFIG_CMD_LOADENV=y
 CONFIG_CMD_PRINTENV=y
@@ -69,6 +73,7 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_LED=y
 CONFIG_CMD_SPI=y
+CONFIG_CMD_NAND=y
 CONFIG_CMD_LED_TRIGGER=y
 CONFIG_CMD_WD=y
 CONFIG_CMD_BAREBOX_UPDATE=y
@@ -85,6 +90,11 @@ CONFIG_DP83867_PHY=y
 CONFIG_REALTEK_PHY=y
 CONFIG_NET_DSA_MV88E6XXX=y
 CONFIG_DRIVER_SPI_FSL_QUADSPI=y
+CONFIG_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_MTD_NAND_ECC_SOFT=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
 CONFIG_I2C=y
 CONFIG_I2C_IMX=y
 CONFIG_I2C_MUX=y
@@ -112,5 +122,7 @@ CONFIG_FS_NFS=y
 CONFIG_FS_FAT=y
 CONFIG_FS_FAT_WRITE=y
 CONFIG_FS_FAT_LFN=y
+CONFIG_FS_UBIFS=y
+CONFIG_FS_UBIFS_COMPRESSION_LZO=y
 CONFIG_ZLIB=y
 CONFIG_LZO_DECOMPRESS=y
-- 
2.27.0


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  parent reply	other threads:[~2021-07-28 12:49 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-28 12:47 [PATCH 0/4] NXP IFC nand driver Renaud Barbier
2021-07-28 12:47 ` [PATCH 1/4] ARM: atomic.h: add 64-bit counter support Renaud Barbier
2021-07-29  9:58   ` Ahmad Fatoum
2021-07-28 12:47 ` [PATCH 2/4] arm: 64-bit device specific operation Renaud Barbier
2021-07-29 10:00   ` Ahmad Fatoum
2021-07-28 12:47 ` [PATCH 3/4] nand: add NXP IFC nand driver Renaud Barbier
2021-07-29 10:11   ` Ahmad Fatoum
2021-07-28 12:47 ` Renaud Barbier [this message]
2021-07-29 10:13   ` [PATCH 4/4] ls1046ardb: enable IFC NAND Ahmad Fatoum
2021-07-29 18:19     ` Barbier, Renaud

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