* [PATCH master] ARM: i.MX7: enable caches when booted over USB
@ 2022-09-30 13:37 Johannes Zink
2022-10-04 7:54 ` Marco Felsch
2022-10-10 5:52 ` Sascha Hauer
0 siblings, 2 replies; 5+ messages in thread
From: Johannes Zink @ 2022-09-30 13:37 UTC (permalink / raw)
To: barebox; +Cc: Johannes Zink
From: Ahmad Fatoum <a.fatoum@pengutronix.de>
BootROM on the i.MX7 doesn't set the SMP bit when booted
over serial download. This leads to vastly worse performance
when doing memory-heavy operations in a USB-booted system,
as the caches are not utilized. Example running md5sum over
a 25M image in ramfs:
without patch: 10796ms
with patch: 457ms
This issue isn't unique to the i.MX7, but exists for the i.MX6UL as
well, which also has the Cortex-A7 as CPU. Like with
imx6ul_cpu_lowlevel_init(), adapt imx7_cpu_lowlevel_init() to avoid this
slow down.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Johannes Zink <j.zink@pengutronix.de>
---
arch/arm/mach-imx/cpu_init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/cpu_init.c b/arch/arm/mach-imx/cpu_init.c
index ea36215419..ede2076102 100644
--- a/arch/arm/mach-imx/cpu_init.c
+++ b/arch/arm/mach-imx/cpu_init.c
@@ -49,7 +49,7 @@ void imx6ul_cpu_lowlevel_init(void)
void imx7_cpu_lowlevel_init(void)
{
- arm_cpu_lowlevel_init();
+ cortex_a7_lowlevel_init();
imx_cpu_timer_init(IOMEM(MX7_SYSCNT_CTRL_BASE_ADDR));
}
--
2.30.2
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH master] ARM: i.MX7: enable caches when booted over USB
2022-09-30 13:37 [PATCH master] ARM: i.MX7: enable caches when booted over USB Johannes Zink
@ 2022-10-04 7:54 ` Marco Felsch
2022-10-10 6:32 ` Ahmad Fatoum
2022-10-10 5:52 ` Sascha Hauer
1 sibling, 1 reply; 5+ messages in thread
From: Marco Felsch @ 2022-10-04 7:54 UTC (permalink / raw)
To: Johannes Zink; +Cc: barebox
Hi,
On 22-09-30, Johannes Zink wrote:
> From: Ahmad Fatoum <a.fatoum@pengutronix.de>
>
> BootROM on the i.MX7 doesn't set the SMP bit when booted
> over serial download. This leads to vastly worse performance
> when doing memory-heavy operations in a USB-booted system,
> as the caches are not utilized. Example running md5sum over
> a 25M image in ramfs:
>
> without patch: 10796ms
> with patch: 457ms
>
> This issue isn't unique to the i.MX7, but exists for the i.MX6UL as
> well, which also has the Cortex-A7 as CPU. Like with
> imx6ul_cpu_lowlevel_init(), adapt imx7_cpu_lowlevel_init() to avoid this
> slow down.
>
> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> Signed-off-by: Johannes Zink <j.zink@pengutronix.de>
> ---
> arch/arm/mach-imx/cpu_init.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-imx/cpu_init.c b/arch/arm/mach-imx/cpu_init.c
> index ea36215419..ede2076102 100644
> --- a/arch/arm/mach-imx/cpu_init.c
> +++ b/arch/arm/mach-imx/cpu_init.c
> @@ -49,7 +49,7 @@ void imx6ul_cpu_lowlevel_init(void)
>
> void imx7_cpu_lowlevel_init(void)
> {
> - arm_cpu_lowlevel_init();
> + cortex_a7_lowlevel_init();
Out of curiosity, arm_cpu_lowlevel_init() does a lot more than
cortex_a7_lowlevel_init() e.g. cache invalidation. Is it save to only
call cortex_a7_lowlevel_init() here?
Regards,
Marco
> imx_cpu_timer_init(IOMEM(MX7_SYSCNT_CTRL_BASE_ADDR));
> }
>
> --
> 2.30.2
>
>
>
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH master] ARM: i.MX7: enable caches when booted over USB
2022-10-04 7:54 ` Marco Felsch
@ 2022-10-10 6:32 ` Ahmad Fatoum
0 siblings, 0 replies; 5+ messages in thread
From: Ahmad Fatoum @ 2022-10-10 6:32 UTC (permalink / raw)
To: Marco Felsch, Johannes Zink; +Cc: barebox
On 04.10.22 09:54, Marco Felsch wrote:
> Hi,
>
> On 22-09-30, Johannes Zink wrote:
>> From: Ahmad Fatoum <a.fatoum@pengutronix.de>
>>
>> BootROM on the i.MX7 doesn't set the SMP bit when booted
>> over serial download. This leads to vastly worse performance
>> when doing memory-heavy operations in a USB-booted system,
>> as the caches are not utilized. Example running md5sum over
>> a 25M image in ramfs:
>>
>> without patch: 10796ms
>> with patch: 457ms
>>
>> This issue isn't unique to the i.MX7, but exists for the i.MX6UL as
>> well, which also has the Cortex-A7 as CPU. Like with
>> imx6ul_cpu_lowlevel_init(), adapt imx7_cpu_lowlevel_init() to avoid this
>> slow down.
>>
>> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
>> Signed-off-by: Johannes Zink <j.zink@pengutronix.de>
>> ---
>> arch/arm/mach-imx/cpu_init.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/mach-imx/cpu_init.c b/arch/arm/mach-imx/cpu_init.c
>> index ea36215419..ede2076102 100644
>> --- a/arch/arm/mach-imx/cpu_init.c
>> +++ b/arch/arm/mach-imx/cpu_init.c
>> @@ -49,7 +49,7 @@ void imx6ul_cpu_lowlevel_init(void)
>>
>> void imx7_cpu_lowlevel_init(void)
>> {
>> - arm_cpu_lowlevel_init();
>> + cortex_a7_lowlevel_init();
>
> Out of curiosity, arm_cpu_lowlevel_init() does a lot more than
> cortex_a7_lowlevel_init() e.g. cache invalidation. Is it save to only
> call cortex_a7_lowlevel_init() here?
It's not and this was an oversight. Thanks for catching.
>
> Regards,
> Marco
>
>> imx_cpu_timer_init(IOMEM(MX7_SYSCNT_CTRL_BASE_ADDR));
>> }
>>
>> --
>> 2.30.2
>>
>>
>>
>
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH master] ARM: i.MX7: enable caches when booted over USB
2022-09-30 13:37 [PATCH master] ARM: i.MX7: enable caches when booted over USB Johannes Zink
2022-10-04 7:54 ` Marco Felsch
@ 2022-10-10 5:52 ` Sascha Hauer
2022-10-10 6:35 ` Ahmad Fatoum
1 sibling, 1 reply; 5+ messages in thread
From: Sascha Hauer @ 2022-10-10 5:52 UTC (permalink / raw)
To: Johannes Zink; +Cc: barebox
On Fri, Sep 30, 2022 at 03:37:02PM +0200, Johannes Zink wrote:
> From: Ahmad Fatoum <a.fatoum@pengutronix.de>
>
> BootROM on the i.MX7 doesn't set the SMP bit when booted
> over serial download. This leads to vastly worse performance
> when doing memory-heavy operations in a USB-booted system,
> as the caches are not utilized. Example running md5sum over
> a 25M image in ramfs:
>
> without patch: 10796ms
> with patch: 457ms
>
> This issue isn't unique to the i.MX7, but exists for the i.MX6UL as
> well, which also has the Cortex-A7 as CPU. Like with
> imx6ul_cpu_lowlevel_init(), adapt imx7_cpu_lowlevel_init() to avoid this
> slow down.
>
> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> Signed-off-by: Johannes Zink <j.zink@pengutronix.de>
> ---
> arch/arm/mach-imx/cpu_init.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-imx/cpu_init.c b/arch/arm/mach-imx/cpu_init.c
> index ea36215419..ede2076102 100644
> --- a/arch/arm/mach-imx/cpu_init.c
> +++ b/arch/arm/mach-imx/cpu_init.c
> @@ -49,7 +49,7 @@ void imx6ul_cpu_lowlevel_init(void)
>
> void imx7_cpu_lowlevel_init(void)
> {
> - arm_cpu_lowlevel_init();
> + cortex_a7_lowlevel_init();
Why do you remove the call to arm_cpu_lowlevel_init() here?
Sascha
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH master] ARM: i.MX7: enable caches when booted over USB
2022-10-10 5:52 ` Sascha Hauer
@ 2022-10-10 6:35 ` Ahmad Fatoum
0 siblings, 0 replies; 5+ messages in thread
From: Ahmad Fatoum @ 2022-10-10 6:35 UTC (permalink / raw)
To: Sascha Hauer, Johannes Zink; +Cc: barebox
On 10.10.22 07:52, Sascha Hauer wrote:
> On Fri, Sep 30, 2022 at 03:37:02PM +0200, Johannes Zink wrote:
>> From: Ahmad Fatoum <a.fatoum@pengutronix.de>
>>
>> BootROM on the i.MX7 doesn't set the SMP bit when booted
>> over serial download. This leads to vastly worse performance
>> when doing memory-heavy operations in a USB-booted system,
>> as the caches are not utilized. Example running md5sum over
>> a 25M image in ramfs:
>>
>> without patch: 10796ms
>> with patch: 457ms
>>
>> This issue isn't unique to the i.MX7, but exists for the i.MX6UL as
>> well, which also has the Cortex-A7 as CPU. Like with
>> imx6ul_cpu_lowlevel_init(), adapt imx7_cpu_lowlevel_init() to avoid this
>> slow down.
>>
>> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
>> Signed-off-by: Johannes Zink <j.zink@pengutronix.de>
>> ---
>> arch/arm/mach-imx/cpu_init.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/mach-imx/cpu_init.c b/arch/arm/mach-imx/cpu_init.c
>> index ea36215419..ede2076102 100644
>> --- a/arch/arm/mach-imx/cpu_init.c
>> +++ b/arch/arm/mach-imx/cpu_init.c
>> @@ -49,7 +49,7 @@ void imx6ul_cpu_lowlevel_init(void)
>>
>> void imx7_cpu_lowlevel_init(void)
>> {
>> - arm_cpu_lowlevel_init();
>> + cortex_a7_lowlevel_init();
>
> Why do you remove the call to arm_cpu_lowlevel_init() here?
Oversight, I thought cortex_a7_lowlevel_init() calls it
internally. Just sent out v2. Thanks.
>
> Sascha
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2022-10-10 6:36 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-09-30 13:37 [PATCH master] ARM: i.MX7: enable caches when booted over USB Johannes Zink
2022-10-04 7:54 ` Marco Felsch
2022-10-10 6:32 ` Ahmad Fatoum
2022-10-10 5:52 ` Sascha Hauer
2022-10-10 6:35 ` Ahmad Fatoum
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox