* [PATCH v2 0/6] ARM: layerscape: streamline and document boot
@ 2019-09-17 11:55 Ahmad Fatoum
2019-09-17 11:55 ` [PATCH v2 1/6] ARM: Layerscape: add bootm handler for images Ahmad Fatoum
` (6 more replies)
0 siblings, 7 replies; 8+ messages in thread
From: Ahmad Fatoum @ 2019-09-17 11:55 UTC (permalink / raw)
To: barebox; +Cc: Ahmad Fatoum
v1 -> v2:
- Not calling back into bootm code. We now read barebox and invoke
it directly in the bootm handler (Sascha)
- Dropped copy_file_2 implementation, because it's no longer needed
- Fixed a commit message typo (Roland)
Ahmad Fatoum (6):
ARM: Layerscape: add bootm handler for images
ARM: Layerscape: don't generate second-stage 2nd.image
filetype: support fastboot barebox_update with layerscape image
scripts: pblimage: explicitly set architecture to ARM
ARM: layerscape: tqmls1046a: disable all SGMII PHYs
Documentation: boards: document layerscape support
Documentation/boards/layerscape.rst | 61 +++++++++++++++++++
.../boards/layerscape/ls1046ardb.rst | 36 +++++++++++
.../boards/layerscape/tqmls1046a.rst | 49 +++++++++++++++
.../defaultenv-tqmls1046a/nv/dev.eth0.mode | 1 +
.../defaultenv-tqmls1046a/nv/dev.eth1.mode | 1 +
arch/arm/mach-layerscape/Makefile | 1 +
arch/arm/mach-layerscape/pblimage.c | 58 ++++++++++++++++++
common/filetype.c | 2 +
images/Makefile.layerscape | 8 +--
scripts/pblimage.c | 2 +-
10 files changed, 212 insertions(+), 7 deletions(-)
create mode 100644 Documentation/boards/layerscape.rst
create mode 100644 Documentation/boards/layerscape/ls1046ardb.rst
create mode 100644 Documentation/boards/layerscape/tqmls1046a.rst
create mode 100644 arch/arm/boards/tqmls1046a/defaultenv-tqmls1046a/nv/dev.eth0.mode
create mode 100644 arch/arm/boards/tqmls1046a/defaultenv-tqmls1046a/nv/dev.eth1.mode
create mode 100644 arch/arm/mach-layerscape/pblimage.c
--
2.23.0
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^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 1/6] ARM: Layerscape: add bootm handler for images
2019-09-17 11:55 [PATCH v2 0/6] ARM: layerscape: streamline and document boot Ahmad Fatoum
@ 2019-09-17 11:55 ` Ahmad Fatoum
2019-09-17 11:55 ` [PATCH v2 2/6] ARM: Layerscape: don't generate second-stage 2nd.image Ahmad Fatoum
` (5 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Ahmad Fatoum @ 2019-09-17 11:55 UTC (permalink / raw)
To: barebox; +Cc: Ahmad Fatoum
The layerscape images are preceeded by a RCW and PBI, which are interpreted
by the Layerscape Hardware Pre-Bootloader and aren't executable as ARM code.
To maintain the ability to network boot them, add a bootm handler that
skips the fixed-size header.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
arch/arm/mach-layerscape/Makefile | 1 +
arch/arm/mach-layerscape/pblimage.c | 58 +++++++++++++++++++++++++++++
2 files changed, 59 insertions(+)
create mode 100644 arch/arm/mach-layerscape/pblimage.c
diff --git a/arch/arm/mach-layerscape/Makefile b/arch/arm/mach-layerscape/Makefile
index 8a814f944161..854a327c9125 100644
--- a/arch/arm/mach-layerscape/Makefile
+++ b/arch/arm/mach-layerscape/Makefile
@@ -5,3 +5,4 @@ obj-y += icid.o
obj-pbl-y += boot.o
pbl-y += xload-qspi.o xload.o
obj-$(CONFIG_ARCH_LAYERSCAPE_PPA) += ppa.o ppa-entry.o
+obj-$(CONFIG_BOOTM) += pblimage.o
diff --git a/arch/arm/mach-layerscape/pblimage.c b/arch/arm/mach-layerscape/pblimage.c
new file mode 100644
index 000000000000..deaf7143b92b
--- /dev/null
+++ b/arch/arm/mach-layerscape/pblimage.c
@@ -0,0 +1,58 @@
+#define pr_fmt(fmt) "pblimage: " fmt
+
+#include <bootm.h>
+#include <common.h>
+#include <init.h>
+#include <memory.h>
+#include <linux/sizes.h>
+
+#define BAREBOX_STAGE2_OFFSET SZ_128K
+
+static int do_bootm_layerscape_pblimage(struct image_data *data)
+{
+ void (*barebox)(unsigned long x0, unsigned long x1, unsigned long x2,
+ unsigned long x3);
+ resource_size_t start, end;
+ int ret;
+
+ ret = memory_bank_first_find_space(&start, &end);
+ if (ret)
+ return ret;
+
+ ret = bootm_load_os(data, start);
+ if (ret)
+ return ret;
+
+ barebox = (void*)start + BAREBOX_STAGE2_OFFSET;
+
+ if (data->verbose)
+ printf("Loaded barebox image to 0x%08lx\n",
+ (unsigned long)barebox);
+
+ shutdown_barebox();
+
+ barebox(0, 0, 0, 0);
+
+ return -EIO;
+}
+
+static struct image_handler image_handler_layerscape_pbl_image = {
+ .name = "Layerscape image",
+ .bootm = do_bootm_layerscape_pblimage,
+ .filetype = filetype_layerscape_image,
+};
+
+static struct image_handler image_handler_layerscape_qspi_pbl_image = {
+ .name = "Layerscape QSPI image",
+ .bootm = do_bootm_layerscape_pblimage,
+ .filetype = filetype_layerscape_qspi_image,
+};
+
+static int layerscape_register_pbl_image_handler(void)
+{
+ register_image_handler(&image_handler_layerscape_pbl_image);
+ register_image_handler(&image_handler_layerscape_qspi_pbl_image);
+
+ return 0;
+}
+late_initcall(layerscape_register_pbl_image_handler);
--
2.23.0
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^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 2/6] ARM: Layerscape: don't generate second-stage 2nd.image
2019-09-17 11:55 [PATCH v2 0/6] ARM: layerscape: streamline and document boot Ahmad Fatoum
2019-09-17 11:55 ` [PATCH v2 1/6] ARM: Layerscape: add bootm handler for images Ahmad Fatoum
@ 2019-09-17 11:55 ` Ahmad Fatoum
2019-09-17 11:55 ` [PATCH v2 3/6] filetype: support fastboot barebox_update with layerscape image Ahmad Fatoum
` (4 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Ahmad Fatoum @ 2019-09-17 11:55 UTC (permalink / raw)
To: barebox; +Cc: Ahmad Fatoum
For layerscape images, barebox currently generates a second stage
barebox that lacks the RCW and PBI and as such can be bootm'd as
any other barebox ARM image. A previous commit implemented bootm
handlers for the RCW and PBI prefixed images and thus the 2nd.image
no longer serves a real purpose. Drop it.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
images/Makefile.layerscape | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/images/Makefile.layerscape b/images/Makefile.layerscape
index d20cc6a37e03..806c09d8fbce 100644
--- a/images/Makefile.layerscape
+++ b/images/Makefile.layerscape
@@ -21,8 +21,6 @@ quiet_cmd_lspbl_spi_image = LSPBL-SPI-IMG $@
-m $($(patsubst $(obj)/%.pblb,PBL_CODE_SIZE_%,$<)) -p $(lspbl-pbi-tmp) -i $<
pbl-$(CONFIG_MACH_LS1046ARDB) += start_ls1046ardb.pbl
-$(obj)/barebox-ls1046ardb-2nd.image: $(obj)/start_ls1046ardb.pblb
- $(call if_changed,shipped)
$(obj)/barebox-ls1046ardb-sd.image: $(obj)/start_ls1046ardb.pblb \
$(board)/ls1046ardb/ls1046ardb_rcw_sd.cfg \
@@ -40,11 +38,9 @@ $(obj)/barebox-ls1046ardb-qspi.image: $(obj)/start_ls1046ardb.pblb \
$(call if_changed,lspbl_spi_image)
image-$(CONFIG_MACH_LS1046ARDB) += barebox-ls1046ardb-sd.image barebox-ls1046ardb-qspi.image \
- barebox-ls1046ardb-emmc.image barebox-ls1046ardb-2nd.image
+ barebox-ls1046ardb-emmc.image
pbl-$(CONFIG_MACH_TQMLS1046A) += start_tqmls1046a.pbl
-$(obj)/barebox-tqmls1046a-2nd.image: $(obj)/start_tqmls1046a.pblb
- $(call if_changed,shipped)
$(obj)/barebox-tqmls1046a-sd.image: $(obj)/start_tqmls1046a.pblb \
$(board)/tqmls1046a/tqmls1046a_rcw_sd_3333_5559.cfg \
@@ -57,4 +53,4 @@ $(obj)/barebox-tqmls1046a-qspi.image: $(obj)/start_tqmls1046a.pblb \
$(call if_changed,lspbl_spi_image)
image-$(CONFIG_MACH_TQMLS1046A) += barebox-tqmls1046a-sd.image \
- barebox-tqmls1046a-qspi.image barebox-tqmls1046a-2nd.image
+ barebox-tqmls1046a-qspi.image
--
2.23.0
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^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 3/6] filetype: support fastboot barebox_update with layerscape image
2019-09-17 11:55 [PATCH v2 0/6] ARM: layerscape: streamline and document boot Ahmad Fatoum
2019-09-17 11:55 ` [PATCH v2 1/6] ARM: Layerscape: add bootm handler for images Ahmad Fatoum
2019-09-17 11:55 ` [PATCH v2 2/6] ARM: Layerscape: don't generate second-stage 2nd.image Ahmad Fatoum
@ 2019-09-17 11:55 ` Ahmad Fatoum
2019-09-17 11:55 ` [PATCH v2 4/6] scripts: pblimage: explicitly set architecture to ARM Ahmad Fatoum
` (3 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Ahmad Fatoum @ 2019-09-17 11:55 UTC (permalink / raw)
To: barebox; +Cc: Ahmad Fatoum
We do not yet support USB on the Layerscape platforms, but when we do,
it's imaginable that we would want to export barebox_update targets over
Fastboot. Prepare for this by adding the layerscape images to those that
filetype_is_barebox_image returns true for.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
common/filetype.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/common/filetype.c b/common/filetype.c
index 825bf25ad107..4966c5e068bd 100644
--- a/common/filetype.c
+++ b/common/filetype.c
@@ -460,6 +460,8 @@ bool filetype_is_barebox_image(enum filetype ft)
case filetype_mips_barebox:
case filetype_ch_image:
case filetype_ch_image_be:
+ case filetype_layerscape_image:
+ case filetype_layerscape_qspi_image:
return true;
default:
return false;
--
2.23.0
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http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 4/6] scripts: pblimage: explicitly set architecture to ARM
2019-09-17 11:55 [PATCH v2 0/6] ARM: layerscape: streamline and document boot Ahmad Fatoum
` (2 preceding siblings ...)
2019-09-17 11:55 ` [PATCH v2 3/6] filetype: support fastboot barebox_update with layerscape image Ahmad Fatoum
@ 2019-09-17 11:55 ` Ahmad Fatoum
2019-09-17 11:55 ` [PATCH v2 5/6] ARM: layerscape: tqmls1046a: disable all SGMII PHYs Ahmad Fatoum
` (2 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Ahmad Fatoum @ 2019-09-17 11:55 UTC (permalink / raw)
To: barebox; +Cc: Ahmad Fatoum
architecture is statically initialized to zero, which happens to be
ARCH_ARM as it's the first enum constant.
Make this a bit clearer by explicitly assigning ARCH_ARM to architecture.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
scripts/pblimage.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/pblimage.c b/scripts/pblimage.c
index 73c0169ac1c1..235af8aa11b1 100644
--- a/scripts/pblimage.c
+++ b/scripts/pblimage.c
@@ -61,7 +61,7 @@ enum arch {
ARCH_POWERPC,
};
-enum arch architecture;
+enum arch architecture = ARCH_ARM;
static char *rcwfile;
static char *pbifile;
static char *outfile;
--
2.23.0
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http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 5/6] ARM: layerscape: tqmls1046a: disable all SGMII PHYs
2019-09-17 11:55 [PATCH v2 0/6] ARM: layerscape: streamline and document boot Ahmad Fatoum
` (3 preceding siblings ...)
2019-09-17 11:55 ` [PATCH v2 4/6] scripts: pblimage: explicitly set architecture to ARM Ahmad Fatoum
@ 2019-09-17 11:55 ` Ahmad Fatoum
2019-09-17 11:55 ` [PATCH v2 6/6] Documentation: boards: document layerscape support Ahmad Fatoum
2019-09-18 12:40 ` [PATCH v2 0/6] ARM: layerscape: streamline and document boot Sascha Hauer
6 siblings, 0 replies; 8+ messages in thread
From: Ahmad Fatoum @ 2019-09-17 11:55 UTC (permalink / raw)
To: barebox; +Cc: Ahmad Fatoum
We already disable PHYs 4-7, which are currently unusable as they hang
off SGMII, which barebox' FMan driver does not yet support.
Follow suit for the SGMII eth0 and eth1 as well, so they don't
unnecessarily clutter the barebox output with
Unable to find a PHY (unknown ID?)
messages.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
.../arm/boards/tqmls1046a/defaultenv-tqmls1046a/nv/dev.eth0.mode | 1 +
.../arm/boards/tqmls1046a/defaultenv-tqmls1046a/nv/dev.eth1.mode | 1 +
2 files changed, 2 insertions(+)
create mode 100644 arch/arm/boards/tqmls1046a/defaultenv-tqmls1046a/nv/dev.eth0.mode
create mode 100644 arch/arm/boards/tqmls1046a/defaultenv-tqmls1046a/nv/dev.eth1.mode
diff --git a/arch/arm/boards/tqmls1046a/defaultenv-tqmls1046a/nv/dev.eth0.mode b/arch/arm/boards/tqmls1046a/defaultenv-tqmls1046a/nv/dev.eth0.mode
new file mode 100644
index 000000000000..7a68b11da8b1
--- /dev/null
+++ b/arch/arm/boards/tqmls1046a/defaultenv-tqmls1046a/nv/dev.eth0.mode
@@ -0,0 +1 @@
+disabled
diff --git a/arch/arm/boards/tqmls1046a/defaultenv-tqmls1046a/nv/dev.eth1.mode b/arch/arm/boards/tqmls1046a/defaultenv-tqmls1046a/nv/dev.eth1.mode
new file mode 100644
index 000000000000..7a68b11da8b1
--- /dev/null
+++ b/arch/arm/boards/tqmls1046a/defaultenv-tqmls1046a/nv/dev.eth1.mode
@@ -0,0 +1 @@
+disabled
--
2.23.0
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^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 6/6] Documentation: boards: document layerscape support
2019-09-17 11:55 [PATCH v2 0/6] ARM: layerscape: streamline and document boot Ahmad Fatoum
` (4 preceding siblings ...)
2019-09-17 11:55 ` [PATCH v2 5/6] ARM: layerscape: tqmls1046a: disable all SGMII PHYs Ahmad Fatoum
@ 2019-09-17 11:55 ` Ahmad Fatoum
2019-09-18 12:40 ` [PATCH v2 0/6] ARM: layerscape: streamline and document boot Sascha Hauer
6 siblings, 0 replies; 8+ messages in thread
From: Ahmad Fatoum @ 2019-09-17 11:55 UTC (permalink / raw)
To: barebox; +Cc: Ahmad Fatoum
Some peripherals are still missing, but the main functionality to boot
an OS is already in place. Document how to use it.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
Documentation/boards/layerscape.rst | 61 +++++++++++++++++++
.../boards/layerscape/ls1046ardb.rst | 36 +++++++++++
.../boards/layerscape/tqmls1046a.rst | 49 +++++++++++++++
3 files changed, 146 insertions(+)
create mode 100644 Documentation/boards/layerscape.rst
create mode 100644 Documentation/boards/layerscape/ls1046ardb.rst
create mode 100644 Documentation/boards/layerscape/tqmls1046a.rst
diff --git a/Documentation/boards/layerscape.rst b/Documentation/boards/layerscape.rst
new file mode 100644
index 000000000000..ae089539e564
--- /dev/null
+++ b/Documentation/boards/layerscape.rst
@@ -0,0 +1,61 @@
+NXP Layerscape
+==============
+
+barebox has support for some of the ARM64 based Layerscape SoCs from NXP.
+
+Booting barebox
+---------------
+
+The Layerscape SoCs contain logic dubbed the Pre-Bootloader (PBL). This unit
+reads the boot medium and conducts basic IO multiplexing according to the RCW
+(Reset Configuration Word). The RCW then refers the PBL to the location of the
+Pre-Bootloader Instructions (PBI). These do basic device configuration and
+afterwards poke the barebox PBL into On-Chip SRAM.
+The barebox PBL then loads the complete barebox image and runs the PBL again,
+this time from SDRAM after it has been set up.
+
+For each board, a barebox image per supported boot medium is generated.
+They may differ in the RCW, PBI and endianess depending on the boot medium.
+
+Flashing barebox
+----------------
+
+The barebox binary is expected to be located 4K bytes into the SD-Card::
+
+ dd if=images/barebox-${boardname}-sd.image of=/dev/sdX bs=512 seek=8
+
+From there on, ``barebox_update`` can be used to flash
+barebox to the QSPI NOR-Flash if required::
+
+ barebox_update -t qspi /mnt/tftp/barebox-${global.hostname}-qspi.imaag
+
+Flashing to the eMMC is possible likewise::
+
+ barebox_update -t sd /mnt/tftp/barebox-${global.hostname}-sd.imaag
+
+.. note:: Some SoCs like the LS1046A feature only a single eSDHC.
+ In such a case, using eMMC and SD-Card at the same time is not possible.
+ Boot from QSPI to flash the eMMC.
+
+Firmware Blobs
+--------------
+
+Network: `fsl_fman_ucode_ls1046_r1.0_106_4_18.bin <https://github.com/NXP/qoriq-fm-ucode/raw/integration/fsl_fman_ucode_ls1046_r1.0_106_4_18.bin>`_.
+
+PSCI Firmware: `ppa-ls1046a.bin <https://github.com/NXP/qoriq-ppa-binary/raw/integration/soc-ls1046/ppa.itb>`_.
+
+Layerscape boards
+-----------------
+
+With multi-image and device trees, it's expected to have ``layerscape_defconfig``
+as sole defconfig for all Layerscape boards::
+
+ make ARCH=arm layerscape_defconfig
+
+Generated images will be placed under ``images/``.
+
+.. toctree::
+ :glob:
+ :maxdepth: 1
+
+ layerscape/*
diff --git a/Documentation/boards/layerscape/ls1046ardb.rst b/Documentation/boards/layerscape/ls1046ardb.rst
new file mode 100644
index 000000000000..323f2ca990c9
--- /dev/null
+++ b/Documentation/boards/layerscape/ls1046ardb.rst
@@ -0,0 +1,36 @@
+NXP LS1046A Reference Design Board
+==================================
+
+Boot DIP Switches
+-----------------
+
+Boot source selection happens via the the bottom most DIP switch (near the micro-usb port)::
+
+ OFF -> ON
+ +---------+
+ 1 | O---- |
+ 2 | O---- |
+ 3 | ----O |
+ 4 | O---- |
+ 5 | O---- |
+ 6 | O---- |
+ 7 | ----O | <---- Boot from QSPI (default)
+ 8 | O---- |
+ +---------+
+
+ OFF -> ON
+ +---------+
+ 1 | O---- |
+ 2 | O---- |
+ 3 | ----O |
+ 4 | O---- |
+ 5 | O---- |
+ 6 | O---- |
+ 7 | O---- | <---- Boot from SDHC
+ 8 | O---- |
+ +---------+
+
+Known Issues
+------------
+
+System reset may not complete if the CMSIS-DAP micro-usb is connected.
diff --git a/Documentation/boards/layerscape/tqmls1046a.rst b/Documentation/boards/layerscape/tqmls1046a.rst
new file mode 100644
index 000000000000..55a5dff4a396
--- /dev/null
+++ b/Documentation/boards/layerscape/tqmls1046a.rst
@@ -0,0 +1,49 @@
+TQ-Group TQMLS1046A Module
+==========================
+
+Ethernet Ports
+--------------
+
+There two RGMII ports are the two closest to the RS-232 socket.
+They are ``eth2`` for the lower port and ``eth3`` for the upper port.
+
+MBLS10xxA (Base Board) Boot DIP Switches
+----------------------------------------
+
+Boot source selection happens via the ``S5`` DIP-Switch::
+
+ +---------+
+ | |
+ | | | O x |
+ | | | | x | <---- SDHC (X31)
+ | O O | x |
+ | |
+ | 1 2 3 4 |
+ +---------+
+
+ +---------+
+ | |
+ | O | O x |
+ | | | | x | <---- eMMC
+ | | O | x |
+ | |
+ | 1 2 3 4 |
+ +---------+
+
+ +---------+
+ | |
+ | | O O x |
+ | | | | x | <---- QSPI (eSDHC controls SDHC)
+ | O | | x |
+ | |
+ | 1 2 3 4 |
+ +---------+
+
+ +---------+
+ | |
+ | O O O x |
+ | | | | x | <---- QSPI (eSDHC controls eMMC)
+ | | | | x |
+ | |
+ | 1 2 3 4 |
+ +---------+
--
2.23.0
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^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 0/6] ARM: layerscape: streamline and document boot
2019-09-17 11:55 [PATCH v2 0/6] ARM: layerscape: streamline and document boot Ahmad Fatoum
` (5 preceding siblings ...)
2019-09-17 11:55 ` [PATCH v2 6/6] Documentation: boards: document layerscape support Ahmad Fatoum
@ 2019-09-18 12:40 ` Sascha Hauer
6 siblings, 0 replies; 8+ messages in thread
From: Sascha Hauer @ 2019-09-18 12:40 UTC (permalink / raw)
To: Ahmad Fatoum; +Cc: barebox
On Tue, Sep 17, 2019 at 01:55:12PM +0200, Ahmad Fatoum wrote:
> v1 -> v2:
> - Not calling back into bootm code. We now read barebox and invoke
> it directly in the bootm handler (Sascha)
> - Dropped copy_file_2 implementation, because it's no longer needed
> - Fixed a commit message typo (Roland)
>
> Ahmad Fatoum (6):
> ARM: Layerscape: add bootm handler for images
> ARM: Layerscape: don't generate second-stage 2nd.image
> filetype: support fastboot barebox_update with layerscape image
> scripts: pblimage: explicitly set architecture to ARM
> ARM: layerscape: tqmls1046a: disable all SGMII PHYs
> Documentation: boards: document layerscape support
Applied, thanks
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
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^ permalink raw reply [flat|nested] 8+ messages in thread
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2019-09-17 11:55 [PATCH v2 0/6] ARM: layerscape: streamline and document boot Ahmad Fatoum
2019-09-17 11:55 ` [PATCH v2 1/6] ARM: Layerscape: add bootm handler for images Ahmad Fatoum
2019-09-17 11:55 ` [PATCH v2 2/6] ARM: Layerscape: don't generate second-stage 2nd.image Ahmad Fatoum
2019-09-17 11:55 ` [PATCH v2 3/6] filetype: support fastboot barebox_update with layerscape image Ahmad Fatoum
2019-09-17 11:55 ` [PATCH v2 4/6] scripts: pblimage: explicitly set architecture to ARM Ahmad Fatoum
2019-09-17 11:55 ` [PATCH v2 5/6] ARM: layerscape: tqmls1046a: disable all SGMII PHYs Ahmad Fatoum
2019-09-17 11:55 ` [PATCH v2 6/6] Documentation: boards: document layerscape support Ahmad Fatoum
2019-09-18 12:40 ` [PATCH v2 0/6] ARM: layerscape: streamline and document boot Sascha Hauer
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