[PATCH] ARM: imx8mq: reclock ARM PLL to 800MHz

[PATCH] ARM: imx8mq: reclock ARM PLL to 800MHz

[Lucas Stach]

The BootROM sets up the ARM PLL to run at 1.6GHz and then uses the
divider after the PLL the achieve a CPU clock rate of 800MHz. New Linux
kernels (>= 5.8) switch to a clock path that bypasses the divider, as
the divider should not be used for CPU clock frequencies >1GHz. If the
BootROM setup is left unchanged this causes the CPU clock to jump to
the full 1.6GHz until CPUfreq takes over and reprograms the PLL. This
rate is outside of the chip specification and leads to crashes.

Fix this by reclocking the ARM PLL to 800MHz.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 arch/arm/dts/imx8mq.dtsi | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/imx8mq.dtsi b/arch/arm/dts/imx8mq.dtsi
index ec8347f38fa8..e56cdfe1308e 100644
--- a/arch/arm/dts/imx8mq.dtsi
+++ b/arch/arm/dts/imx8mq.dtsi
@@ -17,7 +17,9 @@
 			  <&clk IMX8MQ_CLK_USDHC2>,
 			  <&clk IMX8MQ_CLK_ENET_AXI>,
 			  <&clk IMX8MQ_CLK_ENET_TIMER>,
-			  <&clk IMX8MQ_CLK_ENET_REF>;
+			  <&clk IMX8MQ_CLK_ENET_REF>,
+			  <&clk IMX8MQ_ARM_PLL>,
+			  <&clk IMX8MQ_CLK_A53_DIV>;
 
 	assigned-clock-parents =  <&clk IMX8MQ_SYS1_PLL_400M>,
 				  <&clk IMX8MQ_SYS1_PLL_400M>,
@@ -29,5 +31,7 @@
 			       <200000000>,
 			       <266000000>,
 			       <25000000>,
-			       <125000000>;
+			       <125000000>,
+			       <800000000>,
+			       <800000000>;
 };
-- 
2.29.2


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Re: [PATCH] ARM: imx8mq: reclock ARM PLL to 800MHz

[Sascha Hauer]

On Tue, Dec 29, 2020 at 09:23:28PM +0100, Lucas Stach wrote:
> The BootROM sets up the ARM PLL to run at 1.6GHz and then uses the
> divider after the PLL the achieve a CPU clock rate of 800MHz. New Linux
> kernels (>= 5.8) switch to a clock path that bypasses the divider, as
> the divider should not be used for CPU clock frequencies >1GHz. If the
> BootROM setup is left unchanged this causes the CPU clock to jump to
> the full 1.6GHz until CPUfreq takes over and reprograms the PLL. This
> rate is outside of the chip specification and leads to crashes.
> 
> Fix this by reclocking the ARM PLL to 800MHz.
> 
> Signed-off-by: Lucas Stach <dev@lynxeye.de>
> ---
>  arch/arm/dts/imx8mq.dtsi | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)

Applied, thanks

Sascha

> 
> diff --git a/arch/arm/dts/imx8mq.dtsi b/arch/arm/dts/imx8mq.dtsi
> index ec8347f38fa8..e56cdfe1308e 100644
> --- a/arch/arm/dts/imx8mq.dtsi
> +++ b/arch/arm/dts/imx8mq.dtsi
> @@ -17,7 +17,9 @@
>  			  <&clk IMX8MQ_CLK_USDHC2>,
>  			  <&clk IMX8MQ_CLK_ENET_AXI>,
>  			  <&clk IMX8MQ_CLK_ENET_TIMER>,
> -			  <&clk IMX8MQ_CLK_ENET_REF>;
> +			  <&clk IMX8MQ_CLK_ENET_REF>,
> +			  <&clk IMX8MQ_ARM_PLL>,
> +			  <&clk IMX8MQ_CLK_A53_DIV>;
>  
>  	assigned-clock-parents =  <&clk IMX8MQ_SYS1_PLL_400M>,
>  				  <&clk IMX8MQ_SYS1_PLL_400M>,
> @@ -29,5 +31,7 @@
>  			       <200000000>,
>  			       <266000000>,
>  			       <25000000>,
> -			       <125000000>;
> +			       <125000000>,
> +			       <800000000>,
> +			       <800000000>;
>  };
> -- 
> 2.29.2
> 
> 
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