* [PATCH] ARM: dts: imx6qdl: pfla02: Use NAND pinmux entries from upstream
@ 2021-01-25 10:00 Alexander Shiyan
2021-01-25 10:12 ` Sascha Hauer
0 siblings, 1 reply; 2+ messages in thread
From: Alexander Shiyan @ 2021-01-25 10:00 UTC (permalink / raw)
To: barebox
The gpminand pinmux entries are in the upstream dtsi now, so use them.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
---
arch/arm/dts/imx6qdl-phytec-pfla02.dtsi | 24 ------------------------
1 file changed, 24 deletions(-)
diff --git a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
index f499ca568..e1aa3183b 100644
--- a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
+++ b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
@@ -127,30 +127,6 @@
MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x80000000
>;
};
-
- pinctrl_gpmi_nand: gpminandgrp {
- fsl,pins = <
- MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
- MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
- MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
- MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
- MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
- MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
- MX6QDL_PAD_NANDF_CS2__NAND_CE2_B 0xb0b1
- MX6QDL_PAD_NANDF_CS3__NAND_CE3_B 0xb0b1
- MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
- MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
- MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
- MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
- MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
- MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
- MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
- MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
- MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
- MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
- MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
- >;
- };
};
};
--
2.26.2
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^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PATCH] ARM: dts: imx6qdl: pfla02: Use NAND pinmux entries from upstream
2021-01-25 10:00 [PATCH] ARM: dts: imx6qdl: pfla02: Use NAND pinmux entries from upstream Alexander Shiyan
@ 2021-01-25 10:12 ` Sascha Hauer
0 siblings, 0 replies; 2+ messages in thread
From: Sascha Hauer @ 2021-01-25 10:12 UTC (permalink / raw)
To: Alexander Shiyan; +Cc: barebox
On Mon, Jan 25, 2021 at 01:00:47PM +0300, Alexander Shiyan wrote:
> The gpminand pinmux entries are in the upstream dtsi now, so use them.
>
> Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
> ---
> arch/arm/dts/imx6qdl-phytec-pfla02.dtsi | 24 ------------------------
> 1 file changed, 24 deletions(-)
Applied, thanks
Sascha
>
> diff --git a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
> index f499ca568..e1aa3183b 100644
> --- a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
> +++ b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
> @@ -127,30 +127,6 @@
> MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x80000000
> >;
> };
> -
> - pinctrl_gpmi_nand: gpminandgrp {
> - fsl,pins = <
> - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
> - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
> - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
> - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
> - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
> - MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
> - MX6QDL_PAD_NANDF_CS2__NAND_CE2_B 0xb0b1
> - MX6QDL_PAD_NANDF_CS3__NAND_CE3_B 0xb0b1
> - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
> - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
> - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
> - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
> - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
> - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
> - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
> - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
> - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
> - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
> - MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
> - >;
> - };
> };
> };
>
> --
> 2.26.2
>
>
> _______________________________________________
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2021-01-25 10:00 [PATCH] ARM: dts: imx6qdl: pfla02: Use NAND pinmux entries from upstream Alexander Shiyan
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