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From: Sascha Hauer <s.hauer@pengutronix.de>
To: Barebox List <barebox@lists.infradead.org>
Subject: [PATCH 21/24] clk: implement set/get phase
Date: Wed,  2 Jun 2021 11:55:04 +0200	[thread overview]
Message-ID: <20210602095507.24609-22-s.hauer@pengutronix.de> (raw)
In-Reply-To: <20210602095507.24609-1-s.hauer@pengutronix.de>

Linux has clk_set_phase() and clk_get_phase() along with the
corresponding callbacks in struct clk_ops. Implement the same for
barebox as well.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/clk/clk.c   | 55 +++++++++++++++++++++++++++++++++++++++++++++
 include/linux/clk.h |  5 +++++
 2 files changed, 60 insertions(+)

diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index fe2424dc8a..8b90f30486 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -320,6 +320,61 @@ struct clk_hw *clk_hw_get_parent(struct clk_hw *hw)
 	return clk_to_clk_hw(clk);
 }
 
+/**
+ * clk_set_phase - adjust the phase shift of a clock signal
+ * @clk: clock signal source
+ * @degrees: number of degrees the signal is shifted
+ *
+ * Shifts the phase of a clock signal by the specified
+ * degrees. Returns 0 on success, -EERROR otherwise.
+ *
+ * This function makes no distinction about the input or reference
+ * signal that we adjust the clock signal phase against. For example
+ * phase locked-loop clock signal generators we may shift phase with
+ * respect to feedback clock signal input, but for other cases the
+ * clock phase may be shifted with respect to some other, unspecified
+ * signal.
+ *
+ * Additionally the concept of phase shift does not propagate through
+ * the clock tree hierarchy, which sets it apart from clock rates and
+ * clock accuracy. A parent clock phase attribute does not have an
+ * impact on the phase attribute of a child clock.
+ */
+int clk_set_phase(struct clk *clk, int degrees)
+{
+	if (!clk)
+		return 0;
+
+	/* sanity check degrees */
+	degrees %= 360;
+	if (degrees < 0)
+		degrees += 360;
+
+	if (!clk->ops->set_phase)
+		return -EINVAL;
+
+	return clk->ops->set_phase(clk_to_clk_hw(clk), degrees);
+}
+
+/**
+ * clk_get_phase - return the phase shift of a clock signal
+ * @clk: clock signal source
+ *
+ * Returns the phase shift of a clock node in degrees, otherwise returns
+ * -EERROR.
+ */
+int clk_get_phase(struct clk *clk)
+{
+	int ret;
+
+	if (!clk->ops->get_phase)
+		return 0;
+
+	ret = clk->ops->get_phase(clk_to_clk_hw(clk));
+
+	return ret;
+}
+
 int bclk_register(struct clk *clk)
 {
 	struct clk_hw *hw = clk_to_clk_hw(clk);
diff --git a/include/linux/clk.h b/include/linux/clk.h
index 72971c8e27..6b4c368231 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -237,6 +237,9 @@ int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *hwp);
 struct clk *clk_get_parent(struct clk *clk);
 struct clk_hw *clk_hw_get_parent(struct clk_hw *hw);
 
+int clk_set_phase(struct clk *clk, int degrees);
+int clk_get_phase(struct clk *clk);
+
 /**
  * clk_get_sys - get a clock based upon the device name
  * @dev_id: device name
@@ -356,6 +359,8 @@ struct clk_ops {
 	int		(*get_parent)(struct clk_hw *hw);
 	int		(*set_rate)(struct clk_hw *hw, unsigned long,
 				    unsigned long);
+	int		(*set_phase)(struct clk_hw *hw, int degrees);
+	int		(*get_phase)(struct clk_hw *hw);
 };
 
 /**
-- 
2.29.2


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  parent reply	other threads:[~2021-06-02 10:02 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-02  9:54 [PATCH v2 00/24] clk updates Sascha Hauer
2021-06-02  9:54 ` [PATCH 01/24] clk: clk-mux: Fix handling of CLK_MUX_HIWORD_MASK Sascha Hauer
2021-06-02 15:18   ` Ahmad Fatoum
2021-06-02  9:54 ` [PATCH 02/24] clk: introduce clk init op Sascha Hauer
2021-06-02  9:54 ` [PATCH 03/24] clk: rename clk_register() to bclk_register() Sascha Hauer
2021-06-02  9:54 ` [PATCH 04/24] clk: introduce struct clk_hw Sascha Hauer
2021-06-11  7:55   ` Ahmad Fatoum
2021-06-11  8:41     ` Sascha Hauer
2021-06-11  9:19       ` Ahmad Fatoum
2021-06-11 11:46         ` Sascha Hauer
2021-06-11 12:14           ` Ahmad Fatoum
2021-06-02  9:54 ` [PATCH 05/24] clk: introduce clk_register() Sascha Hauer
2021-06-02  9:54 ` [PATCH 06/24] clk: divider: Make clk_divider_ops const Sascha Hauer
2021-06-02  9:54 ` [PATCH 07/24] clk: divider: Add ro ops Sascha Hauer
2021-06-02  9:54 ` [PATCH 08/24] clk: divider: Make clk_mux_ops const Sascha Hauer
2021-06-02  9:54 ` [PATCH 09/24] clk: mux: Add ro ops Sascha Hauer
2021-06-02  9:54 ` [PATCH 10/24] clk: move fixed_factor to include/linux/clk.h Sascha Hauer
2021-06-02  9:54 ` [PATCH 11/24] Add rational_best_approximation() Sascha Hauer
2021-06-02 18:25   ` Trent Piepho
2021-06-07 11:22     ` Sascha Hauer
2021-06-02  9:54 ` [PATCH 12/24] clk: Update fractional divider from Linux Sascha Hauer
2021-06-02  9:54 ` [PATCH 13/24] clk: Add lock to different clock types Sascha Hauer
2021-06-02  9:54 ` [PATCH 14/24] clk: Add Linux functions to register a divider Sascha Hauer
2021-06-02  9:54 ` [PATCH 15/24] clk: Add Linux functions to register a fixed factor clock Sascha Hauer
2021-06-02  9:54 ` [PATCH 16/24] clk: Add Linux functions to register a gate Sascha Hauer
2021-06-02  9:55 ` [PATCH 17/24] clk: Add Linux functions to register a mux Sascha Hauer
2021-06-02  9:55 ` [PATCH 18/24] clk: Add CLK_GET_RATE_NOCACHE Sascha Hauer
2021-06-02  9:55 ` [PATCH 19/24] clk: Rename CLK_GATE_INVERTED to CLK_GATE_SET_TO_DISABLE Sascha Hauer
2021-06-02  9:55 ` [PATCH 20/24] clk: implement CLK_SET_RATE_UNGATE Sascha Hauer
2021-06-02  9:55 ` Sascha Hauer [this message]
2021-06-02  9:55 ` [PATCH 22/24] regmap: Add regmap_read_poll_timeout Sascha Hauer
2021-06-02  9:55 ` [PATCH 23/24] clk: rockchip: Update to current Linux Sascha Hauer
2021-06-02  9:55 ` [PATCH 24/24] clk: Rockchip: Add rk3568 clk support Sascha Hauer
2021-06-09  9:18   ` Ahmad Fatoum

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