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From: Ahmad Fatoum <a.fatoum@pengutronix.de>
To: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Barebox List <barebox@lists.infradead.org>
Subject: Re: [PATCH 04/24] clk: introduce struct clk_hw
Date: Fri, 11 Jun 2021 11:19:12 +0200
Message-ID: <791dae7e-82b4-ae55-799d-8dd164b24f0c@pengutronix.de> (raw)
In-Reply-To: <20210611084107.GC22904@pengutronix.de>

Hello Sascha,

On 11.06.21 10:41, Sascha Hauer wrote:
> On Fri, Jun 11, 2021 at 09:55:36AM +0200, Ahmad Fatoum wrote:
>> Hello Sascha,
>>
>> On 02.06.21 11:54, Sascha Hauer wrote:
>>
>>> In Linux the ops in struct clk_ops take a struct clk_hw * argument
>>
>>> instead of a struct clk * argument as in barebox. With this taking
>>
>>> new clk drivers from Linux requires a lot of mechanical conversions.
>>
>>> Instead of doing this over and over again swallow the pill once and
>>
>>> convert the existing barebox code over to clk_hw.
>>
>>>
>>
>>> The implementation is a little different from Linux. In Linux struct clk
>>
>>> is only known to the core clock code. In barebox struct clk is
>>
>>> publically known and it is embedded into struct clk_hw. This allows
>>
>>> us to still use struct clk members in the clock drivers which we
>>
>>> currently still need, because otherwise this patch would be even
>>
>>> bigger.
>>
>>>
>>
>>> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
>>
>> drivers/clk/sifive, which was added recently doesn't have these changes
>> and thus the build fails. To reproduce, without installed RISC-V toolchain, try:
>>
>>    ./test/emulate.pl --runtime=podman sifive_defconfig
> 
> Can't exec "tuxmake": No such file or directory at ./test/emulate.pl line 377.
> 
> Where do I get this from?

pip3 install tuxmake

>> Doing the conversions aren't completely trivial to me, as there are no
>> clkdev clk_hw helpers ported and I still need to figure out how to use them.
>> Given that your caches are still hot, could you take a look?
> 
> Here we go. I added the following to next.

Just tested in QEMU and works fine!
You should still try emulate.pl above though. If it runs through, it will
start a QEMU VM, where dhcp working will tell you that the clock changes
seem ok.

Cheers,
Ahmad

> 
> Sascha
> 
> ---------------------------8<--------------------------------
> 
> From 61da1fea5d3c516d7f2609daebfc19e035a4c485 Mon Sep 17 00:00:00 2001
> From: Sascha Hauer <s.hauer@pengutronix.de>
> Date: Fri, 11 Jun 2021 10:38:27 +0200
> Subject: [PATCH] clk: sifive: Fix missing conversion to struct clk_hw
> 
> Sifive was not converted to the recent struct clk_hw changes. Add these.
> 
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
>  drivers/clk/sifive/sifive-prci.c | 42 +++++++++++++++++---------------
>  drivers/clk/sifive/sifive-prci.h | 18 +++++++-------
>  2 files changed, 32 insertions(+), 28 deletions(-)
> 
> diff --git a/drivers/clk/sifive/sifive-prci.c b/drivers/clk/sifive/sifive-prci.c
> index b452bbf8cc..1701a2c5a0 100644
> --- a/drivers/clk/sifive/sifive-prci.c
> +++ b/drivers/clk/sifive/sifive-prci.c
> @@ -185,7 +185,7 @@ static void __prci_wrpll_write_cfg1(struct __prci_data *pd,
>   * these functions.
>   */
>  
> -unsigned long sifive_prci_wrpll_recalc_rate(struct clk *hw,
> +unsigned long sifive_prci_wrpll_recalc_rate(struct clk_hw *hw,
>  					    unsigned long parent_rate)
>  {
>  	struct __prci_clock *pc = clk_hw_to_prci_clock(hw);
> @@ -194,7 +194,7 @@ unsigned long sifive_prci_wrpll_recalc_rate(struct clk *hw,
>  	return wrpll_calc_output_rate(&pwd->c, parent_rate);
>  }
>  
> -long sifive_prci_wrpll_round_rate(struct clk *hw,
> +long sifive_prci_wrpll_round_rate(struct clk_hw *hw,
>  				  unsigned long rate,
>  				  unsigned long *parent_rate)
>  {
> @@ -209,7 +209,7 @@ long sifive_prci_wrpll_round_rate(struct clk *hw,
>  	return wrpll_calc_output_rate(&c, *parent_rate);
>  }
>  
> -int sifive_prci_wrpll_set_rate(struct clk *hw,
> +int sifive_prci_wrpll_set_rate(struct clk_hw *hw,
>  			       unsigned long rate, unsigned long parent_rate)
>  {
>  	struct __prci_clock *pc = clk_hw_to_prci_clock(hw);
> @@ -231,7 +231,7 @@ int sifive_prci_wrpll_set_rate(struct clk *hw,
>  	return 0;
>  }
>  
> -int sifive_clk_is_enabled(struct clk *hw)
> +int sifive_clk_is_enabled(struct clk_hw *hw)
>  {
>  	struct __prci_clock *pc = clk_hw_to_prci_clock(hw);
>  	struct __prci_wrpll_data *pwd = pc->pwd;
> @@ -246,7 +246,7 @@ int sifive_clk_is_enabled(struct clk *hw)
>  		return 0;
>  }
>  
> -int sifive_prci_clock_enable(struct clk *hw)
> +int sifive_prci_clock_enable(struct clk_hw *hw)
>  {
>  	struct __prci_clock *pc = clk_hw_to_prci_clock(hw);
>  	struct __prci_wrpll_data *pwd = pc->pwd;
> @@ -263,7 +263,7 @@ int sifive_prci_clock_enable(struct clk *hw)
>  	return 0;
>  }
>  
> -void sifive_prci_clock_disable(struct clk *hw)
> +void sifive_prci_clock_disable(struct clk_hw *hw)
>  {
>  	struct __prci_clock *pc = clk_hw_to_prci_clock(hw);
>  	struct __prci_wrpll_data *pwd = pc->pwd;
> @@ -281,7 +281,7 @@ void sifive_prci_clock_disable(struct clk *hw)
>  
>  /* TLCLKSEL clock integration */
>  
> -unsigned long sifive_prci_tlclksel_recalc_rate(struct clk *hw,
> +unsigned long sifive_prci_tlclksel_recalc_rate(struct clk_hw *hw,
>  					       unsigned long parent_rate)
>  {
>  	struct __prci_clock *pc = clk_hw_to_prci_clock(hw);
> @@ -298,7 +298,7 @@ unsigned long sifive_prci_tlclksel_recalc_rate(struct clk *hw,
>  
>  /* HFPCLK clock integration */
>  
> -unsigned long sifive_prci_hfpclkplldiv_recalc_rate(struct clk *hw,
> +unsigned long sifive_prci_hfpclkplldiv_recalc_rate(struct clk_hw *hw,
>  						   unsigned long parent_rate)
>  {
>  	struct __prci_clock *pc = clk_hw_to_prci_clock(hw);
> @@ -473,6 +473,7 @@ void sifive_prci_hfpclkpllsel_use_hfpclkpll(struct __prci_data *pd)
>  static int __prci_register_clocks(struct device_d *dev, struct __prci_data *pd,
>  				  const struct prci_clk_desc *desc)
>  {
> +	struct clk_init_data init = { };
>  	struct __prci_clock *pic;
>  	int parent_count, i, r;
>  
> @@ -485,33 +486,36 @@ static int __prci_register_clocks(struct device_d *dev, struct __prci_data *pd,
>  
>  	/* Register PLLs */
>  	for (i = 0; i < desc->num_clks; ++i) {
> +		struct clk *clk;
> +
>  		pic = &(desc->clks[i]);
>  
> -		pic->hw.name = pic->name;
> -		pic->hw.parent_names = &pic->parent_name;
> -		pic->hw.num_parents = 1;
> -		pic->hw.ops = pic->ops;
> +		init.name = pic->name;
> +		init.parent_names = &pic->parent_name;
> +		init.num_parents = 1;
> +		init.ops = pic->ops;
> +		pic->hw.init = &init;
>  
>  		pic->pd = pd;
>  
>  		if (pic->pwd)
>  			__prci_wrpll_read_cfg0(pd, pic->pwd);
>  
> -		r = clk_register(&pic->hw);
> -		if (r) {
> +		clk = clk_register(dev, &pic->hw);
> +		if (IS_ERR(clk)) {
>  			dev_warn(dev, "Failed to register clock %s: %d\n",
> -				 pic->hw.name, r);
> -			return r;
> +				 clk_hw_get_name(&pic->hw), r);
> +			return PTR_ERR(clk);
>  		}
>  
> -		r = clk_register_clkdev(&pic->hw, pic->name, dev_name(dev));
> +		r = clk_register_clkdev(clk, pic->name, dev_name(dev));
>  		if (r) {
>  			dev_warn(dev, "Failed to register clkdev for %s: %d\n",
> -				 pic->hw.name, r);
> +				 clk_hw_get_name(&pic->hw), r);
>  			return r;
>  		}
>  
> -		pd->hw_clks.clks[i] = &pic->hw;
> +		pd->hw_clks.clks[i] = clk;
>  	}
>  
>  	pd->hw_clks.clk_num = i;
> diff --git a/drivers/clk/sifive/sifive-prci.h b/drivers/clk/sifive/sifive-prci.h
> index d851553818..e7a04ae790 100644
> --- a/drivers/clk/sifive/sifive-prci.h
> +++ b/drivers/clk/sifive/sifive-prci.h
> @@ -254,7 +254,7 @@ struct __prci_clock {
>  	const char *name;
>  	const char *parent_name;
>  	const struct clk_ops *ops;
> -	struct clk hw;
> +	struct clk_hw hw;
>  	struct __prci_wrpll_data *pwd;
>  	struct __prci_data *pd;
>  };
> @@ -281,18 +281,18 @@ void sifive_prci_hfpclkpllsel_use_hfclk(struct __prci_data *pd);
>  void sifive_prci_hfpclkpllsel_use_hfpclkpll(struct __prci_data *pd);
>  
>  /* Linux clock framework integration */
> -long sifive_prci_wrpll_round_rate(struct clk *hw, unsigned long rate,
> +long sifive_prci_wrpll_round_rate(struct clk_hw *hw, unsigned long rate,
>  				  unsigned long *parent_rate);
> -int sifive_prci_wrpll_set_rate(struct clk *hw, unsigned long rate,
> +int sifive_prci_wrpll_set_rate(struct clk_hw *hw, unsigned long rate,
>  			       unsigned long parent_rate);
> -int sifive_clk_is_enabled(struct clk *hw);
> -int sifive_prci_clock_enable(struct clk *hw);
> -void sifive_prci_clock_disable(struct clk *hw);
> -unsigned long sifive_prci_wrpll_recalc_rate(struct clk *hw,
> +int sifive_clk_is_enabled(struct clk_hw *hw);
> +int sifive_prci_clock_enable(struct clk_hw *hw);
> +void sifive_prci_clock_disable(struct clk_hw *hw);
> +unsigned long sifive_prci_wrpll_recalc_rate(struct clk_hw *hw,
>  					    unsigned long parent_rate);
> -unsigned long sifive_prci_tlclksel_recalc_rate(struct clk *hw,
> +unsigned long sifive_prci_tlclksel_recalc_rate(struct clk_hw *hw,
>  					       unsigned long parent_rate);
> -unsigned long sifive_prci_hfpclkplldiv_recalc_rate(struct clk *hw,
> +unsigned long sifive_prci_hfpclkplldiv_recalc_rate(struct clk_hw *hw,
>  						   unsigned long parent_rate);
>  
>  #endif /* __SIFIVE_CLK_SIFIVE_PRCI_H */
> 

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  reply	other threads:[~2021-06-11  9:20 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-02  9:54 [PATCH v2 00/24] clk updates Sascha Hauer
2021-06-02  9:54 ` [PATCH 01/24] clk: clk-mux: Fix handling of CLK_MUX_HIWORD_MASK Sascha Hauer
2021-06-02 15:18   ` Ahmad Fatoum
2021-06-02  9:54 ` [PATCH 02/24] clk: introduce clk init op Sascha Hauer
2021-06-02  9:54 ` [PATCH 03/24] clk: rename clk_register() to bclk_register() Sascha Hauer
2021-06-02  9:54 ` [PATCH 04/24] clk: introduce struct clk_hw Sascha Hauer
2021-06-11  7:55   ` Ahmad Fatoum
2021-06-11  8:41     ` Sascha Hauer
2021-06-11  9:19       ` Ahmad Fatoum [this message]
2021-06-11 11:46         ` Sascha Hauer
2021-06-11 12:14           ` Ahmad Fatoum
2021-06-02  9:54 ` [PATCH 05/24] clk: introduce clk_register() Sascha Hauer
2021-06-02  9:54 ` [PATCH 06/24] clk: divider: Make clk_divider_ops const Sascha Hauer
2021-06-02  9:54 ` [PATCH 07/24] clk: divider: Add ro ops Sascha Hauer
2021-06-02  9:54 ` [PATCH 08/24] clk: divider: Make clk_mux_ops const Sascha Hauer
2021-06-02  9:54 ` [PATCH 09/24] clk: mux: Add ro ops Sascha Hauer
2021-06-02  9:54 ` [PATCH 10/24] clk: move fixed_factor to include/linux/clk.h Sascha Hauer
2021-06-02  9:54 ` [PATCH 11/24] Add rational_best_approximation() Sascha Hauer
2021-06-02 18:25   ` Trent Piepho
2021-06-07 11:22     ` Sascha Hauer
2021-06-02  9:54 ` [PATCH 12/24] clk: Update fractional divider from Linux Sascha Hauer
2021-06-02  9:54 ` [PATCH 13/24] clk: Add lock to different clock types Sascha Hauer
2021-06-02  9:54 ` [PATCH 14/24] clk: Add Linux functions to register a divider Sascha Hauer
2021-06-02  9:54 ` [PATCH 15/24] clk: Add Linux functions to register a fixed factor clock Sascha Hauer
2021-06-02  9:54 ` [PATCH 16/24] clk: Add Linux functions to register a gate Sascha Hauer
2021-06-02  9:55 ` [PATCH 17/24] clk: Add Linux functions to register a mux Sascha Hauer
2021-06-02  9:55 ` [PATCH 18/24] clk: Add CLK_GET_RATE_NOCACHE Sascha Hauer
2021-06-02  9:55 ` [PATCH 19/24] clk: Rename CLK_GATE_INVERTED to CLK_GATE_SET_TO_DISABLE Sascha Hauer
2021-06-02  9:55 ` [PATCH 20/24] clk: implement CLK_SET_RATE_UNGATE Sascha Hauer
2021-06-02  9:55 ` [PATCH 21/24] clk: implement set/get phase Sascha Hauer
2021-06-02  9:55 ` [PATCH 22/24] regmap: Add regmap_read_poll_timeout Sascha Hauer
2021-06-02  9:55 ` [PATCH 23/24] clk: rockchip: Update to current Linux Sascha Hauer
2021-06-02  9:55 ` [PATCH 24/24] clk: Rockchip: Add rk3568 clk support Sascha Hauer
2021-06-09  9:18   ` Ahmad Fatoum

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