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* [PATCH 1/2] ARM: mmu: inherit pte flags from pmd
@ 2021-06-18  8:09 Steffen Trumtrar
  2021-06-18  8:09 ` [PATCH 2/2] firmware: socfpga: set APPLYCFG after loading bitstream Steffen Trumtrar
  2021-06-21  4:33 ` [PATCH 1/2] ARM: mmu: inherit pte flags from pmd Sascha Hauer
  0 siblings, 2 replies; 4+ messages in thread
From: Steffen Trumtrar @ 2021-06-18  8:09 UTC (permalink / raw)
  To: Barebox List

From: Sascha Hauer <s.hauer@pengutronix.de>

When creating a 2nd level page table from a section inherit the flags
from the section rather than assuming the section was mapped cached
previously. This fixes creating a 2nd level pagetable when the section
was mapped differently than we expected.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/cpu/mmu.c | 28 ++++++++++++++++++++++++----
 1 file changed, 24 insertions(+), 4 deletions(-)

diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c
index 6af228505dd1..6388e1bf14f6 100644
--- a/arch/arm/cpu/mmu.c
+++ b/arch/arm/cpu/mmu.c
@@ -138,6 +138,29 @@ static u32 *arm_create_pte(unsigned long virt, uint32_t flags)
 	return table;
 }
 
+static u32 pmd_flags_to_pte(u32 pmd)
+{
+	u32 pte = 0;
+
+	if (pmd & PMD_SECT_BUFFERABLE)
+		pte |= PTE_BUFFERABLE;
+	if (pmd & PMD_SECT_CACHEABLE)
+		pte |= PTE_CACHEABLE;
+	if (pmd & PMD_SECT_nG)
+		pte |= PTE_EXT_NG;
+	if (pmd & PMD_SECT_XN)
+		pte |= PTE_EXT_XN;
+
+	/* TEX[2:0] */
+	pte |= PTE_EXT_TEX((pmd >> 12) & 7);
+	/* AP[1:0] */
+	pte |= ((pmd >> 10) & 0x3) << 4;
+	/* AP[2] */
+	pte |= ((pmd >> 15) & 0x1) << 9;
+
+	return pte;
+}
+
 int arch_remap_range(void *start, size_t size, unsigned flags)
 {
 	u32 addr = (u32)start;
@@ -206,11 +229,8 @@ int arch_remap_range(void *start, size_t size, unsigned flags)
 				 * If PTE is not found it means that
 				 * we needs to split this section and
 				 * create a new page table for it
-				 *
-				 * NOTE: Here we assume that section
-				 * we just split was mapped as cached
 				 */
-				table = arm_create_pte(addr, pte_flags_cached);
+				table = arm_create_pte(addr, pmd_flags_to_pte(*pgd));
 				pte = find_pte(addr);
 				BUG_ON(!pte);
 			}
-- 
2.29.2


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^ permalink raw reply	[flat|nested] 4+ messages in thread

* [PATCH 2/2] firmware: socfpga: set APPLYCFG after loading bitstream
  2021-06-18  8:09 [PATCH 1/2] ARM: mmu: inherit pte flags from pmd Steffen Trumtrar
@ 2021-06-18  8:09 ` Steffen Trumtrar
  2021-06-18  8:55   ` Ahmad Fatoum
  2021-06-21  4:33 ` [PATCH 1/2] ARM: mmu: inherit pte flags from pmd Sascha Hauer
  1 sibling, 1 reply; 4+ messages in thread
From: Steffen Trumtrar @ 2021-06-18  8:09 UTC (permalink / raw)
  To: Barebox List

To make changes to the SDRAM controller effective, the APPLYCFG bit must
be set after programming the bitstream to the FPGA. This has to be done
without any SDRAM usage. Therefore copy the function to execute to the
OCRAM and execute it from there.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
 .../mach-socfpga/include/mach/cyclone5-regs.h |  1 +
 drivers/firmware/Makefile                     |  2 +-
 drivers/firmware/socfpga.c                    | 21 +++++++++++++++++++
 drivers/firmware/socfpga_sdr.S                | 17 +++++++++++++++
 4 files changed, 40 insertions(+), 1 deletion(-)
 create mode 100644 drivers/firmware/socfpga_sdr.S

diff --git a/arch/arm/mach-socfpga/include/mach/cyclone5-regs.h b/arch/arm/mach-socfpga/include/mach/cyclone5-regs.h
index e88daf718917..1a7d787a27bf 100644
--- a/arch/arm/mach-socfpga/include/mach/cyclone5-regs.h
+++ b/arch/arm/mach-socfpga/include/mach/cyclone5-regs.h
@@ -18,5 +18,6 @@
 #define CYCLONE5_SYSMGR_ADDRESS		0xffd08000
 #define CYCLONE5_SCANMGR_ADDRESS	0xfff02000
 #define CYCLONE5_SMP_TWD_ADDRESS	0xfffec600
+#define CYCLONE5_OCRAM_ADDRESS		0xffff0000
 
 #endif /* __MACH_SOCFPGA_REGS_H */
diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile
index b162b08b0a80..bbd2bcda9780 100644
--- a/drivers/firmware/Makefile
+++ b/drivers/firmware/Makefile
@@ -1,3 +1,3 @@
 obj-$(CONFIG_FIRMWARE_ALTERA_SERIAL) += altera_serial.o
-obj-$(CONFIG_FIRMWARE_ALTERA_SOCFPGA) += socfpga.o
+obj-$(CONFIG_FIRMWARE_ALTERA_SOCFPGA) += socfpga.o socfpga_sdr.o
 obj-$(CONFIG_FIRMWARE_ZYNQMP_FPGA) += zynqmp-fpga.o
diff --git a/drivers/firmware/socfpga.c b/drivers/firmware/socfpga.c
index 393c78c45d79..c468c743720f 100644
--- a/drivers/firmware/socfpga.c
+++ b/drivers/firmware/socfpga.c
@@ -38,6 +38,9 @@
 #include <mach/cyclone5-reset-manager.h>
 #include <mach/cyclone5-regs.h>
 #include <mach/cyclone5-sdram.h>
+#include <asm/fncpy.h>
+#include <mmu.h>
+#include <asm/cache.h>
 
 #define FPGAMGRREGS_STAT			0x0
 #define FPGAMGRREGS_CTRL			0x4
@@ -77,6 +80,9 @@
 #define CDRATIO_x4	0x2
 #define CDRATIO_x8	0x3
 
+extern void socfpga_sdram_apply_static_cfg(void __iomem *sdrctrlgrp);
+extern void socfpga_sdram_apply_static_cfg_end(void *);
+
 struct fpgamgr {
 	struct firmware_handler fh;
 	struct device_d dev;
@@ -353,6 +359,9 @@ static int fpgamgr_program_finish(struct firmware_handler *fh)
 {
 	struct fpgamgr *mgr = container_of(fh, struct fpgamgr, fh);
 	int status;
+	unsigned int func_size = &socfpga_sdram_apply_static_cfg_end -
+				 &socfpga_sdram_apply_static_cfg;
+	void (*ocram_func)(void __iomem *ocram_base);
 
 	/* Ensure the FPGA entering config done */
 	status = fpgamgr_program_poll_cd(mgr);
@@ -382,6 +391,18 @@ static int fpgamgr_program_finish(struct firmware_handler *fh)
 		return status;
 	}
 
+	remap_range((void *)CYCLONE5_OCRAM_ADDRESS, PAGE_SIZE, MAP_CACHED);
+
+	dev_dbg(&mgr->dev, "Setting APPLYCFG bit...\n");
+
+	ocram_func = fncpy((void __iomem *)CYCLONE5_OCRAM_ADDRESS,
+			   &socfpga_sdram_apply_static_cfg, func_size);
+
+	sync_caches_for_execution();
+
+	ocram_func((void __iomem *) (CYCLONE5_SDR_ADDRESS +
+				     SDR_CTRLGRP_STATICCFG_ADDRESS));
+
 	return 0;
 }
 
diff --git a/drivers/firmware/socfpga_sdr.S b/drivers/firmware/socfpga_sdr.S
new file mode 100644
index 000000000000..d634d6362722
--- /dev/null
+++ b/drivers/firmware/socfpga_sdr.S
@@ -0,0 +1,17 @@
+#include <linux/linkage.h>
+
+	.arch	armv7-a
+	.arm
+
+/*
+ * r0 : sdram controller staticcfg
+ */
+
+ENTRY(socfpga_sdram_apply_static_cfg)
+	push {ip,lr}
+	ldr r1, [r0]
+	orr r1, r1, #8
+	str r1, [r0]
+	pop {ip,pc}
+	.align
+ENTRY(socfpga_sdram_apply_static_cfg_end)
-- 
2.29.2


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^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH 2/2] firmware: socfpga: set APPLYCFG after loading bitstream
  2021-06-18  8:09 ` [PATCH 2/2] firmware: socfpga: set APPLYCFG after loading bitstream Steffen Trumtrar
@ 2021-06-18  8:55   ` Ahmad Fatoum
  0 siblings, 0 replies; 4+ messages in thread
From: Ahmad Fatoum @ 2021-06-18  8:55 UTC (permalink / raw)
  To: Steffen Trumtrar, Barebox List



On 18.06.21 10:09, Steffen Trumtrar wrote:
> To make changes to the SDRAM controller effective, the APPLYCFG bit must
> be set after programming the bitstream to the FPGA. This has to be done
> without any SDRAM usage. Therefore copy the function to execute to the
> OCRAM and execute it from there.
> 
> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
> ---

> +extern void socfpga_sdram_apply_static_cfg(void __iomem *sdrctrlgrp);
> +extern void socfpga_sdram_apply_static_cfg_end(void *);
> +
>  struct fpgamgr {
>  	struct firmware_handler fh;
>  	struct device_d dev;
> @@ -353,6 +359,9 @@ static int fpgamgr_program_finish(struct firmware_handler *fh)
>  {
>  	struct fpgamgr *mgr = container_of(fh, struct fpgamgr, fh);
>  	int status;
> +	unsigned int func_size = &socfpga_sdram_apply_static_cfg_end -
> +				 &socfpga_sdram_apply_static_cfg;

This is wildly undefined. Kernel users of fncpy I looked at as well as the fncpy
documentation itself suggest doing the arithmetic in assembly instead. See below.

> +	void (*ocram_func)(void __iomem *ocram_base);
>  
>  	/* Ensure the FPGA entering config done */
>  	status = fpgamgr_program_poll_cd(mgr);
> @@ -382,6 +391,18 @@ static int fpgamgr_program_finish(struct firmware_handler *fh)
>  		return status;
>  	}
>  
> +	remap_range((void *)CYCLONE5_OCRAM_ADDRESS, PAGE_SIZE, MAP_CACHED);
> +
> +	dev_dbg(&mgr->dev, "Setting APPLYCFG bit...\n");
> +
> +	ocram_func = fncpy((void __iomem *)CYCLONE5_OCRAM_ADDRESS,
> +			   &socfpga_sdram_apply_static_cfg, func_size);
> +
> +	sync_caches_for_execution();
> +
> +	ocram_func((void __iomem *) (CYCLONE5_SDR_ADDRESS +
> +				     SDR_CTRLGRP_STATICCFG_ADDRESS));
> +
>  	return 0;
>  }
>  
> diff --git a/drivers/firmware/socfpga_sdr.S b/drivers/firmware/socfpga_sdr.S
> new file mode 100644
> index 000000000000..d634d6362722
> --- /dev/null
> +++ b/drivers/firmware/socfpga_sdr.S
> @@ -0,0 +1,17 @@
> +#include <linux/linkage.h>
> +
> +	.arch	armv7-a
> +	.arm
> +
> +/*
> + * r0 : sdram controller staticcfg
> + */
> +
> +ENTRY(socfpga_sdram_apply_static_cfg)
> +	push {ip,lr}
> +	ldr r1, [r0]
> +	orr r1, r1, #8
> +	str r1, [r0]
> +	pop {ip,pc}
> +	.align
> +ENTRY(socfpga_sdram_apply_static_cfg_end)

Alternative:

ENDPROC(socfpga_sdram_apply_static_cfg)

ENTRY(socfpga_sdram_apply_static_sz)      
	.word . - socfpga_sdram_apply_static_cfg

And then size is accessible from C with
extern const u32 socfpga_sdram_apply_static_cfg_sz;

This makes for a clean disassembly and avoids the undefined
behavior above.

-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH 1/2] ARM: mmu: inherit pte flags from pmd
  2021-06-18  8:09 [PATCH 1/2] ARM: mmu: inherit pte flags from pmd Steffen Trumtrar
  2021-06-18  8:09 ` [PATCH 2/2] firmware: socfpga: set APPLYCFG after loading bitstream Steffen Trumtrar
@ 2021-06-21  4:33 ` Sascha Hauer
  1 sibling, 0 replies; 4+ messages in thread
From: Sascha Hauer @ 2021-06-21  4:33 UTC (permalink / raw)
  To: Steffen Trumtrar; +Cc: Barebox List

On Fri, Jun 18, 2021 at 10:09:38AM +0200, Steffen Trumtrar wrote:
> From: Sascha Hauer <s.hauer@pengutronix.de>
> 
> When creating a 2nd level page table from a section inherit the flags
> from the section rather than assuming the section was mapped cached
> previously. This fixes creating a 2nd level pagetable when the section
> was mapped differently than we expected.
> 
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
>  arch/arm/cpu/mmu.c | 28 ++++++++++++++++++++++++----
>  1 file changed, 24 insertions(+), 4 deletions(-)

Applied this one only for now, thanks

Sascha

-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2021-06-21  4:35 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-06-18  8:09 [PATCH 1/2] ARM: mmu: inherit pte flags from pmd Steffen Trumtrar
2021-06-18  8:09 ` [PATCH 2/2] firmware: socfpga: set APPLYCFG after loading bitstream Steffen Trumtrar
2021-06-18  8:55   ` Ahmad Fatoum
2021-06-21  4:33 ` [PATCH 1/2] ARM: mmu: inherit pte flags from pmd Sascha Hauer

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