From: Ahmad Fatoum <a.fatoum@pengutronix.de>
To: barebox@lists.infradead.org
Cc: Ahmad Fatoum <a.fatoum@pengutronix.de>
Subject: [PATCH master] ARM: i.MX8M: nxp-imx8mn-evk: use regular i2c read for device detection
Date: Sat, 30 Oct 2021 16:19:34 +0200 [thread overview]
Message-ID: <20211030141934.2207659-1-a.fatoum@pengutronix.de> (raw)
The barebox-nxp-imx8mn-evk image supports both DDR4 and LPDDR4 variants
by probing for the PMIC in use as the former uses a BD71847 and the
latter a PCA9450B.
The PCA9450B was observed to hang on the 0-byte (probe) reads.
This results in I/O errors during later PMIC writes and the image
would only boot on the EVKs with DDR4, which have the other PMIC.
Fix this by switching to a 1 byte read instead. Change tested on
i.MX8MN DDR4 EVK as well as another board with LPDDR4.
While at it, note the address of the PMIC in the error message, so it's
clear, what the result of the i2c probe was.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
arch/arm/boards/nxp-imx8mn-evk/lowlevel.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boards/nxp-imx8mn-evk/lowlevel.c b/arch/arm/boards/nxp-imx8mn-evk/lowlevel.c
index bac632aa431b..de53213ebc77 100644
--- a/arch/arm/boards/nxp-imx8mn-evk/lowlevel.c
+++ b/arch/arm/boards/nxp-imx8mn-evk/lowlevel.c
@@ -56,7 +56,7 @@ static void pmic_reg_write(void *i2c, int addr, int reg, uint8_t val)
ret = i2c_fsl_xfer(i2c, msgs, ARRAY_SIZE(msgs));
if (ret != 1)
- pr_err("Failed to write to pmic %d\n", ret);
+ pr_err("Failed to write to pmic@%x: %d\n", addr, ret);
}
static int power_init_board_pca9450(void *i2c, int addr)
@@ -66,7 +66,8 @@ static int power_init_board_pca9450(void *i2c, int addr)
{
.addr = addr,
.buf = buf,
- .flags = I2C_M_RD
+ .flags = I2C_M_RD,
+ .len = 1,
},
};
--
2.30.2
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next reply other threads:[~2021-10-30 14:21 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-30 14:19 Ahmad Fatoum [this message]
2021-11-01 9:10 ` Sascha Hauer
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