[PATCH 0/7] ARM: i.MX6: clk updates

[PATCH 0/7] ARM: i.MX6: clk updates

[Sascha Hauer]

This branch fixes some odd issues in the i.MX6 clock tree. The i.MX6Q
and i.MX6D SoC variants need a workaround for the PFDs and it turned
out we have that workaround twice: once in the clk driver and then again
in architecture code. When deep probe is enabled the order in which they
run may be changed. The difference with both workarounds is that the one
in the architecture code leaves the PFD clocks enabled and the one in
the clock driver leaves them disabled. That is still not a problem, but
our clock driver lacks the hdmi_isfr clock, so that the i.MX hdmi driver
works on a dummy clock instead. This works when the architecture
workaround runs after the one in the clk driver, but when deep probe
is enabled and the order changes then the hdmi driver finds its clock
disabled and doesn't work.

The issues are resolved in this series: The hdmi_isfr clock is added to
the clock tree and one of the duplicated workarounds is removed. There
are some other patches I came along while investigating why hdmi doesn't
work with deep probe enabled.

Sascha Hauer (7):
  clk: imx6: Add hdmi_isfr clk
  clk: imx6: fix axi_sels
  clk: imx6: Fix periph_clk2_sel and periph2_clk2_sel clocks
  clk: imx6: emi_sel clock muxing
  clk: imx6: fix cko1_sels
  clk: imx6: do pfd workaround unconditionally
  ARM: i.MX: Remove duplicate PFD workaround

 arch/arm/mach-imx/imx6.c   | 44 --------------------------------------
 drivers/clk/imx/clk-imx6.c | 37 ++++++++++++++++++++++++--------
 2 files changed, 28 insertions(+), 53 deletions(-)

-- 
2.30.2


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[PATCH 1/7] clk: imx6: Add hdmi_isfr clk

[Sascha Hauer]

The hdmi_isfr clk is requested and enabled by the hdmi driver, but it is
never registered, so effectively a dummy clk is used in the hdmi driver.
Add the clk and its parents so that the real clk is used.
One of the parents is pll3_pfd1_540m which happens to be enabled in
our pfd clock workaround in imx6_init_lowlevel(). This patch is
necessary when that workaround is removed later.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/clk/imx/clk-imx6.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/imx/clk-imx6.c b/drivers/clk/imx/clk-imx6.c
index e3afcf7858..aa5876d21b 100644
--- a/drivers/clk/imx/clk-imx6.c
+++ b/drivers/clk/imx/clk-imx6.c
@@ -152,7 +152,7 @@ static const char *cko1_sels[] = {
 	"pll2_bus",
 	"pll1_sys",
 	"pll5_video",
-	"dummy",
+	"video_27m",
 	"axi",
 	"enfc",
 	"ipu1_di0",
@@ -612,6 +612,8 @@ static void imx6_add_video_clks(void __iomem *anab, void __iomem *cb, struct dev
 	clks[IMX6QDL_CLK_IPU2_DI0_PRE]     = imx_clk_divider("ipu2_di0_pre",     "ipu2_di0_pre_sel",  cb + 0x38, 3,  3);
 	clks[IMX6QDL_CLK_IPU2_DI1_PRE]     = imx_clk_divider("ipu2_di1_pre",     "ipu2_di1_pre_sel",  cb + 0x38, 12, 3);
 
+	clks[IMX6QDL_CLK_HDMI_IAHB]    = imx_clk_gate2("hdmi_iahb",     "ahb",               cb + 0x70, 0);
+	clks[IMX6QDL_CLK_HDMI_ISFR]    = imx_clk_gate2("hdmi_isfr",     "mipi_core_cfg",     cb + 0x70, 4);
 	clks[IMX6QDL_CLK_IPU1]         = imx_clk_gate2("ipu1",          "ipu1_podf",         cb + 0x74, 0);
 	clks[IMX6QDL_CLK_IPU1_DI0]     = imx_clk_gate2("ipu1_di0",      "ipu1_di0_sel",      cb + 0x74, 2);
 	clks[IMX6QDL_CLK_IPU1_DI1]     = imx_clk_gate2("ipu1_di1",      "ipu1_di1_sel",      cb + 0x74, 4);
@@ -620,6 +622,8 @@ static void imx6_add_video_clks(void __iomem *anab, void __iomem *cb, struct dev
 	clks[IMX6QDL_CLK_LDB_DI0]      = imx_clk_gate2("ldb_di0",       "ldb_di0_podf",      cb + 0x74, 12);
 	clks[IMX6QDL_CLK_LDB_DI1]      = imx_clk_gate2("ldb_di1",       "ldb_di1_podf",      cb + 0x74, 14);
 	clks[IMX6QDL_CLK_IPU2_DI1]     = imx_clk_gate2("ipu2_di1",      "ipu2_di1_sel",      cb + 0x74, 10);
+	clks[IMX6QDL_CLK_MIPI_CORE_CFG] = imx_clk_gate2("mipi_core_cfg", "video_27m", cb + 0x74, 16);
+	clks[IMX6QDL_CLK_VIDEO_27M]    = imx_clk_fixed_factor("video_27m", "pll3_pfd1_540m", 1, 20);
 
 	clk_set_parent(clks[IMX6QDL_CLK_IPU1_DI0_SEL], clks[IMX6QDL_CLK_IPU1_DI0_PRE]);
 	clk_set_parent(clks[IMX6QDL_CLK_IPU1_DI1_SEL], clks[IMX6QDL_CLK_IPU1_DI1_PRE]);
-- 
2.30.2


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[PATCH 2/7] clk: imx6: fix axi_sels

[Sascha Hauer]

Adaption of Kernel commit:

| commit a08b9bc586a7810cdebbc316d5cbaed56a2a04a9
| Author:     Anson Huang <b20788@freescale.com>
| Commit:     Shawn Guo <shawn.guo@linaro.org>
| CommitDate: Mon Jun 3 13:47:12 2013 +0800
|
| ARM: imx: clk-imx6q: AXI clock select index is incorrect
|
| The AXI clock mux should be as below:
|
|  00: periph;
|  01: pll2_pfd2_396m;
|  10: periph;
|  11: pll3_pfd1_540m;

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/clk/imx/clk-imx6.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/imx/clk-imx6.c b/drivers/clk/imx/clk-imx6.c
index aa5876d21b..8cc4c2a08f 100644
--- a/drivers/clk/imx/clk-imx6.c
+++ b/drivers/clk/imx/clk-imx6.c
@@ -106,6 +106,7 @@ static const char *periph2_sels[] = {
 static const char *axi_sels[] = {
 	"periph",
 	"pll2_pfd2_396m",
+	"periph",
 	"pll3_pfd1_540m",
 };
 
-- 
2.30.2


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[PATCH 3/7] clk: imx6: Fix periph_clk2_sel and periph2_clk2_sel clocks

[Sascha Hauer]

Adaption of kernel commit:

| commit 72cd7447e72a13ce72d760b42ec295430f77300a
| Author: Philipp Zabel <p.zabel@pengutronix.de>
| Date:   Wed Apr 17 12:05:58 2013 +0200
|
|     ARM i.MX6q: Fix periph_clk2_sel and periph2_clk2_sel clocks
|
|     The periph_clk2_sel mux can be set to pll3, osc/pll1_ref_clk, or osc/
|     pll2_burn_in_clk. The periph2_clk2_sel mux can be set to pll3 or pll2.
|
|     Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
|     Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/clk/imx/clk-imx6.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/imx/clk-imx6.c b/drivers/clk/imx/clk-imx6.c
index 8cc4c2a08f..a23aff5266 100644
--- a/drivers/clk/imx/clk-imx6.c
+++ b/drivers/clk/imx/clk-imx6.c
@@ -91,6 +91,13 @@ static const char *periph_pre_sels[] = {
 static const char *periph_clk2_sels[] = {
 	"pll3_usb_otg",
 	"osc",
+	"osc",
+	"dummy",
+};
+
+static const char *periph2_clk2_sels[] = {
+	"pll3_usb_otg",
+	"pll2_bus",
 };
 
 static const char *periph_sels[] = {
@@ -700,7 +707,7 @@ static int imx6_ccm_probe(struct device_d *dev)
 	clks[IMX6QDL_CLK_PERIPH_PRE]       = imx_clk_mux("periph_pre",       base + 0x18, 18, 2, periph_pre_sels,   ARRAY_SIZE(periph_pre_sels));
 	clks[IMX6QDL_CLK_PERIPH2_PRE]      = imx_clk_mux("periph2_pre",      base + 0x18, 21, 2, periph_pre_sels,   ARRAY_SIZE(periph_pre_sels));
 	clks[IMX6QDL_CLK_PERIPH_CLK2_SEL]  = imx_clk_mux("periph_clk2_sel",  base + 0x18, 12, 1, periph_clk2_sels,  ARRAY_SIZE(periph_clk2_sels));
-	clks[IMX6QDL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph_clk2_sels,  ARRAY_SIZE(periph_clk2_sels));
+	clks[IMX6QDL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels,  ARRAY_SIZE(periph2_clk2_sels));
 	clks[IMX6QDL_CLK_AXI_SEL]          = imx_clk_mux("axi_sel",          base + 0x14, 6,  2, axi_sels,          ARRAY_SIZE(axi_sels));
 	clks[IMX6QDL_CLK_USDHC1_SEL]       = imx_clk_mux("usdhc1_sel",       base + 0x1c, 16, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels));
 	clks[IMX6QDL_CLK_USDHC2_SEL]       = imx_clk_mux("usdhc2_sel",       base + 0x1c, 17, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels));
-- 
2.30.2


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[PATCH 4/7] clk: imx6: emi_sel clock muxing

[Sascha Hauer]

Adaption of kernel commit:

| commit 3b79cd15bfc5f1ddb5e387310fa3dbb09b81b552
| Author: Liu Ying <Ying.Liu@freescale.com>
| Date:   Wed Jul 3 15:29:06 2013 +0800
|
|     ARM: i.MX6Q: correct emi_sel clock muxing
|
|     The correct muxing for emi_sel clock should be
|     2b'00 - 396M PFD
|     2b'01 - PLL3
|     2b'10 - AXI clk root
|     2b'11 - 352M PFD
|
|     This patch corrects the muxing in the clock driver.
|
|     Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
|     Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|     Acked-by: Dirk Behme <dirk.behme@de.bosch.com>

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/clk/imx/clk-imx6.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/imx/clk-imx6.c b/drivers/clk/imx/clk-imx6.c
index a23aff5266..56ae09fc7b 100644
--- a/drivers/clk/imx/clk-imx6.c
+++ b/drivers/clk/imx/clk-imx6.c
@@ -139,6 +139,13 @@ static const char *enfc_sels_plus[] = {
 };
 
 static const char *eim_sels[] = {
+	"pll2_pfd2_396m",
+	"pll3_usb_otg",
+	"axi",
+	"pll2_pfd0_352m",
+};
+
+static const char *eim_slow_sels[] = {
 	"axi",
 	"pll3_usb_otg",
 	"pll2_pfd2_396m",
@@ -718,7 +725,7 @@ static int imx6_ccm_probe(struct device_d *dev)
 	else
 		clks[IMX6QDL_CLK_ENFC_SEL]         = imx_clk_mux("enfc_sel",         base + 0x2c, 16, 2, enfc_sels,         ARRAY_SIZE(enfc_sels));
 	clks[IMX6QDL_CLK_EIM_SEL]          = imx_clk_mux("eim_sel",          base + 0x1c, 27, 2, eim_sels,          ARRAY_SIZE(eim_sels));
-	clks[IMX6QDL_CLK_EIM_SLOW_SEL]     = imx_clk_mux("eim_slow_sel",     base + 0x1c, 29, 2, eim_sels,          ARRAY_SIZE(eim_sels));
+	clks[IMX6QDL_CLK_EIM_SLOW_SEL]     = imx_clk_mux("eim_slow_sel",     base + 0x1c, 29, 2, eim_sels,          ARRAY_SIZE(eim_slow_sels));
 	clks[IMX6QDL_CLK_VDO_AXI_SEL]      = imx_clk_mux("vdo_axi_sel",      base + 0x18, 11, 1, vdo_axi_sels,      ARRAY_SIZE(vdo_axi_sels));
 	clks[IMX6QDL_CLK_CKO1_SEL]         = imx_clk_mux("cko1_sel",         base + 0x60, 0,  4, cko1_sels,         ARRAY_SIZE(cko1_sels));
 	clks[IMX6QDL_CLK_CKO2_SEL]         = imx_clk_mux("cko2_sel",         base + 0x60, 16, 5, cko2_sels,         ARRAY_SIZE(cko2_sels));
-- 
2.30.2


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[PATCH 5/7] clk: imx6: fix cko1_sels

[Sascha Hauer]

cko1 outputs pll5_video_div, not pll5_video. Also it outputs
pll4_audio_div, not pll4_audio.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/clk/imx/clk-imx6.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/imx/clk-imx6.c b/drivers/clk/imx/clk-imx6.c
index 56ae09fc7b..4f843b8ba7 100644
--- a/drivers/clk/imx/clk-imx6.c
+++ b/drivers/clk/imx/clk-imx6.c
@@ -166,7 +166,7 @@ static const char *cko1_sels[] = {
 	"pll3_usb_otg",
 	"pll2_bus",
 	"pll1_sys",
-	"pll5_video",
+	"pll5_video_div",
 	"video_27m",
 	"axi",
 	"enfc",
@@ -178,7 +178,7 @@ static const char *cko1_sels[] = {
 	"ipg",
 	"ipg_per",
 	"ckil",
-	"pll4_audio",
+	"pll4_audio_div",
 };
 
 static const char *cko2_sels[] = {
-- 
2.30.2


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[PATCH 6/7] clk: imx6: do pfd workaround unconditionally

[Sascha Hauer]

The i.MX6D and i.MX6Q SoC variants need a workaround for the PFDs which
may not work properly when they are not gated/ungated once during
startup. We currently have this workaround twice, once in the clock
driver and once in imx6_init_lowlevel(). The latter will be removed, but
before doing that the workaround in the clock driver is done
unconditionally and not only when the IPU driver is enabled.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/clk/imx/clk-imx6.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/imx/clk-imx6.c b/drivers/clk/imx/clk-imx6.c
index 4f843b8ba7..06cc992b72 100644
--- a/drivers/clk/imx/clk-imx6.c
+++ b/drivers/clk/imx/clk-imx6.c
@@ -588,10 +588,6 @@ static void imx6_add_video_clks(void __iomem *anab, void __iomem *cb, struct dev
 	clks[IMX6QDL_CLK_IPU1_SEL]         = imx_clk_mux("ipu1_sel",         cb + 0x3c, 9,  2, ipu_sels,          ARRAY_SIZE(ipu_sels));
 	clks[IMX6QDL_CLK_IPU2_SEL]         = imx_clk_mux("ipu2_sel",         cb + 0x3c, 14, 2, ipu_sels,          ARRAY_SIZE(ipu_sels));
 
-	disable_anatop_clocks(anab);
-
-	imx6q_mmdc_ch1_mask_handshake(cb);
-
 	if (cpu_mx6_has_err009219()) {
 		/*
 		 * The LDB_DI0/1_SEL muxes should be read-only due to a hardware
@@ -807,6 +803,10 @@ static int imx6_ccm_probe(struct device_d *dev)
 
 	clkdev_add_physbase(clks[IMX6QDL_CLK_IPG], MX6_OCOTP_BASE_ADDR, NULL);
 
+	disable_anatop_clocks(anatop_base);
+
+	imx6q_mmdc_ch1_mask_handshake(ccm_base);
+
 	if (IS_ENABLED(CONFIG_DRIVER_VIDEO_IMX_IPUV3))
 		imx6_add_video_clks(anatop_base, ccm_base, dev->device_node);
 
-- 
2.30.2


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[PATCH 7/7] ARM: i.MX: Remove duplicate PFD workaround

[Sascha Hauer]

The i.MX6Q and i.MX6D SoC variants need a workaround for broken PFDs.
That was added to the architecture code in f1f6d76 ("ARM: i.MX6: correct
work flow of PFDs from uboot-sources") and then added again in b534f79
("clk: imx6: Fix procedure to switch the parent of LDB_DI_CLK"). We only
need this once, so remove the workaround in the architecture code.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/mach-imx/imx6.c | 44 ----------------------------------------
 1 file changed, 44 deletions(-)

diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
index 7bd29446e9..bf8d1a0065 100644
--- a/arch/arm/mach-imx/imx6.c
+++ b/arch/arm/mach-imx/imx6.c
@@ -54,17 +54,9 @@ static void imx6_configure_aips(void __iomem *aips)
 
 static void imx6_init_lowlevel(void)
 {
-	bool is_imx6q = __imx6_cpu_type() == IMX6_CPUTYPE_IMX6Q;
-	bool is_imx6d = __imx6_cpu_type() == IMX6_CPUTYPE_IMX6D;
 	bool is_imx6ull = __imx6_cpu_type() == IMX6_CPUTYPE_IMX6ULL;
 	bool is_imx6sx = __imx6_cpu_type() == IMX6_CPUTYPE_IMX6SX;
 
-	uint32_t val_480;
-	uint32_t val_528;
-	uint32_t periph_sel_1;
-	uint32_t periph_sel_2;
-	uint32_t reg;
-
 	/*
 	 * Before reset the controller imx6_boot_save_loc() must be called to
 	 * detect serial-downloader fall back boots. For further information
@@ -77,42 +69,6 @@ static void imx6_init_lowlevel(void)
 	imx6_configure_aips(IOMEM(MX6_AIPS2_ON_BASE_ADDR));
 	if (is_imx6ull || is_imx6sx)
 		imx6_configure_aips(IOMEM(MX6_AIPS3_ON_BASE_ADDR));
-
-	/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
-	 * to make sure PFD is working right, otherwise, PFDs may
-	 * not output clock after reset, MX6DL and MX6SL have added 396M pfd
-	 * workaround in ROM code, as bus clock need it.
-	 * Don't reset PLL2 PFD0 / PLL2 PFD2 if is's used by periph_clk.
-	 */
-	if (is_imx6q || is_imx6d) {
-		val_480 = BM_ANADIG_PFD_480_PFD3_CLKGATE |
-			   BM_ANADIG_PFD_480_PFD2_CLKGATE |
-			   BM_ANADIG_PFD_480_PFD1_CLKGATE |
-			   BM_ANADIG_PFD_480_PFD0_CLKGATE;
-
-		val_528 = BM_ANADIG_PFD_528_PFD3_CLKGATE |
-			   BM_ANADIG_PFD_528_PFD1_CLKGATE;
-
-		reg = readl(MXC_CCM_CBCMR);
-		periph_sel_1 = (reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
-			>> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
-
-		periph_sel_2 = (reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
-			>> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET;
-
-		if ((periph_sel_1 != 0x2) && (periph_sel_2 != 0x2))
-			val_528 |= BM_ANADIG_PFD_528_PFD0_CLKGATE;
-
-		if ((periph_sel_1 != 0x1) && (periph_sel_2 != 0x1)
-		    && (periph_sel_1 != 0x3) && (periph_sel_2 != 0x3))
-			val_528 |= BM_ANADIG_PFD_528_PFD2_CLKGATE;
-
-		writel(val_480, MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_480_SET);
-		writel(val_528, MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_SET);
-
-		writel(val_480, MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_480_CLR);
-		writel(val_528, MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_CLR);
-	}
 }
 
 static bool imx6_has_ipu(void)
-- 
2.30.2


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