From: Lucas Stach <l.stach@pengutronix.de> To: barebox@lists.infradead.org Subject: [PATCH] ARM: imx: esdctl: fix LPDDR4 size calculation Date: Fri, 13 May 2022 16:16:25 +0200 [thread overview] Message-ID: <20220513141625.1411217-1-l.stach@pengutronix.de> (raw) The DDRC only uses the DEVICE_CONFIG field for memory types other than LPDDR4. While LPDDR4 always has a bus width of x32, the script aid generates the value for a x16 bus, as this was apparently used for the controller validation. This resulted in the calculated DRAM size to be halved on boards with LPDDR4 memory. Fixes: d8d5778ee8c2 ("ARM: imx: Correct mem size calculation for 4/8/16/32 bit bus width") Signed-off-by: Lucas Stach <l.stach@pengutronix.de> --- arch/arm/mach-imx/esdctl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c index d3dbfff423da..4c8765c193d0 100644 --- a/arch/arm/mach-imx/esdctl.c +++ b/arch/arm/mach-imx/esdctl.c @@ -392,7 +392,7 @@ imx_ddrc_sdram_size(void __iomem *ddrc, const u32 addrmap[], } /* Bus width in bytes, 0 means half byte or 4-bit mode */ - if (is_imx8) + if (is_imx8 && !(mstr & DDRC_MSTR_LPDDR4)) width = (1 << FIELD_GET(DDRC_MSTR_DEVICE_CONFIG, mstr)) >> 1; else width = 4; -- 2.35.3 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
next reply other threads:[~2022-05-13 14:18 UTC|newest] Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-05-13 14:16 Lucas Stach [this message] 2022-05-16 8:10 ` Sascha Hauer 2022-05-20 14:16 ` Teresa Remmet 2022-05-20 14:33 ` Lucas Stach 2022-05-20 14:55 ` Teresa Remmet
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