* [PATCH 0/3] arm: rockchip: add support for the radxa rock3 board
@ 2022-05-31 16:26 Michael Riesch
2022-05-31 16:26 ` [PATCH 1/3] HACK: add device trees for rk3568 Michael Riesch
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: Michael Riesch @ 2022-05-31 16:26 UTC (permalink / raw)
To: barebox; +Cc: Michael Riesch
Hi all,
This series aims to add support for the Radxa ROCK3 Model A single
board computer featuring the Rockchip RK3568 SoC.
The first two patches mock the dts sync from the Linux kernel and
introduce the device tree for the board (will appear in Linux
v5.19-rc1). These patches can be dropped of course and are added only
for convenience.
There are a few open issues that are somewhat shared by all RK356x
boards:
- The RAM size is defined in the device tree and limited to 2 GB.
This is correct for the 2 GB version lying around on my desk, but
it should be noted that there are also 4 GB and 8 GB versions of
this board available.
- The eMMC controller seems to require the "no-sd" property in the
device tree, which is not present in the mainline version. The
quick fix is to provide this property in the barebox dts.
- RFC: The "rk3568_start" method in the low-level board code seems
to be shared by all RK356x boards. Can it be refactored and made
non-static? If yes, what would be a reasonable location for the
new function?
- Of course the IO domain bits are board specific. In the long run
they should be replaced anyway by a proper iodomain driver. For
the time being I believe they could remain in the ENTRY_FUNCTION.
Apart from these issues (which are not exactly critical) barebox
works just fine on this neat little board.
Looking forward to your comments!
Best regards,
Michael
Michael Riesch (3):
HACK: add device trees for rk3568
HACK: add device tree for radxa rock3 model a
arm: rockchip: add support for the radxa rock3 board
Documentation/boards/rockchip.rst | 1 +
arch/arm/boards/Makefile | 1 +
arch/arm/boards/radxa-rock3/.gitignore | 1 +
arch/arm/boards/radxa-rock3/Makefile | 3 +
arch/arm/boards/radxa-rock3/board.c | 48 ++
arch/arm/boards/radxa-rock3/lowlevel.c | 44 ++
arch/arm/configs/rockchip_v8_defconfig | 1 +
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3568-rock-3a.dts | 54 +++
arch/arm/mach-rockchip/Kconfig | 6 +
dts/src/arm64/rockchip/rk3568-rock-3a.dts | 562 ++++++++++++++++++++++
dts/src/arm64/rockchip/rk3568.dtsi | 23 +
dts/src/arm64/rockchip/rk356x.dtsi | 74 ++-
images/Makefile.rockchip | 7 +
14 files changed, 825 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boards/radxa-rock3/.gitignore
create mode 100644 arch/arm/boards/radxa-rock3/Makefile
create mode 100644 arch/arm/boards/radxa-rock3/board.c
create mode 100644 arch/arm/boards/radxa-rock3/lowlevel.c
create mode 100644 arch/arm/dts/rk3568-rock-3a.dts
create mode 100644 dts/src/arm64/rockchip/rk3568-rock-3a.dts
--
2.30.2
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^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 1/3] HACK: add device trees for rk3568
2022-05-31 16:26 [PATCH 0/3] arm: rockchip: add support for the radxa rock3 board Michael Riesch
@ 2022-05-31 16:26 ` Michael Riesch
2022-05-31 16:26 ` [PATCH 2/3] HACK: add device tree for radxa rock3 model a Michael Riesch
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Michael Riesch @ 2022-05-31 16:26 UTC (permalink / raw)
To: barebox; +Cc: Michael Riesch
Mock sync from Linux v5.19-rc1.
Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
---
dts/src/arm64/rockchip/rk3568.dtsi | 23 ++++++++++
dts/src/arm64/rockchip/rk356x.dtsi | 74 +++++++++++++++++++++++++++++-
2 files changed, 96 insertions(+), 1 deletion(-)
diff --git a/dts/src/arm64/rockchip/rk3568.dtsi b/dts/src/arm64/rockchip/rk3568.dtsi
index 5b0f528d68..5eafddf62e 100644
--- a/dts/src/arm64/rockchip/rk3568.dtsi
+++ b/dts/src/arm64/rockchip/rk3568.dtsi
@@ -8,6 +8,20 @@
/ {
compatible = "rockchip,rk3568";
+ sata0: sata@fc000000 {
+ compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
+ reg = <0 0xfc000000 0 0x1000>;
+ clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>,
+ <&cru CLK_SATA0_RXOOB>;
+ clock-names = "sata", "pmalive", "rxoob";
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&combphy0 PHY_TYPE_SATA>;
+ phy-names = "sata-phy";
+ ports-implemented = <0x1>;
+ power-domains = <&power RK3568_PD_PIPE>;
+ status = "disabled";
+ };
+
pipe_phy_grf0: syscon@fdc70000 {
compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
reg = <0x0 0xfdc70000 0x0 0x1000>;
@@ -99,6 +113,10 @@
};
};
+&pipegrf {
+ compatible = "rockchip,rk3568-pipe-grf", "syscon";
+};
+
&power {
power-domain@RK3568_PD_PIPE {
reg = <RK3568_PD_PIPE>;
@@ -114,3 +132,8 @@
#power-domain-cells = <0>;
};
};
+
+&usb_host0_xhci {
+ phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>;
+ phy-names = "usb2-phy", "usb3-phy";
+};
diff --git a/dts/src/arm64/rockchip/rk356x.dtsi b/dts/src/arm64/rockchip/rk356x.dtsi
index 7cdef800cb..1042e68602 100644
--- a/dts/src/arm64/rockchip/rk356x.dtsi
+++ b/dts/src/arm64/rockchip/rk356x.dtsi
@@ -230,6 +230,68 @@
};
};
+ sata1: sata@fc400000 {
+ compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
+ reg = <0 0xfc400000 0 0x1000>;
+ clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>,
+ <&cru CLK_SATA1_RXOOB>;
+ clock-names = "sata", "pmalive", "rxoob";
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&combphy1 PHY_TYPE_SATA>;
+ phy-names = "sata-phy";
+ ports-implemented = <0x1>;
+ power-domains = <&power RK3568_PD_PIPE>;
+ status = "disabled";
+ };
+
+ sata2: sata@fc800000 {
+ compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
+ reg = <0 0xfc800000 0 0x1000>;
+ clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>,
+ <&cru CLK_SATA2_RXOOB>;
+ clock-names = "sata", "pmalive", "rxoob";
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&combphy2 PHY_TYPE_SATA>;
+ phy-names = "sata-phy";
+ ports-implemented = <0x1>;
+ power-domains = <&power RK3568_PD_PIPE>;
+ status = "disabled";
+ };
+
+ usb_host0_xhci: usb@fcc00000 {
+ compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
+ reg = <0x0 0xfcc00000 0x0 0x400000>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>,
+ <&cru ACLK_USB3OTG0>;
+ clock-names = "ref_clk", "suspend_clk",
+ "bus_clk";
+ dr_mode = "otg";
+ phy_type = "utmi_wide";
+ power-domains = <&power RK3568_PD_PIPE>;
+ resets = <&cru SRST_USB3OTG0>;
+ snps,dis_u2_susphy_quirk;
+ status = "disabled";
+ };
+
+ usb_host1_xhci: usb@fd000000 {
+ compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
+ reg = <0x0 0xfd000000 0x0 0x400000>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>,
+ <&cru ACLK_USB3OTG1>;
+ clock-names = "ref_clk", "suspend_clk",
+ "bus_clk";
+ dr_mode = "host";
+ phys = <&usb2phy0_host>, <&combphy1 PHY_TYPE_USB3>;
+ phy-names = "usb2-phy", "usb3-phy";
+ phy_type = "utmi_wide";
+ power-domains = <&power RK3568_PD_PIPE>;
+ resets = <&cru SRST_USB3OTG1>;
+ snps,dis_u2_susphy_quirk;
+ status = "disabled";
+ };
+
gic: interrupt-controller@fd400000 {
compatible = "arm,gic-v3";
reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
@@ -297,7 +359,6 @@
};
pipegrf: syscon@fdc50000 {
- compatible = "rockchip,rk3568-pipe-grf", "syscon";
reg = <0x0 0xfdc50000 0x0 0x1000>;
};
@@ -717,6 +778,17 @@
status = "disabled";
};
+ sfc: spi@fe300000 {
+ compatible = "rockchip,sfc";
+ reg = <0x0 0xfe300000 0x0 0x4000>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
+ clock-names = "clk_sfc", "hclk_sfc";
+ pinctrl-0 = <&fspi_pins>;
+ pinctrl-names = "default";
+ status = "disabled";
+ };
+
sdhci: mmc@fe310000 {
compatible = "rockchip,rk3568-dwcmshc";
reg = <0x0 0xfe310000 0x0 0x10000>;
--
2.30.2
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^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 2/3] HACK: add device tree for radxa rock3 model a
2022-05-31 16:26 [PATCH 0/3] arm: rockchip: add support for the radxa rock3 board Michael Riesch
2022-05-31 16:26 ` [PATCH 1/3] HACK: add device trees for rk3568 Michael Riesch
@ 2022-05-31 16:26 ` Michael Riesch
2022-05-31 16:26 ` [PATCH 3/3] arm: rockchip: add support for the radxa rock3 board Michael Riesch
2022-06-08 7:19 ` [PATCH 0/3] " Sascha Hauer
3 siblings, 0 replies; 5+ messages in thread
From: Michael Riesch @ 2022-05-31 16:26 UTC (permalink / raw)
To: barebox; +Cc: Michael Riesch
Mock sync from Linux v5.19-rc1.
Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
---
dts/src/arm64/rockchip/rk3568-rock-3a.dts | 562 ++++++++++++++++++++++
1 file changed, 562 insertions(+)
create mode 100644 dts/src/arm64/rockchip/rk3568-rock-3a.dts
diff --git a/dts/src/arm64/rockchip/rk3568-rock-3a.dts b/dts/src/arm64/rockchip/rk3568-rock-3a.dts
new file mode 100644
index 0000000000..0813c0c5ab
--- /dev/null
+++ b/dts/src/arm64/rockchip/rk3568-rock-3a.dts
@@ -0,0 +1,562 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3568.dtsi"
+
+/ {
+ model = "Radxa ROCK3 Model A";
+ compatible = "radxa,rock3a", "rockchip,rk3568";
+
+ aliases {
+ ethernet0 = &gmac1;
+ mmc0 = &sdmmc0;
+ mmc1 = &sdhci;
+ };
+
+ chosen: chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_user: led-0 {
+ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
+ function = LED_FUNCTION_HEARTBEAT;
+ color = <LED_COLOR_ID_BLUE>;
+ linux,default-trigger = "heartbeat";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_user_en>;
+ };
+ };
+
+ rk809-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,name = "Analog RK809";
+ simple-audio-card,mclk-fs = <256>;
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s1_8ch>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&rk809>;
+ };
+ };
+
+ vcc12v_dcin: vcc12v-dcin {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcc3v3_sys: vcc3v3-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc5v0_usb: vcc5v0-usb {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc5v0_usb_host: vcc5v0-usb-host {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_usb_host_en>;
+ regulator-name = "vcc5v0_usb_host";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_usb>;
+ };
+
+ vcc5v0_usb_hub: vcc5v0-usb-hub-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_usb_hub_en>;
+ regulator-name = "vcc5v0_usb_hub";
+ regulator-always-on;
+ vin-supply = <&vcc5v0_usb>;
+ };
+
+ vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_usb_otg_en>;
+ regulator-name = "vcc5v0_usb_otg";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_usb>;
+ };
+};
+
+&combphy0 {
+ status = "okay";
+};
+
+&combphy1 {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&gmac1 {
+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
+ assigned-clock-rates = <0>, <125000000>;
+ clock_in_out = "output";
+ phy-handle = <&rgmii_phy1>;
+ phy-mode = "rgmii-id";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac1m1_miim
+ &gmac1m1_tx_bus2
+ &gmac1m1_rx_bus2
+ &gmac1m1_rgmii_clk
+ &gmac1m1_rgmii_bus>;
+ status = "okay";
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ vdd_cpu: regulator@1c {
+ compatible = "tcs,tcs4525";
+ reg = <0x1c>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ rk809: pmic@20 {
+ compatible = "rockchip,rk809";
+ reg = <0x20>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+ assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
+ assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
+ #clock-cells = <1>;
+ clock-names = "mclk";
+ clocks = <&cru I2S1_MCLKOUT_TX>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>;
+ rockchip,system-power-controller;
+ #sound-dai-cells = <0>;
+ vcc1-supply = <&vcc3v3_sys>;
+ vcc2-supply = <&vcc3v3_sys>;
+ vcc3-supply = <&vcc3v3_sys>;
+ vcc4-supply = <&vcc3v3_sys>;
+ vcc5-supply = <&vcc3v3_sys>;
+ vcc6-supply = <&vcc3v3_sys>;
+ vcc7-supply = <&vcc3v3_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc3v3_sys>;
+ wakeup-source;
+
+ regulators {
+ vdd_logic: DCDC_REG1 {
+ regulator-name = "vdd_logic";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-init-microvolt = <900000>;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_gpu: DCDC_REG2 {
+ regulator-name = "vdd_gpu";
+ regulator-always-on;
+ regulator-init-microvolt = <900000>;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vdd_npu: DCDC_REG4 {
+ regulator-name = "vdd_npu";
+ regulator-init-microvolt = <900000>;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8: DCDC_REG5 {
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_image: LDO_REG1 {
+ regulator-name = "vdda0v9_image";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda_0v9: LDO_REG2 {
+ regulator-name = "vdda_0v9";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_pmu: LDO_REG3 {
+ regulator-name = "vdda0v9_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vccio_acodec: LDO_REG4 {
+ regulator-name = "vccio_acodec";
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-name = "vccio_sd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_pmu: LDO_REG6 {
+ regulator-name = "vcc3v3_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcca_1v8: LDO_REG7 {
+ regulator-name = "vcca_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca1v8_pmu: LDO_REG8 {
+ regulator-name = "vcca1v8_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcca1v8_image: LDO_REG9 {
+ regulator-name = "vcca1v8_image";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3: SWITCH_REG1 {
+ regulator-name = "vcc_3v3";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_sd: SWITCH_REG2 {
+ regulator-name = "vcc3v3_sd";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+
+ codec {
+ mic-in-differential;
+ };
+ };
+};
+
+&i2s1_8ch {
+ rockchip,trcm-sync-tx-only;
+ status = "okay";
+};
+
+&mdio1 {
+ rgmii_phy1: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <ð_phy_rst>;
+ reset-assert-us = <20000>;
+ reset-deassert-us = <100000>;
+ reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&pinctrl {
+ ethernet {
+ eth_phy_rst: eth_phy_rst {
+ rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ leds {
+ led_user_en: led_user_en {
+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int: pmic_int {
+ rockchip,pins =
+ <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ usb {
+ vcc5v0_usb_host_en: vcc5v0_usb_host_en {
+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ vcc5v0_usb_hub_en: vcc5v0_usb_hub_en {
+ rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pmu_io_domains {
+ pmuio1-supply = <&vcc3v3_pmu>;
+ pmuio2-supply = <&vcc3v3_pmu>;
+ vccio1-supply = <&vccio_acodec>;
+ vccio2-supply = <&vcc_1v8>;
+ vccio3-supply = <&vccio_sd>;
+ vccio4-supply = <&vcc_1v8>;
+ vccio5-supply = <&vcc_3v3>;
+ vccio6-supply = <&vcc_1v8>;
+ vccio7-supply = <&vcc_3v3>;
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcca_1v8>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&sdmmc0 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc3v3_sd>;
+ vqmmc-supply = <&vccio_sd>;
+ status = "okay";
+};
+
+&tsadc {
+ rockchip,hw-tshut-mode = <1>;
+ rockchip,hw-tshut-polarity = <0>;
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host0_xhci {
+ extcon = <&usb2phy0>;
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
+
+&usb_host1_xhci {
+ status = "okay";
+};
+
+&usb2phy0 {
+ status = "okay";
+};
+
+&usb2phy0_host {
+ phy-supply = <&vcc5v0_usb_host>;
+ status = "okay";
+};
+
+&usb2phy0_otg {
+ vbus-supply = <&vcc5v0_usb_otg>;
+ status = "okay";
+};
+
+&usb2phy1 {
+ status = "okay";
+};
+
+&usb2phy1_host {
+ phy-supply = <&vcc5v0_usb_host>;
+ status = "okay";
+};
+
+&usb2phy1_otg {
+ phy-supply = <&vcc5v0_usb_host>;
+ status = "okay";
+};
--
2.30.2
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^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 3/3] arm: rockchip: add support for the radxa rock3 board
2022-05-31 16:26 [PATCH 0/3] arm: rockchip: add support for the radxa rock3 board Michael Riesch
2022-05-31 16:26 ` [PATCH 1/3] HACK: add device trees for rk3568 Michael Riesch
2022-05-31 16:26 ` [PATCH 2/3] HACK: add device tree for radxa rock3 model a Michael Riesch
@ 2022-05-31 16:26 ` Michael Riesch
2022-06-08 7:19 ` [PATCH 0/3] " Sascha Hauer
3 siblings, 0 replies; 5+ messages in thread
From: Michael Riesch @ 2022-05-31 16:26 UTC (permalink / raw)
To: barebox; +Cc: Michael Riesch
Add basic support for the Radxa ROCK3 Model A board (featuring
the Rockchip RK3568 SoC).
Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
---
Documentation/boards/rockchip.rst | 1 +
arch/arm/boards/Makefile | 1 +
arch/arm/boards/radxa-rock3/.gitignore | 1 +
arch/arm/boards/radxa-rock3/Makefile | 3 ++
arch/arm/boards/radxa-rock3/board.c | 48 +++++++++++++++++++++++
arch/arm/boards/radxa-rock3/lowlevel.c | 44 +++++++++++++++++++++
arch/arm/configs/rockchip_v8_defconfig | 1 +
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3568-rock-3a.dts | 54 ++++++++++++++++++++++++++
arch/arm/mach-rockchip/Kconfig | 6 +++
images/Makefile.rockchip | 7 ++++
11 files changed, 167 insertions(+)
create mode 100644 arch/arm/boards/radxa-rock3/.gitignore
create mode 100644 arch/arm/boards/radxa-rock3/Makefile
create mode 100644 arch/arm/boards/radxa-rock3/board.c
create mode 100644 arch/arm/boards/radxa-rock3/lowlevel.c
create mode 100644 arch/arm/dts/rk3568-rock-3a.dts
diff --git a/Documentation/boards/rockchip.rst b/Documentation/boards/rockchip.rst
index 041bb9fa64..d4f8a9c5a3 100644
--- a/Documentation/boards/rockchip.rst
+++ b/Documentation/boards/rockchip.rst
@@ -59,6 +59,7 @@ Supported Boards
- Rockchip RK3568 EVB
- Rockchip RK3568 Bananapi R2 Pro
- Pine64 Quartz64 Model A
+- Radxa ROCK3 Model A
The steps described in the following target the RK3568 and the RK3568 EVB but
generally apply to both SoCs and all boards.
diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
index d303999614..3ccde26f1b 100644
--- a/arch/arm/boards/Makefile
+++ b/arch/arm/boards/Makefile
@@ -192,3 +192,4 @@ obj-$(CONFIG_MACH_SKOV_ARM9CPU) += skov-arm9cpu/
obj-$(CONFIG_MACH_RK3568_EVB) += rockchip-rk3568-evb/
obj-$(CONFIG_MACH_RK3568_BPI_R2PRO) += rockchip-rk3568-bpi-r2pro/
obj-$(CONFIG_MACH_PINE64_QUARTZ64) += pine64-quartz64/
+obj-$(CONFIG_MACH_RADXA_ROCK3) += radxa-rock3/
diff --git a/arch/arm/boards/radxa-rock3/.gitignore b/arch/arm/boards/radxa-rock3/.gitignore
new file mode 100644
index 0000000000..f458f794b5
--- /dev/null
+++ b/arch/arm/boards/radxa-rock3/.gitignore
@@ -0,0 +1 @@
+sdram-init.bin
diff --git a/arch/arm/boards/radxa-rock3/Makefile b/arch/arm/boards/radxa-rock3/Makefile
new file mode 100644
index 0000000000..b37b6c870b
--- /dev/null
+++ b/arch/arm/boards/radxa-rock3/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+obj-y += board.o
+lwl-y += lowlevel.o
diff --git a/arch/arm/boards/radxa-rock3/board.c b/arch/arm/boards/radxa-rock3/board.c
new file mode 100644
index 0000000000..05a526b06e
--- /dev/null
+++ b/arch/arm/boards/radxa-rock3/board.c
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0-only
+#include <bootsource.h>
+#include <common.h>
+#include <init.h>
+
+struct rock3_model {
+ const char *name;
+ const char *shortname;
+};
+
+static int rock3_probe(struct device_d *dev)
+{
+ enum bootsource bootsource = bootsource_get();
+ int instance = bootsource_get_instance();
+ const struct rock3_model *model;
+
+ model = device_get_match_data(dev);
+
+ barebox_set_model(model->name);
+ barebox_set_hostname(model->shortname);
+
+ if (bootsource == BOOTSOURCE_MMC && instance == 1)
+ of_device_enable_path("/chosen/environment-sd");
+ else
+ of_device_enable_path("/chosen/environment-emmc");
+
+ return 0;
+}
+
+static const struct rock3_model rock3a = {
+ .name = "Radxa ROCK3 Model A",
+ .shortname = "rock3a",
+};
+
+static const struct of_device_id rock3_of_match[] = {
+ {
+ .compatible = "radxa,rock3a",
+ .data = &rock3a,
+ },
+ { /* sentinel */ },
+};
+
+static struct driver_d rock3_board_driver = {
+ .name = "board-rock3",
+ .probe = rock3_probe,
+ .of_compatible = rock3_of_match,
+};
+coredevice_platform_driver(rock3_board_driver);
diff --git a/arch/arm/boards/radxa-rock3/lowlevel.c b/arch/arm/boards/radxa-rock3/lowlevel.c
new file mode 100644
index 0000000000..00a68889cd
--- /dev/null
+++ b/arch/arm/boards/radxa-rock3/lowlevel.c
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0-only
+#include <common.h>
+#include <linux/sizes.h>
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+#include <mach/hardware.h>
+#include <mach/atf.h>
+#include <debug_ll.h>
+#include <mach/rockchip.h>
+
+extern char __dtb_rk3568_rock_3a_start[];
+
+static noinline void rk3568_start(void *fdt)
+{
+ /*
+ * Image execution starts at 0x0, but this is used for ATF and
+ * OP-TEE later, so move away from here.
+ */
+ if (current_el() == 3)
+ relocate_to_adr_full(RK3568_BAREBOX_LOAD_ADDRESS);
+ else
+ relocate_to_current_adr();
+
+ setup_c();
+
+ /*
+ * Enable vccio4 1.8V and vccio6 1.8V
+ * Needed for GMAC to work.
+ */
+ writel(RK_SETBITS(0x50), 0xfdc20140);
+
+ if (current_el() == 3) {
+ rk3568_lowlevel_init();
+ rk3568_atf_load_bl31(fdt);
+ /* not reached */
+ }
+
+ barebox_arm_entry(RK3568_DRAM_BOTTOM, 0x80000000 - RK3568_DRAM_BOTTOM, fdt);
+}
+
+ENTRY_FUNCTION(start_rock3a, r0, r1, r2)
+{
+ rk3568_start(__dtb_rk3568_rock_3a_start);
+}
diff --git a/arch/arm/configs/rockchip_v8_defconfig b/arch/arm/configs/rockchip_v8_defconfig
index 79d51234cc..1c7116e74a 100644
--- a/arch/arm/configs/rockchip_v8_defconfig
+++ b/arch/arm/configs/rockchip_v8_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARCH_ROCKCHIP=y
CONFIG_MACH_RK3568_EVB=y
CONFIG_MACH_RK3568_BPI_R2PRO=y
CONFIG_MACH_PINE64_QUARTZ64=y
+CONFIG_MACH_RADXA_ROCK3=y
CONFIG_BOARD_ARM_GENERIC_DT=y
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_ARM_PSCI_CLIENT=y
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index d67d10bde8..723bd2a123 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -105,6 +105,7 @@ lwl-$(CONFIG_MACH_PROTONIC_STM32MP1) += \
stm32mp151-prtt1c.dtb.o \
stm32mp151-prtt1s.dtb.o
lwl-$(CONFIG_MACH_RADXA_ROCK) += rk3188-radxarock.dtb.o
+lwl-$(CONFIG_MACH_RADXA_ROCK3) += rk3568-rock-3a.dtb.o
lwl-$(CONFIG_MACH_PHYTEC_SOM_RK3288) += rk3288-phycore-som.dtb.o
lwl-$(CONFIG_MACH_REALQ7) += imx6q-dmo-edmqmx6.dtb.o
lwl-$(CONFIG_MACH_RK3568_EVB) += rk3568-evb1-v10.dtb.o
diff --git a/arch/arm/dts/rk3568-rock-3a.dts b/arch/arm/dts/rk3568-rock-3a.dts
new file mode 100644
index 0000000000..44d4fc9686
--- /dev/null
+++ b/arch/arm/dts/rk3568-rock-3a.dts
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <arm64/rockchip/rk3568-rock-3a.dts>
+
+/ {
+ chosen: chosen {
+ environment-sd {
+ compatible = "barebox,environment";
+ device-path = &environment_sd;
+ status = "disabled";
+ };
+
+ environment-emmc {
+ compatible = "barebox,environment";
+ device-path = &environment_emmc;
+ status = "disabled";
+ };
+ };
+
+ memory@a00000 {
+ device_type = "memory";
+ reg = <0x0 0x00a00000 0x0 0x7f600000>;
+ };
+};
+
+&sdhci {
+ no-sd;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ environment_emmc: partition@408000 {
+ label = "barebox-environment";
+ reg = <0x0 0x408000 0x0 0x8000>;
+ };
+ };
+};
+
+&sdmmc0 {
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ environment_sd: partition@408000 {
+ label = "barebox-environment";
+ reg = <0x0 0x408000 0x0 0x8000>;
+ };
+ };
+};
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index ffd3aa8a4e..4b6dfd2c17 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -80,6 +80,12 @@ config MACH_PINE64_QUARTZ64
help
Say Y here if you are using a Pine64 Quartz64
+config MACH_RADXA_ROCK3
+ select ARCH_RK3568
+ bool "Radxa ROCK3"
+ help
+ Say Y here if you are using a Radxa ROCK3
+
comment "select board features:"
config ARCH_RK3399_OPTEE
diff --git a/images/Makefile.rockchip b/images/Makefile.rockchip
index cdc7772c2e..33c76caf79 100644
--- a/images/Makefile.rockchip
+++ b/images/Makefile.rockchip
@@ -20,6 +20,9 @@ image-$(CONFIG_MACH_RK3568_BPI_R2PRO) += barebox-rk3568-bpi-r2pro.img
pblb-$(CONFIG_MACH_PINE64_QUARTZ64) += start_quartz64a
image-$(CONFIG_MACH_PINE64_QUARTZ64) += barebox-quartz64a.img
+pblb-$(CONFIG_MACH_RADXA_ROCK3) += start_rock3a
+image-$(CONFIG_MACH_RADXA_ROCK3) += barebox-rock3a.img
+
quiet_cmd_rkimg_image = RK-IMG $@
cmd_rkimg_image = $(objtree)/scripts/rkimage -o $@ $(word 2,$^) $(word 1,$^)
@@ -34,3 +37,7 @@ $(obj)/barebox-rk3568-bpi-r2pro.img: $(obj)/start_rk3568_bpi_r2pro.pblb \
$(obj)/barebox-quartz64a.img: $(obj)/start_quartz64a.pblb \
$(board)/pine64-quartz64/sdram-init.bin
$(call if_changed,rkimg_image)
+
+$(obj)/barebox-rock3a.img: $(obj)/start_rock3a.pblb \
+ $(board)/radxa-rock3/sdram-init.bin
+ $(call if_changed,rkimg_image)
--
2.30.2
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http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 0/3] arm: rockchip: add support for the radxa rock3 board
2022-05-31 16:26 [PATCH 0/3] arm: rockchip: add support for the radxa rock3 board Michael Riesch
` (2 preceding siblings ...)
2022-05-31 16:26 ` [PATCH 3/3] arm: rockchip: add support for the radxa rock3 board Michael Riesch
@ 2022-06-08 7:19 ` Sascha Hauer
3 siblings, 0 replies; 5+ messages in thread
From: Sascha Hauer @ 2022-06-08 7:19 UTC (permalink / raw)
To: Michael Riesch; +Cc: barebox
On Tue, May 31, 2022 at 06:26:21PM +0200, Michael Riesch wrote:
> Hi all,
>
> This series aims to add support for the Radxa ROCK3 Model A single
> board computer featuring the Rockchip RK3568 SoC.
>
> The first two patches mock the dts sync from the Linux kernel and
> introduce the device tree for the board (will appear in Linux
> v5.19-rc1). These patches can be dropped of course and are added only
> for convenience.
devicetree-rebasing for v5.19-rc1 is out, I applied this series now.
Sascha
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2022-06-08 7:21 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-05-31 16:26 [PATCH 0/3] arm: rockchip: add support for the radxa rock3 board Michael Riesch
2022-05-31 16:26 ` [PATCH 1/3] HACK: add device trees for rk3568 Michael Riesch
2022-05-31 16:26 ` [PATCH 2/3] HACK: add device tree for radxa rock3 model a Michael Riesch
2022-05-31 16:26 ` [PATCH 3/3] arm: rockchip: add support for the radxa rock3 board Michael Riesch
2022-06-08 7:19 ` [PATCH 0/3] " Sascha Hauer
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