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From: Alexander Shiyan <eagle.alexander923@gmail.com>
To: barebox@lists.infradead.org
Cc: Alexander Shiyan <eagle.alexander923@gmail.com>
Subject: [RFC 4/8] ARM: OMAP: Move locally used definitions from emif4 header to am35xx_emif4
Date: Fri,  3 Jun 2022 14:25:36 +0300	[thread overview]
Message-ID: <20220603112540.51644-4-eagle.alexander923@gmail.com> (raw)
In-Reply-To: <20220603112540.51644-1-eagle.alexander923@gmail.com>

Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com>
---
 arch/arm/mach-omap/am35xx_emif4.c       | 53 ++++++++++++++++++++++++-
 arch/arm/mach-omap/include/mach/emif4.h | 52 ------------------------
 2 files changed, 52 insertions(+), 53 deletions(-)

diff --git a/arch/arm/mach-omap/am35xx_emif4.c b/arch/arm/mach-omap/am35xx_emif4.c
index 8780dfb539..bd4fbd21e3 100644
--- a/arch/arm/mach-omap/am35xx_emif4.c
+++ b/arch/arm/mach-omap/am35xx_emif4.c
@@ -15,7 +15,58 @@
 #include <mach/omap3-silicon.h>
 
 /*
- * do_pac200_emif4_init -
+ * AM35xx configuration values
+ */
+#define EMIF4_TIM1_T_RP		(0x3 << 25)
+#define EMIF4_TIM1_T_RCD	(0x3 << 21)
+#define EMIF4_TIM1_T_WR		(0x3 << 17)
+#define EMIF4_TIM1_T_RAS	(0x7 << 12)
+#define EMIF4_TIM1_T_RC		(0xa << 6)
+#define EMIF4_TIM1_T_RRD	(0x2 << 3)
+#define EMIF4_TIM1_T_WTR	(0x2)
+
+#define EMIF4_TIM2_T_XP		(0x2 << 28)
+#define EMIF4_TIM2_T_ODT	(0x0 << 25)
+#define EMIF4_TIM2_T_XSNR	(0x1c << 16)
+#define EMIF4_TIM2_T_XSRD	(0xc8 << 6)
+#define EMIF4_TIM2_T_RTP	(0x1 << 3)
+#define EMIF4_TIM2_T_CKE	(0x2)
+
+#define EMIF4_TIM3_T_RFC	(0x15 << 4)
+#define EMIF4_TIM3_T_RAS_MAX	(0xf)
+
+#define EMIF4_PWR_IDLE_MODE	(0x2 << 30)
+#define EMIF4_PWR_DPD_DIS	(0x0 << 10)
+#define EMIF4_PWR_DPD_EN	(0x1 << 10)
+#define EMIF4_PWR_LP_MODE	(0x0 << 8)
+#define EMIF4_PWR_PM_TIM	(0x0)
+
+#define EMIF4_INITREF_DIS	(0x0 << 31)
+#define EMIF4_REFRESH_RATE	(0x257)
+
+#define EMIF4_CFG_SDRAM_TYP	(0x2 << 29)
+#define EMIF4_CFG_IBANK_POS	(0x0 << 27)
+#define EMIF4_CFG_DDR_TERM	(0x3 << 24)
+#define EMIF4_CFG_DDR2_DDQS	(0x1 << 23)
+#define EMIF4_CFG_DDR_DIS_DLL	(0x0 << 20)
+#define EMIF4_CFG_SDR_DRV	(0x0 << 18)
+#define EMIF4_CFG_NARROW_MD	(0x0 << 14)
+#define EMIF4_CFG_CL		(0x5 << 10)
+#define EMIF4_CFG_ROWSIZE	(0x0 << 7)
+#define EMIF4_CFG_IBANK		(0x3 << 4)
+#define EMIF4_CFG_EBANK		(0x0 << 3)
+#define EMIF4_CFG_PGSIZE	(0x2)
+
+/*
+ * EMIF4 PHY Control 1 register configuration
+ */
+#define EMIF4_DDR1_EXT_STRB_EN	(0x1 << 7)
+#define EMIF4_DDR1_EXT_STRB_DIS	(0x0 << 7)
+#define EMIF4_DDR1_PWRDN_DIS	(0x0 << 6)
+#define EMIF4_DDR1_PWRDN_EN	(0x1 << 6)
+#define EMIF4_DDR1_READ_LAT	(0x6 << 0)
+
+/*
  *  - Init the emif4 module for DDR access
  *  - Early init routines, called from flash or SRAM.
  */
diff --git a/arch/arm/mach-omap/include/mach/emif4.h b/arch/arm/mach-omap/include/mach/emif4.h
index 06dabc5939..23d5c18fcf 100644
--- a/arch/arm/mach-omap/include/mach/emif4.h
+++ b/arch/arm/mach-omap/include/mach/emif4.h
@@ -45,58 +45,6 @@
 #define EMIF4_DDR_PHY_CTRL_2					0xec
 #define EMIF4_IODFT_TLGC					0x60
 
-/*
- * Configuration values
- */
-#define EMIF4_TIM1_T_RP		(0x3 << 25)
-#define EMIF4_TIM1_T_RCD	(0x3 << 21)
-#define EMIF4_TIM1_T_WR		(0x3 << 17)
-#define EMIF4_TIM1_T_RAS	(0x7 << 12) /* 8->7 */
-#define EMIF4_TIM1_T_RC		(0xA << 6)
-#define EMIF4_TIM1_T_RRD	(0x2 << 3)
-#define EMIF4_TIM1_T_WTR	(0x2)
-
-#define EMIF4_TIM2_T_XP		(0x2 << 28)
-#define EMIF4_TIM2_T_ODT	(0x0 << 25) /* 2? */
-#define EMIF4_TIM2_T_XSNR	(0x1C << 16)
-#define EMIF4_TIM2_T_XSRD	(0xC8 << 6)
-#define EMIF4_TIM2_T_RTP	(0x1 << 3)
-#define EMIF4_TIM2_T_CKE	(0x2)
-
-#define EMIF4_TIM3_T_RFC	(0x15 << 4) /* 25->15 */
-#define EMIF4_TIM3_T_RAS_MAX	(0xf)	    /* 7->f */
-
-#define EMIF4_PWR_IDLE_MODE	(0x2 << 30)
-#define EMIF4_PWR_DPD_DIS	(0x0 << 10)
-#define EMIF4_PWR_DPD_EN	(0x1 << 10)
-#define EMIF4_PWR_LP_MODE	(0x0 << 8)
-#define EMIF4_PWR_PM_TIM	(0x0)
-
-#define EMIF4_INITREF_DIS	(0x0 << 31)
-#define EMIF4_REFRESH_RATE	(0x257) /* 50f->257 */
-
-#define EMIF4_CFG_SDRAM_TYP	(0x2 << 29)
-#define EMIF4_CFG_IBANK_POS	(0x0 << 27)
-#define EMIF4_CFG_DDR_TERM	(0x3 << 24) /* --> 0x3 */
-#define EMIF4_CFG_DDR2_DDQS	(0x1 << 23)
-#define EMIF4_CFG_DDR_DIS_DLL	(0x0 << 20)
-#define EMIF4_CFG_SDR_DRV	(0x0 << 18)
-#define EMIF4_CFG_NARROW_MD	(0x0 << 14)
-#define EMIF4_CFG_CL		(0x5 << 10)
-#define EMIF4_CFG_ROWSIZE	(0x0 << 7) /* --> 0x4: a0..a12 */
-#define EMIF4_CFG_IBANK		(0x3 << 4)
-#define EMIF4_CFG_EBANK		(0x0 << 3)
-#define EMIF4_CFG_PGSIZE	(0x2)      /* 10 columns */
-
-/*
- * EMIF4 PHY Control 1 register configuration
- */
-#define EMIF4_DDR1_EXT_STRB_EN	(0x1 << 7)
-#define EMIF4_DDR1_EXT_STRB_DIS	(0x0 << 7)
-#define EMIF4_DDR1_PWRDN_DIS	(0x0 << 6)
-#define EMIF4_DDR1_PWRDN_EN	(0x1 << 6)
-#define EMIF4_DDR1_READ_LAT	(0x6 << 0)
-
 void am35xx_emif4_init(void);
 
 #endif /* endif _EMIF_H_ */
-- 
2.32.0


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  parent reply	other threads:[~2022-06-03 11:27 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-03 11:25 [RFC 1/8] ARM: OMAP: Rearranging EMIF4 definitions Alexander Shiyan
2022-06-03 11:25 ` [RFC 2/8] ARM: OMAP: Move EMIF4 definitions to appropriate header Alexander Shiyan
2022-06-03 11:25 ` [RFC 3/8] ARM: OMAP: Adopt am35xx_emif4_init() to use fixed offset definitions Alexander Shiyan
2022-06-03 11:25 ` Alexander Shiyan [this message]
2022-06-03 11:25 ` [RFC 5/8] ARM: OMAP: emif: Abstract am35xx_emif4 from any CPU-specific includes Alexander Shiyan
2022-06-03 11:25 ` [RFC 6/8] ARM: OMAP: emif: Rename am35xx_emif4 unit Alexander Shiyan
2022-06-03 11:25 ` [RFC 7/8] ARM: OMAP: Use EMIF4 registers for get SDRAM size Alexander Shiyan
2022-06-03 11:25 ` [RFC 8/8] ARM: OMAP: Move am33xx_sdram_size() into EMIF module and make it generic Alexander Shiyan
2022-06-07  7:38 ` [RFC 1/8] ARM: OMAP: Rearranging EMIF4 definitions Sascha Hauer
2022-06-07  7:47   ` Alexander Shiyan

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