* [PATCH v2 01/11] pwm: atmel: Fix build and update
2022-06-28 20:38 [PATCH 0/11] ARM: at91: Add pbl support to skov-arm9cpu Sam Ravnborg
@ 2022-06-28 20:38 ` Sam Ravnborg
2022-06-28 20:38 ` [PATCH v2 02/11] ARM: at91: Make sdramc.h useable in multi image builds Sam Ravnborg
` (10 subsequent siblings)
11 siblings, 0 replies; 21+ messages in thread
From: Sam Ravnborg @ 2022-06-28 20:38 UTC (permalink / raw)
To: barebox, Ahmad Fatoum; +Cc: Sam Ravnborg
The pwm-atmel driver was not updated to use the atomic api and did not
build.
Update the driver from linux kernel 5.16-rc7 and adapt to barebox
to get the latest fixes including the conversion to atomic api.
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
---
drivers/pwm/pwm-atmel.c | 383 ++++++++++++++++++++++++++++++----------
1 file changed, 285 insertions(+), 98 deletions(-)
diff --git a/drivers/pwm/pwm-atmel.c b/drivers/pwm/pwm-atmel.c
index 648f75fb7..9ec81e18b 100644
--- a/drivers/pwm/pwm-atmel.c
+++ b/drivers/pwm/pwm-atmel.c
@@ -55,15 +55,7 @@
#define PWMV2_CPRD 0x0C
#define PWMV2_CPRDUPD 0x10
-/*
- * Max value for duty and period
- *
- * Although the duty and period register is 32 bit,
- * however only the LSB 16 bits are significant.
- */
-#define PWM_MAX_DTY 0xFFFF
-#define PWM_MAX_PRD 0xFFFF
-#define PRD_MAX_PRES 10
+#define PWM_MAX_PRES 10
struct atmel_pwm_registers {
u8 period;
@@ -72,30 +64,53 @@ struct atmel_pwm_registers {
u8 duty_upd;
};
-struct atmel_pwm;
+struct atmel_pwm_config {
+ u32 period_bits;
+};
-struct atmel_pwm_chip {
- struct pwm_chip chip;
- struct atmel_pwm *atmel;
+struct atmel_pwm_data {
+ struct atmel_pwm_registers regs;
+ struct atmel_pwm_config cfg;
};
-struct atmel_pwm {
- struct atmel_pwm_chip atmel_pwm_chip[PWM_CHANNELS];
- const struct atmel_pwm_registers *regs;
+struct atmel_pwm_chip {
+ struct pwm_chip chips[PWM_CHANNELS];
struct clk *clk;
void __iomem *base;
struct device_d *dev;
+ const struct atmel_pwm_data *data;
+
+ /*
+ * The hardware supports a mechanism to update a channel's duty cycle at
+ * the end of the currently running period. When such an update is
+ * pending we delay disabling the PWM until the new configuration is
+ * active because otherwise pmw_config(duty_cycle=0); pwm_disable();
+ * might not result in an inactive output.
+ * This bitmask tracks for which channels an update is pending in
+ * hardware.
+ */
+ u32 update_pending;
+
+ /* Protects .update_pending */
+ spinlock_t lock;
};
static inline struct atmel_pwm_chip *to_atmel_pwm_chip(struct pwm_chip *chip)
{
- return container_of(chip, struct atmel_pwm_chip, chip);
+ struct pwm_chip (*chips)[4] = (void *)&chip[-chip->id];
+ return container_of(chips, struct atmel_pwm_chip, chips);
+}
+
+static inline u32 atmel_pwm_readl(struct atmel_pwm_chip *chip,
+ unsigned long offset)
+{
+ return readl_relaxed(chip->base + offset);
}
static inline void atmel_pwm_writel(struct atmel_pwm_chip *chip,
unsigned long offset, unsigned long val)
{
- writel(val, chip->atmel->base + offset);
+ writel_relaxed(val, chip->base + offset);
}
static inline u32 atmel_pwm_ch_readl(struct atmel_pwm_chip *chip,
@@ -103,7 +118,7 @@ static inline u32 atmel_pwm_ch_readl(struct atmel_pwm_chip *chip,
{
unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
- return readl(chip->atmel->base + base + offset);
+ return atmel_pwm_readl(chip, base + offset);
}
static inline void atmel_pwm_ch_writel(struct atmel_pwm_chip *chip,
@@ -112,24 +127,95 @@ static inline void atmel_pwm_ch_writel(struct atmel_pwm_chip *chip,
{
unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
- writel(val, chip->atmel->base + base + offset);
+ atmel_pwm_writel(chip, base + offset, val);
+}
+
+static void atmel_pwm_update_pending(struct atmel_pwm_chip *chip)
+{
+ /*
+ * Each channel that has its bit in ISR set started a new period since
+ * ISR was cleared and so there is no more update pending. Note that
+ * reading ISR clears it, so this needs to handle all channels to not
+ * loose information.
+ */
+ u32 isr = atmel_pwm_readl(chip, PWM_ISR);
+
+ chip->update_pending &= ~isr;
+}
+
+static void atmel_pwm_set_pending(struct atmel_pwm_chip *chip, unsigned int ch)
+{
+ spin_lock(&chip->lock);
+
+ /*
+ * Clear pending flags in hardware because otherwise there might still
+ * be a stale flag in ISR.
+ */
+ atmel_pwm_update_pending(chip);
+
+ chip->update_pending |= (1 << ch);
+
+ spin_unlock(&chip->lock);
+}
+
+static int atmel_pwm_test_pending(struct atmel_pwm_chip *chip, unsigned int ch)
+{
+ int ret = 0;
+
+ spin_lock(&chip->lock);
+
+ if (chip->update_pending & (1 << ch)) {
+ atmel_pwm_update_pending(chip);
+
+ if (chip->update_pending & (1 << ch))
+ ret = 1;
+ }
+
+ spin_unlock(&chip->lock);
+
+ return ret;
+}
+
+static int atmel_pwm_wait_nonpending(struct atmel_pwm_chip *chip, unsigned int ch)
+{
+ unsigned long timeout = get_time_ns() + 2 * HZ;
+ int ret;
+
+ while ((ret = atmel_pwm_test_pending(chip, ch)) &&
+ !is_timeout(get_time_ns(), timeout))
+ udelay(100);
+
+ return ret ? -ETIMEDOUT : 0;
}
-static int atmel_pwm_calculate_cprd_and_pres(struct atmel_pwm_chip *atmel_pwm,
- int period,
+static int atmel_pwm_calculate_cprd_and_pres(struct pwm_chip *chip,
+ unsigned long clkrate,
+ const struct pwm_state *state,
unsigned long *cprd, u32 *pres)
{
- unsigned long long cycles = period;
+ struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
+ unsigned long long cycles = state->period_ns;
+ int shift;
+
/* Calculate the period cycles and prescale value */
- cycles *= clk_get_rate(atmel_pwm->atmel->clk);
+ cycles *= clkrate;
do_div(cycles, NSEC_PER_SEC);
- for (*pres = 0; cycles > PWM_MAX_PRD; cycles >>= 1)
- (*pres)++;
+ /*
+ * The register for the period length is cfg.period_bits bits wide.
+ * So for each bit the number of clock cycles is wider divide the input
+ * clock frequency by two using pres and shift cprd accordingly.
+ */
+ shift = fls(cycles) - atmel_pwm->data->cfg.period_bits;
- if (*pres > PRD_MAX_PRES) {
- dev_err(atmel_pwm->atmel->dev, "pres exceeds the maximum value\n");
+ if (shift > PWM_MAX_PRES) {
+ dev_err(atmel_pwm->dev, "pres exceeds the maximum value\n");
return -EINVAL;
+ } else if (shift > 0) {
+ *pres = shift;
+ cycles >>= *pres;
+ } else {
+ *pres = 0;
}
*cprd = cycles;
@@ -137,137 +223,238 @@ static int atmel_pwm_calculate_cprd_and_pres(struct atmel_pwm_chip *atmel_pwm,
return 0;
}
-static void atmel_pwm_calculate_cdty(int duty, int period,
- unsigned long cprd, unsigned long *cdty)
+static void atmel_pwm_calculate_cdty(const struct pwm_state *state,
+ unsigned long clkrate, unsigned long cprd,
+ u32 pres, unsigned long *cdty)
{
- unsigned long long cycles = duty;
+ unsigned long long cycles = state->duty_ns;
- cycles *= cprd;
- do_div(cycles, period);
+ cycles *= clkrate;
+ do_div(cycles, NSEC_PER_SEC);
+ cycles >>= pres;
*cdty = cprd - cycles;
}
-static void atmel_pwm_set_cprd_cdty(struct atmel_pwm_chip *atmel_pwm, int ch,
+static void atmel_pwm_update_cdty(struct pwm_chip *chip, unsigned long cdty)
+{
+ struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
+ u32 val;
+
+ if (atmel_pwm->data->regs.duty_upd ==
+ atmel_pwm->data->regs.period_upd) {
+ val = atmel_pwm_ch_readl(atmel_pwm, chip->id, PWM_CMR);
+ val &= ~PWM_CMR_UPD_CDTY;
+ atmel_pwm_ch_writel(atmel_pwm, chip->id, PWM_CMR, val);
+ }
+
+ atmel_pwm_ch_writel(atmel_pwm, chip->id,
+ atmel_pwm->data->regs.duty_upd, cdty);
+ atmel_pwm_set_pending(atmel_pwm, chip->id);
+}
+
+static void atmel_pwm_set_cprd_cdty(struct pwm_chip *chip,
unsigned long cprd, unsigned long cdty)
{
- const struct atmel_pwm_registers *regs = atmel_pwm->atmel->regs;
+ struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
- atmel_pwm_ch_writel(atmel_pwm, ch, regs->duty, cdty);
- atmel_pwm_ch_writel(atmel_pwm, ch, regs->period, cprd);
+ atmel_pwm_ch_writel(atmel_pwm, chip->id,
+ atmel_pwm->data->regs.duty, cdty);
+ atmel_pwm_ch_writel(atmel_pwm, chip->id,
+ atmel_pwm->data->regs.period, cprd);
}
-static int atmel_pwm_config(struct pwm_chip *chip, int duty_ns, int period_ns)
+static void atmel_pwm_disable(struct pwm_chip *chip, bool disable_clk)
{
struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
- unsigned long cprd, cdty;
- u32 pres, val;
- int ret;
- int ch;
+ unsigned long timeout;
- ch = atmel_pwm->chip.id;
- ret = atmel_pwm_calculate_cprd_and_pres(atmel_pwm, period_ns, &cprd, &pres);
- if (ret)
- return ret;
+ atmel_pwm_wait_nonpending(atmel_pwm, chip->id);
- atmel_pwm_calculate_cdty(duty_ns, period_ns, cprd, &cdty);
+ atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << chip->id);
- /* It is necessary to preserve CPOL, inside CMR */
- val = atmel_pwm_ch_readl(atmel_pwm, ch, PWM_CMR);
- val = (val & ~PWM_CMR_CPRE_MSK) | (pres & PWM_CMR_CPRE_MSK);
- /* Assuming normal polarity */
- val &= ~PWM_CMR_CPOL;
+ /*
+ * Wait for the PWM channel disable operation to be effective before
+ * stopping the clock.
+ */
+ timeout = get_time_ns() + 2 * HZ;
- atmel_pwm_ch_writel(atmel_pwm, ch, PWM_CMR, val);
- atmel_pwm_set_cprd_cdty(atmel_pwm, ch, cprd, cdty);
+ while ((atmel_pwm_readl(atmel_pwm, PWM_SR) & (1 << chip->id)) &&
+ !is_timeout(get_time_ns(), timeout))
+ udelay(100);
- return 0;
+ if (disable_clk)
+ clk_disable(atmel_pwm->clk);
}
-static int atmel_pwm_enable(struct pwm_chip *chip)
+static int atmel_pwm_apply(struct pwm_chip *chip, const struct pwm_state *state)
{
struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
+ struct pwm_state cstate;
+ unsigned long cprd, cdty;
+ u32 pres, val;
+ int ret;
- atmel_pwm_writel(atmel_pwm, PWM_ENA, 1 << atmel_pwm->chip.id);
- return 0;
-}
+ cstate = chip->state;
-static void atmel_pwm_disable(struct pwm_chip *chip)
-{
- struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
+ if (state->p_enable) {
+ unsigned long clkrate = clk_get_rate(atmel_pwm->clk);
+
+ if (cstate.p_enable &&
+ cstate.polarity == state->polarity &&
+ cstate.period_ns == state->period_ns) {
+ u32 cmr = atmel_pwm_ch_readl(atmel_pwm, chip->id, PWM_CMR);
+
+ cprd = atmel_pwm_ch_readl(atmel_pwm, chip->id,
+ atmel_pwm->data->regs.period);
+ pres = cmr & PWM_CMR_CPRE_MSK;
+
+ atmel_pwm_calculate_cdty(state, clkrate, cprd, pres, &cdty);
+ atmel_pwm_update_cdty(chip, cdty);
+ return 0;
+ }
+
+ ret = atmel_pwm_calculate_cprd_and_pres(chip, clkrate, state, &cprd,
+ &pres);
+ if (ret) {
+ dev_err(atmel_pwm->dev,
+ "failed to calculate cprd and prescaler\n");
+ return ret;
+ }
+
+ atmel_pwm_calculate_cdty(state, clkrate, cprd, pres, &cdty);
- atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << atmel_pwm->chip.id);
+ if (cstate.p_enable) {
+ atmel_pwm_disable(chip, false);
+ } else {
+ ret = clk_enable(atmel_pwm->clk);
+ if (ret) {
+ dev_err(atmel_pwm->dev, "failed to enable clock\n");
+ return ret;
+ }
+ }
+
+ /* It is necessary to preserve CPOL, inside CMR */
+ val = atmel_pwm_ch_readl(atmel_pwm, chip->id, PWM_CMR);
+ val = (val & ~PWM_CMR_CPRE_MSK) | (pres & PWM_CMR_CPRE_MSK);
+ if (state->polarity == PWM_POLARITY_NORMAL)
+ val &= ~PWM_CMR_CPOL;
+ else
+ val |= PWM_CMR_CPOL;
+ atmel_pwm_ch_writel(atmel_pwm, chip->id, PWM_CMR, val);
+ atmel_pwm_set_cprd_cdty(chip, cprd, cdty);
+ atmel_pwm_writel(atmel_pwm, PWM_ENA, 1 << chip->id);
+ } else if (cstate.p_enable) {
+ atmel_pwm_disable(chip, true);
+ }
+
+ return 0;
}
-static struct pwm_ops atmel_pwm_ops = {
- .config = atmel_pwm_config,
- .enable = atmel_pwm_enable,
- .disable = atmel_pwm_disable,
+static const struct pwm_ops atmel_pwm_ops = {
+ .apply = atmel_pwm_apply,
};
-static const struct atmel_pwm_registers atmel_pwm_regs_v1 = {
- .period = PWMV1_CPRD,
- .period_upd = PWMV1_CUPD,
- .duty = PWMV1_CDTY,
- .duty_upd = PWMV1_CUPD,
+static const struct atmel_pwm_data atmel_sam9rl_pwm_data = {
+ .regs = {
+ .period = PWMV1_CPRD,
+ .period_upd = PWMV1_CUPD,
+ .duty = PWMV1_CDTY,
+ .duty_upd = PWMV1_CUPD,
+ },
+ .cfg = {
+ /* 16 bits to keep period and duty. */
+ .period_bits = 16,
+ },
+};
+
+static const struct atmel_pwm_data atmel_sama5_pwm_data = {
+ .regs = {
+ .period = PWMV2_CPRD,
+ .period_upd = PWMV2_CPRDUPD,
+ .duty = PWMV2_CDTY,
+ .duty_upd = PWMV2_CDTYUPD,
+ },
+ .cfg = {
+ /* 16 bits to keep period and duty. */
+ .period_bits = 16,
+ },
};
-static const struct atmel_pwm_registers atmel_pwm_regs_v2 = {
- .period = PWMV2_CPRD,
- .period_upd = PWMV2_CPRDUPD,
- .duty = PWMV2_CDTY,
- .duty_upd = PWMV2_CDTYUPD,
+static const struct atmel_pwm_data mchp_sam9x60_pwm_data = {
+ .regs = {
+ .period = PWMV1_CPRD,
+ .period_upd = PWMV1_CUPD,
+ .duty = PWMV1_CDTY,
+ .duty_upd = PWMV1_CUPD,
+ },
+ .cfg = {
+ /* 32 bits to keep period and duty. */
+ .period_bits = 32,
+ },
};
static const struct of_device_id atmel_pwm_dt_ids[] = {
{
.compatible = "atmel,at91sam9rl-pwm",
- .data = &atmel_pwm_regs_v1,
+ .data = &atmel_sam9rl_pwm_data,
}, {
.compatible = "atmel,sama5d3-pwm",
- .data = &atmel_pwm_regs_v2,
+ .data = &atmel_sama5_pwm_data,
}, {
.compatible = "atmel,sama5d2-pwm",
- .data = &atmel_pwm_regs_v2,
+ .data = &atmel_sama5_pwm_data,
+ }, {
+ .compatible = "microchip,sam9x60-pwm",
+ .data = &mchp_sam9x60_pwm_data,
}, {
/* sentinel */
},
};
+static int id = -1;
+
static int atmel_pwm_probe(struct device_d *dev)
{
- const struct atmel_pwm_registers *regs;
- struct atmel_pwm *atmel_pwm;
- struct resource *res;
+ const struct atmel_pwm_data *data;
+ struct atmel_pwm_chip *atmel_pwm;
+ struct resource *iores;
+ const char *alias;
int ret;
int i;
- ret = dev_get_drvdata(dev, (const void **)®s);
+ ret = dev_get_drvdata(dev, (const void **)&data);
if (ret)
return ret;
atmel_pwm = xzalloc(sizeof(*atmel_pwm));
- atmel_pwm->regs = regs;
+ atmel_pwm->data = data;
atmel_pwm->dev = dev;
atmel_pwm->clk = clk_get(dev, "pwm_clk");
if (IS_ERR(atmel_pwm->clk))
return PTR_ERR(atmel_pwm->clk);
- res = dev_request_mem_resource(dev, 0);
- if (IS_ERR(res))
- return PTR_ERR(res);
+ iores = dev_request_mem_resource(dev, 0);
+ if (IS_ERR(iores))
+ return PTR_ERR(iores);
- atmel_pwm->base = IOMEM(res->start);
+ atmel_pwm->base = IOMEM(iores->start);
+ alias = of_alias_get(dev->device_node);
+ if (!alias)
+ id++;
for (i = 0; i < PWM_CHANNELS; i++) {
- struct atmel_pwm_chip *chip = &atmel_pwm->atmel_pwm_chip[i];
- chip->chip.ops = &atmel_pwm_ops;
- chip->chip.devname = basprintf("pwm%d", i);
- chip->chip.id = i;
- chip->atmel = atmel_pwm;
-
- ret = pwmchip_add(&chip->chip, dev);
- if (ret < 0) {
- dev_err(dev, "failed to add pwm chip[%d] %d\n", i, ret);
+ struct pwm_chip *chip = &atmel_pwm->chips[i];
+
+ if (alias)
+ chip->devname = basprintf("%sch%u", alias, i + 1);
+ else
+ chip->devname = basprintf("pwm%uch%u", id, i + 1);
+
+ chip->ops = &atmel_pwm_ops;
+ chip->id = i;
+ ret = pwmchip_add(chip, dev);
+ if (ret) {
+ dev_err(dev, "failed to add pwm chip %d\n", ret);
return ret;
}
}
--
2.34.1
^ permalink raw reply [flat|nested] 21+ messages in thread* [PATCH v2 02/11] ARM: at91: Make sdramc.h useable in multi image builds
2022-06-28 20:38 [PATCH 0/11] ARM: at91: Add pbl support to skov-arm9cpu Sam Ravnborg
2022-06-28 20:38 ` [PATCH v2 01/11] pwm: atmel: Fix build and update Sam Ravnborg
@ 2022-06-28 20:38 ` Sam Ravnborg
2022-06-29 6:50 ` Ahmad Fatoum
2022-06-28 20:38 ` [PATCH v2 03/11] ARM: at91: Add initialize function to sdramc Sam Ravnborg
` (9 subsequent siblings)
11 siblings, 1 reply; 21+ messages in thread
From: Sam Ravnborg @ 2022-06-28 20:38 UTC (permalink / raw)
To: barebox, Ahmad Fatoum; +Cc: Sam Ravnborg
There is no need to ifdef out all the static inlines as the headers
no longer conflicts. Drop the ifdefs so we can now use the header
in multi image builds.
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
---
.../mach-at91/include/mach/at91sam9_sdramc.h | 45 ++-----------------
1 file changed, 4 insertions(+), 41 deletions(-)
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
index 80effe214..3cda10165 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
@@ -81,6 +81,10 @@
#ifndef __ASSEMBLY__
#include <io.h>
+#include <mach/at91sam9260.h>
+#include <mach/at91sam9261.h>
+#include <mach/at91sam9263.h>
+
static inline u32 at91_get_sdram_size(void *base)
{
u32 val;
@@ -107,14 +111,11 @@ static inline u32 at91_get_sdram_size(void *base)
return size;
}
-
static inline bool at91_is_low_power_sdram(void *base)
{
return readl(base + AT91_SDRAMC_MDR) & AT91_SDRAMC_MD_LOW_POWER_SDRAM;
}
-#ifdef CONFIG_SOC_AT91SAM9260
-#include <mach/at91sam9260.h>
static inline u32 at91sam9260_get_sdram_size(void)
{
return at91_get_sdram_size(IOMEM(AT91SAM9260_BASE_SDRAMC));
@@ -124,20 +125,7 @@ static inline bool at91sam9260_is_low_power_sdram(void)
{
return at91_is_low_power_sdram(IOMEM(AT91SAM9260_BASE_SDRAMC));
}
-#else
-static inline u32 at91sam9260_get_sdram_size(void)
-{
- return 0;
-}
-
-static inline bool at91sam9260_is_low_power_sdram(void)
-{
- return false;
-}
-#endif
-#ifdef CONFIG_SOC_AT91SAM9261
-#include <mach/at91sam9261.h>
static inline u32 at91sam9261_get_sdram_size(void)
{
return at91_get_sdram_size(IOMEM(AT91SAM9261_BASE_SDRAMC));
@@ -147,20 +135,7 @@ static inline bool at91sam9261_is_low_power_sdram(void)
{
return at91_is_low_power_sdram(IOMEM(AT91SAM9261_BASE_SDRAMC));
}
-#else
-static inline u32 at91sam9261_get_sdram_size(void)
-{
- return 0;
-}
-
-static inline bool at91sam9261_is_low_power_sdram(void)
-{
- return false;
-}
-#endif
-#ifdef CONFIG_SOC_AT91SAM9263
-#include <mach/at91sam9263.h>
static inline u32 at91sam9263_get_sdram_size(int bank)
{
switch (bank) {
@@ -184,18 +159,6 @@ static inline bool at91sam9263_is_low_power_sdram(int bank)
return false;
}
}
-#else
-static inline u32 at91sam9263_get_sdram_size(int bank)
-{
- return 0;
-}
-
-static inline bool at91sam9263_is_low_power_sdram(void)
-{
- return false;
-}
-#endif
#endif
-
#endif
--
2.34.1
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [PATCH v2 02/11] ARM: at91: Make sdramc.h useable in multi image builds
2022-06-28 20:38 ` [PATCH v2 02/11] ARM: at91: Make sdramc.h useable in multi image builds Sam Ravnborg
@ 2022-06-29 6:50 ` Ahmad Fatoum
0 siblings, 0 replies; 21+ messages in thread
From: Ahmad Fatoum @ 2022-06-29 6:50 UTC (permalink / raw)
To: Sam Ravnborg, barebox
On 28.06.22 22:38, Sam Ravnborg wrote:
> There is no need to ifdef out all the static inlines as the headers
> no longer conflicts. Drop the ifdefs so we can now use the header
> in multi image builds.
>
> Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> ---
> .../mach-at91/include/mach/at91sam9_sdramc.h | 45 ++-----------------
> 1 file changed, 4 insertions(+), 41 deletions(-)
>
> diff --git a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
> index 80effe214..3cda10165 100644
> --- a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
> +++ b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
> @@ -81,6 +81,10 @@
>
> #ifndef __ASSEMBLY__
> #include <io.h>
> +#include <mach/at91sam9260.h>
> +#include <mach/at91sam9261.h>
> +#include <mach/at91sam9263.h>
> +
> static inline u32 at91_get_sdram_size(void *base)
> {
> u32 val;
> @@ -107,14 +111,11 @@ static inline u32 at91_get_sdram_size(void *base)
> return size;
> }
>
> -
> static inline bool at91_is_low_power_sdram(void *base)
> {
> return readl(base + AT91_SDRAMC_MDR) & AT91_SDRAMC_MD_LOW_POWER_SDRAM;
> }
>
> -#ifdef CONFIG_SOC_AT91SAM9260
> -#include <mach/at91sam9260.h>
> static inline u32 at91sam9260_get_sdram_size(void)
> {
> return at91_get_sdram_size(IOMEM(AT91SAM9260_BASE_SDRAMC));
> @@ -124,20 +125,7 @@ static inline bool at91sam9260_is_low_power_sdram(void)
> {
> return at91_is_low_power_sdram(IOMEM(AT91SAM9260_BASE_SDRAMC));
> }
> -#else
> -static inline u32 at91sam9260_get_sdram_size(void)
> -{
> - return 0;
> -}
> -
> -static inline bool at91sam9260_is_low_power_sdram(void)
> -{
> - return false;
> -}
> -#endif
>
> -#ifdef CONFIG_SOC_AT91SAM9261
> -#include <mach/at91sam9261.h>
> static inline u32 at91sam9261_get_sdram_size(void)
> {
> return at91_get_sdram_size(IOMEM(AT91SAM9261_BASE_SDRAMC));
> @@ -147,20 +135,7 @@ static inline bool at91sam9261_is_low_power_sdram(void)
> {
> return at91_is_low_power_sdram(IOMEM(AT91SAM9261_BASE_SDRAMC));
> }
> -#else
> -static inline u32 at91sam9261_get_sdram_size(void)
> -{
> - return 0;
> -}
> -
> -static inline bool at91sam9261_is_low_power_sdram(void)
> -{
> - return false;
> -}
> -#endif
>
> -#ifdef CONFIG_SOC_AT91SAM9263
> -#include <mach/at91sam9263.h>
> static inline u32 at91sam9263_get_sdram_size(int bank)
> {
> switch (bank) {
> @@ -184,18 +159,6 @@ static inline bool at91sam9263_is_low_power_sdram(int bank)
> return false;
> }
> }
> -#else
> -static inline u32 at91sam9263_get_sdram_size(int bank)
> -{
> - return 0;
> -}
> -
> -static inline bool at91sam9263_is_low_power_sdram(void)
> -{
> - return false;
> -}
> -#endif
>
> #endif
> -
> #endif
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v2 03/11] ARM: at91: Add initialize function to sdramc
2022-06-28 20:38 [PATCH 0/11] ARM: at91: Add pbl support to skov-arm9cpu Sam Ravnborg
2022-06-28 20:38 ` [PATCH v2 01/11] pwm: atmel: Fix build and update Sam Ravnborg
2022-06-28 20:38 ` [PATCH v2 02/11] ARM: at91: Make sdramc.h useable in multi image builds Sam Ravnborg
@ 2022-06-28 20:38 ` Sam Ravnborg
2022-06-29 6:50 ` Ahmad Fatoum
2022-06-28 20:38 ` [PATCH v2 04/11] ARM: at91: Provide at91_mux_pio_pin for use in lowlevel Sam Ravnborg
` (8 subsequent siblings)
11 siblings, 1 reply; 21+ messages in thread
From: Sam Ravnborg @ 2022-06-28 20:38 UTC (permalink / raw)
To: barebox, Ahmad Fatoum; +Cc: Sam Ravnborg
Port the sdramc initialize function from at91bootstrap.
It is needed from lowlevel code and is a replacement for the
sdramc init code in at91sam926x_board_init.h
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
---
arch/arm/mach-at91/Makefile | 2 +-
arch/arm/mach-at91/at91sam9_sdramc_ll.c | 71 +++++++++++++++++++
.../mach-at91/include/mach/at91sam9_sdramc.h | 12 ++++
3 files changed, 84 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/mach-at91/at91sam9_sdramc_ll.c
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index bfdc89f68..12e64291b 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-y += setup.o aic.o
-lwl-y += at91_pmc_ll.o ddramc_ll.o matrix.o
+lwl-y += at91_pmc_ll.o ddramc_ll.o at91sam9_sdramc_ll.o matrix.o
lwl-$(CONFIG_CLOCKSOURCE_ATMEL_PIT) += early_udelay.o
ifeq ($(CONFIG_COMMON_CLK_OF_PROVIDER),)
diff --git a/arch/arm/mach-at91/at91sam9_sdramc_ll.c b/arch/arm/mach-at91/at91sam9_sdramc_ll.c
new file mode 100644
index 000000000..805cfbbe4
--- /dev/null
+++ b/arch/arm/mach-at91/at91sam9_sdramc_ll.c
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: BSD-1-Clause
+/*
+ * Copyright (c) 2006, Atmel Corporation
+ */
+
+#include <mach/at91sam9_sdramc.h>
+#include <mach/early_udelay.h>
+
+static inline void sdramc_wr(const struct at91sam9_sdramc_config *config,
+ unsigned int offset,
+ const unsigned int value)
+{
+ writel(value, config->sdramc + offset);
+}
+
+int at91sam9_sdramc_initialize(const struct at91sam9_sdramc_config *config,
+ unsigned int sdram_address)
+{
+ unsigned int i;
+
+ /* Step#1 SDRAM feature must be in the configuration register */
+ sdramc_wr(config, AT91_SDRAMC_CR, config->cr);
+
+ /* Step#2 For mobile SDRAM, temperature-compensated self refresh(TCSR),... */
+
+ /* Step#3 The SDRAM memory type must be set in the Memory Device Register */
+ sdramc_wr(config, AT91_SDRAMC_MDR, config->mdr);
+
+ /* Step#4 The minimum pause of 200 us is provided to precede any single toggle */
+ early_udelay(200);
+
+ /* Step#5 A NOP command is issued to the SDRAM devices */
+ sdramc_wr(config, AT91_SDRAMC_MR, AT91_SDRAMC_MODE_NOP);
+ writel(0x00000000, sdram_address);
+
+ /* Step#6 An All Banks Precharge command is issued to the SDRAM devices */
+ sdramc_wr(config, AT91_SDRAMC_MR, AT91_SDRAMC_MODE_PRECHARGE);
+ writel(0x00000000, sdram_address);
+
+ /* Pause cycles */
+ early_udelay(2000);
+
+ /* Step#7 Eight auto-refresh cycles are provided */
+ for (i = 0; i < 8; i++) {
+ sdramc_wr(config, AT91_SDRAMC_MR, AT91_SDRAMC_MODE_REFRESH);
+ writel(0x00000001 + i, sdram_address + 4 + 4 * i);
+ }
+
+ /* Pause cycles */
+ early_udelay(200);
+
+ /* Step#8 A Mode Register set (MRS) cycle is issued to program (TCSR, PASR, DS) */
+ sdramc_wr(config, AT91_SDRAMC_MR, AT91_SDRAMC_MODE_LMR);
+ writel(0xcafedede, sdram_address + 0x24);
+
+ /* Pause cycles */
+ early_udelay(200);
+
+ /* Step#9 For mobile SDRAM initialization, an Extended Mode Register set ... */
+
+ /* Step#10 The application must go into Normal Mode, setting Mode to 0
+ * and perform a write access at any location in the SDRAM.
+ */
+ sdramc_wr(config, AT91_SDRAMC_MR, AT91_SDRAMC_MODE_NORMAL); // Set mode
+ writel(0x00000000, sdram_address); // Perform mode
+
+ /* Step#11 Write the refresh rate into the count field in the Refresh Register. */
+ sdramc_wr(config, AT91_SDRAMC_TR, config->tr);
+
+ return 0;
+}
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
index 3cda10165..c5271af82 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
@@ -85,6 +85,18 @@
#include <mach/at91sam9261.h>
#include <mach/at91sam9263.h>
+struct at91sam9_sdramc_config {
+ void __iomem *sdramc;
+ unsigned int mr;
+ unsigned int tr;
+ unsigned int cr;
+ unsigned int lpr;
+ unsigned int mdr;
+};
+
+int at91sam9_sdramc_initialize(const struct at91sam9_sdramc_config *config,
+ unsigned int sdram_address);
+
static inline u32 at91_get_sdram_size(void *base)
{
u32 val;
--
2.34.1
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [PATCH v2 03/11] ARM: at91: Add initialize function to sdramc
2022-06-28 20:38 ` [PATCH v2 03/11] ARM: at91: Add initialize function to sdramc Sam Ravnborg
@ 2022-06-29 6:50 ` Ahmad Fatoum
0 siblings, 0 replies; 21+ messages in thread
From: Ahmad Fatoum @ 2022-06-29 6:50 UTC (permalink / raw)
To: Sam Ravnborg, barebox
On 28.06.22 22:38, Sam Ravnborg wrote:
> Port the sdramc initialize function from at91bootstrap.
> It is needed from lowlevel code and is a replacement for the
> sdramc init code in at91sam926x_board_init.h
>
> Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> +int at91sam9_sdramc_initialize(const struct at91sam9_sdramc_config *config,
> + unsigned int sdram_address)
> +{
> + unsigned int i;
> +
> + /* Step#1 SDRAM feature must be in the configuration register */
> + sdramc_wr(config, AT91_SDRAMC_CR, config->cr);
> +
> + /* Step#2 For mobile SDRAM, temperature-compensated self refresh(TCSR),... */
> +
> + /* Step#3 The SDRAM memory type must be set in the Memory Device Register */
> + sdramc_wr(config, AT91_SDRAMC_MDR, config->mdr);
> +
> + /* Step#4 The minimum pause of 200 us is provided to precede any single toggle */
> + early_udelay(200);
> +
> + /* Step#5 A NOP command is issued to the SDRAM devices */
> + sdramc_wr(config, AT91_SDRAMC_MR, AT91_SDRAMC_MODE_NOP);
> + writel(0x00000000, sdram_address);
> +
> + /* Step#6 An All Banks Precharge command is issued to the SDRAM devices */
> + sdramc_wr(config, AT91_SDRAMC_MR, AT91_SDRAMC_MODE_PRECHARGE);
> + writel(0x00000000, sdram_address);
> +
> + /* Pause cycles */
> + early_udelay(2000);
> +
> + /* Step#7 Eight auto-refresh cycles are provided */
> + for (i = 0; i < 8; i++) {
> + sdramc_wr(config, AT91_SDRAMC_MR, AT91_SDRAMC_MODE_REFRESH);
> + writel(0x00000001 + i, sdram_address + 4 + 4 * i);
> + }
> +
> + /* Pause cycles */
> + early_udelay(200);
> +
> + /* Step#8 A Mode Register set (MRS) cycle is issued to program (TCSR, PASR, DS) */
> + sdramc_wr(config, AT91_SDRAMC_MR, AT91_SDRAMC_MODE_LMR);
> + writel(0xcafedede, sdram_address + 0x24);
> +
> + /* Pause cycles */
> + early_udelay(200);
> +
> + /* Step#9 For mobile SDRAM initialization, an Extended Mode Register set ... */
> +
> + /* Step#10 The application must go into Normal Mode, setting Mode to 0
> + * and perform a write access at any location in the SDRAM.
> + */
> + sdramc_wr(config, AT91_SDRAMC_MR, AT91_SDRAMC_MODE_NORMAL); // Set mode
> + writel(0x00000000, sdram_address); // Perform mode
> +
> + /* Step#11 Write the refresh rate into the count field in the Refresh Register. */
> + sdramc_wr(config, AT91_SDRAMC_TR, config->tr);
> +
> + return 0;
Nitpick: Function can be void if it always reports success.
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v2 04/11] ARM: at91: Provide at91_mux_pio_pin for use in lowlevel
2022-06-28 20:38 [PATCH 0/11] ARM: at91: Add pbl support to skov-arm9cpu Sam Ravnborg
` (2 preceding siblings ...)
2022-06-28 20:38 ` [PATCH v2 03/11] ARM: at91: Add initialize function to sdramc Sam Ravnborg
@ 2022-06-28 20:38 ` Sam Ravnborg
2022-06-29 6:50 ` Ahmad Fatoum
2022-06-28 20:38 ` [PATCH v2 05/11] mci: atmel_mci: Add PBL helper to configure highcapacity Sam Ravnborg
` (7 subsequent siblings)
11 siblings, 1 reply; 21+ messages in thread
From: Sam Ravnborg @ 2022-06-28 20:38 UTC (permalink / raw)
To: barebox, Ahmad Fatoum; +Cc: Sam Ravnborg
Lowlevel init code may wish the ability to configure pins, e.g. for low
level debug UART. The pinctrl-at91 driver already exports an
at91_mux_pin function, but that one is only usable after driver
probe. Instead, provide an at91_mux_pio_pin function, which can be used
at all times.
This is similar to the already existing at91_mux_pio3_pin function
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
---
arch/arm/mach-at91/include/mach/gpio.h | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h
index ddd6971e3..7f84f41e5 100644
--- a/arch/arm/mach-at91/include/mach/gpio.h
+++ b/arch/arm/mach-at91/include/mach/gpio.h
@@ -151,6 +151,31 @@ static inline int at91_mux_gpio_get(void __iomem *pio, unsigned mask)
return (pdsr & mask) != 0;
}
+static inline void at91_mux_pio_pin(void __iomem *pio, unsigned mask,
+ enum at91_mux mux, int gpio_state)
+{
+ at91_mux_disable_interrupt(pio, mask);
+
+ switch(mux) {
+ case AT91_MUX_GPIO:
+ at91_mux_gpio_enable(pio, mask);
+ break;
+ case AT91_MUX_PERIPH_A:
+ at91_mux_set_A_periph(pio, mask);
+ break;
+ case AT91_MUX_PERIPH_B:
+ at91_mux_set_B_periph(pio, mask);
+ break;
+ default:
+ /* ignore everything else */
+ break;
+ }
+ if (mux != AT91_MUX_GPIO)
+ at91_mux_gpio_disable(pio, mask);
+
+ at91_mux_set_pullup(pio, mask, gpio_state & GPIO_PULL_UP);
+}
+
static inline void at91_mux_pio3_pin(void __iomem *pio, unsigned mask,
enum at91_mux mux, int gpio_state)
{
--
2.34.1
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [PATCH v2 04/11] ARM: at91: Provide at91_mux_pio_pin for use in lowlevel
2022-06-28 20:38 ` [PATCH v2 04/11] ARM: at91: Provide at91_mux_pio_pin for use in lowlevel Sam Ravnborg
@ 2022-06-29 6:50 ` Ahmad Fatoum
0 siblings, 0 replies; 21+ messages in thread
From: Ahmad Fatoum @ 2022-06-29 6:50 UTC (permalink / raw)
To: Sam Ravnborg, barebox
On 28.06.22 22:38, Sam Ravnborg wrote:
> Lowlevel init code may wish the ability to configure pins, e.g. for low
> level debug UART. The pinctrl-at91 driver already exports an
> at91_mux_pin function, but that one is only usable after driver
> probe. Instead, provide an at91_mux_pio_pin function, which can be used
> at all times.
>
> This is similar to the already existing at91_mux_pio3_pin function
>
> Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> ---
> arch/arm/mach-at91/include/mach/gpio.h | 25 +++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h
> index ddd6971e3..7f84f41e5 100644
> --- a/arch/arm/mach-at91/include/mach/gpio.h
> +++ b/arch/arm/mach-at91/include/mach/gpio.h
> @@ -151,6 +151,31 @@ static inline int at91_mux_gpio_get(void __iomem *pio, unsigned mask)
> return (pdsr & mask) != 0;
> }
>
> +static inline void at91_mux_pio_pin(void __iomem *pio, unsigned mask,
> + enum at91_mux mux, int gpio_state)
> +{
> + at91_mux_disable_interrupt(pio, mask);
> +
> + switch(mux) {
> + case AT91_MUX_GPIO:
> + at91_mux_gpio_enable(pio, mask);
> + break;
> + case AT91_MUX_PERIPH_A:
> + at91_mux_set_A_periph(pio, mask);
> + break;
> + case AT91_MUX_PERIPH_B:
> + at91_mux_set_B_periph(pio, mask);
> + break;
> + default:
> + /* ignore everything else */
> + break;
> + }
> + if (mux != AT91_MUX_GPIO)
> + at91_mux_gpio_disable(pio, mask);
> +
> + at91_mux_set_pullup(pio, mask, gpio_state & GPIO_PULL_UP);
> +}
> +
> static inline void at91_mux_pio3_pin(void __iomem *pio, unsigned mask,
> enum at91_mux mux, int gpio_state)
> {
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v2 05/11] mci: atmel_mci: Add PBL helper to configure highcapacity
2022-06-28 20:38 [PATCH 0/11] ARM: at91: Add pbl support to skov-arm9cpu Sam Ravnborg
` (3 preceding siblings ...)
2022-06-28 20:38 ` [PATCH v2 04/11] ARM: at91: Provide at91_mux_pio_pin for use in lowlevel Sam Ravnborg
@ 2022-06-28 20:38 ` Sam Ravnborg
2022-06-29 6:50 ` Ahmad Fatoum
2022-06-28 20:38 ` [PATCH v2 06/11] ARM: at91: Add at91sam9 xload_mmc for PBL use Sam Ravnborg
` (6 subsequent siblings)
11 siblings, 1 reply; 21+ messages in thread
From: Sam Ravnborg @ 2022-06-28 20:38 UTC (permalink / raw)
To: barebox, Ahmad Fatoum; +Cc: Sam Ravnborg
Older atmel SoC's like at91sam9263 do not support highcapacity SD cards.
Add helper that can be used to disable highcapacity support
in the PBL code - as probing for the SD card type is not an option.
Suggested-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
---
arch/arm/mach-at91/include/mach/xload.h | 1 +
drivers/mci/atmel_mci_pbl.c | 5 +++++
2 files changed, 6 insertions(+)
diff --git a/arch/arm/mach-at91/include/mach/xload.h b/arch/arm/mach-at91/include/mach/xload.h
index e9336d59c..488279c1a 100644
--- a/arch/arm/mach-at91/include/mach/xload.h
+++ b/arch/arm/mach-at91/include/mach/xload.h
@@ -13,5 +13,6 @@ void __noreturn sama5d3_atmci_start_image(u32 r4, unsigned int clock,
int at91_sdhci_bio_init(struct pbl_bio *bio, void __iomem *base);
int at91_mci_bio_init(struct pbl_bio *bio, void __iomem *base,
unsigned int clock, unsigned int slot);
+void at91_mci_bio_set_highcapacity(bool highcapacity_card);
#endif /* __MACH_XLOAD_H */
diff --git a/drivers/mci/atmel_mci_pbl.c b/drivers/mci/atmel_mci_pbl.c
index 767d6f3ce..65d8b3632 100644
--- a/drivers/mci/atmel_mci_pbl.c
+++ b/drivers/mci/atmel_mci_pbl.c
@@ -114,3 +114,8 @@ int at91_mci_bio_init(struct pbl_bio *bio, void __iomem *base,
return 0;
}
+
+void at91_mci_bio_set_highcapacity(bool highcapacity_card)
+{
+ atmci_sdcard.highcapacity_card = highcapacity_card;
+}
--
2.34.1
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [PATCH v2 05/11] mci: atmel_mci: Add PBL helper to configure highcapacity
2022-06-28 20:38 ` [PATCH v2 05/11] mci: atmel_mci: Add PBL helper to configure highcapacity Sam Ravnborg
@ 2022-06-29 6:50 ` Ahmad Fatoum
0 siblings, 0 replies; 21+ messages in thread
From: Ahmad Fatoum @ 2022-06-29 6:50 UTC (permalink / raw)
To: Sam Ravnborg, barebox
On 28.06.22 22:38, Sam Ravnborg wrote:
> Older atmel SoC's like at91sam9263 do not support highcapacity SD cards.
> Add helper that can be used to disable highcapacity support
> in the PBL code - as probing for the SD card type is not an option.
Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
>
> Suggested-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
> ---
> arch/arm/mach-at91/include/mach/xload.h | 1 +
> drivers/mci/atmel_mci_pbl.c | 5 +++++
> 2 files changed, 6 insertions(+)
>
> diff --git a/arch/arm/mach-at91/include/mach/xload.h b/arch/arm/mach-at91/include/mach/xload.h
> index e9336d59c..488279c1a 100644
> --- a/arch/arm/mach-at91/include/mach/xload.h
> +++ b/arch/arm/mach-at91/include/mach/xload.h
> @@ -13,5 +13,6 @@ void __noreturn sama5d3_atmci_start_image(u32 r4, unsigned int clock,
> int at91_sdhci_bio_init(struct pbl_bio *bio, void __iomem *base);
> int at91_mci_bio_init(struct pbl_bio *bio, void __iomem *base,
> unsigned int clock, unsigned int slot);
> +void at91_mci_bio_set_highcapacity(bool highcapacity_card);
>
> #endif /* __MACH_XLOAD_H */
> diff --git a/drivers/mci/atmel_mci_pbl.c b/drivers/mci/atmel_mci_pbl.c
> index 767d6f3ce..65d8b3632 100644
> --- a/drivers/mci/atmel_mci_pbl.c
> +++ b/drivers/mci/atmel_mci_pbl.c
> @@ -114,3 +114,8 @@ int at91_mci_bio_init(struct pbl_bio *bio, void __iomem *base,
>
> return 0;
> }
> +
> +void at91_mci_bio_set_highcapacity(bool highcapacity_card)
> +{
> + atmci_sdcard.highcapacity_card = highcapacity_card;
> +}
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v2 06/11] ARM: at91: Add at91sam9 xload_mmc for PBL use
2022-06-28 20:38 [PATCH 0/11] ARM: at91: Add pbl support to skov-arm9cpu Sam Ravnborg
` (4 preceding siblings ...)
2022-06-28 20:38 ` [PATCH v2 05/11] mci: atmel_mci: Add PBL helper to configure highcapacity Sam Ravnborg
@ 2022-06-28 20:38 ` Sam Ravnborg
2022-06-29 6:50 ` Ahmad Fatoum
2022-06-28 20:38 ` [PATCH v2 07/11] ARM: at91: Add extra register definitions Sam Ravnborg
` (5 subsequent siblings)
11 siblings, 1 reply; 21+ messages in thread
From: Sam Ravnborg @ 2022-06-28 20:38 UTC (permalink / raw)
To: barebox, Ahmad Fatoum; +Cc: Sam Ravnborg
Add xload support to at91sam9263 similar to what is already
present for the sama5d3.
The xload supports reading barebox.bin from a SDCARD from the
PBL and load the full barebox.bin and starts it.
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
---
arch/arm/mach-at91/Makefile | 1 +
arch/arm/mach-at91/at91sam9_xload_mmc.c | 118 ++++++++++++++++++++++++
arch/arm/mach-at91/include/mach/xload.h | 4 +
3 files changed, 123 insertions(+)
create mode 100644 arch/arm/mach-at91/at91sam9_xload_mmc.c
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 12e64291b..b171d682f 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -17,6 +17,7 @@ obj-y += at91sam9_reset.o
obj-y += at91sam9g45_reset.o
obj-pbl-$(CONFIG_HAVE_AT91_DDRAMC) += ddramc.o
pbl-$(CONFIG_AT91_MCI_PBL) += xload-mmc.o
+pbl-$(CONFIG_AT91_MCI_PBL) += at91sam9_xload_mmc.o
obj-$(CONFIG_AT91SAM9_SMC) += sam9_smc.o
obj-$(CONFIG_HAVE_AT91SAM9_RST) += at91sam9_rst.o
diff --git a/arch/arm/mach-at91/at91sam9_xload_mmc.c b/arch/arm/mach-at91/at91sam9_xload_mmc.c
new file mode 100644
index 000000000..64266757d
--- /dev/null
+++ b/arch/arm/mach-at91/at91sam9_xload_mmc.c
@@ -0,0 +1,118 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* SPDX-FileCopyrightText: 2022 Sam Ravnborg */
+
+#include <debug_ll.h>
+#include <common.h>
+#include <pbl.h>
+
+#include <linux/sizes.h>
+#include <asm/cache.h>
+
+#include <mach/at91_pmc_ll.h>
+#include <mach/at91sam9263.h>
+#include <mach/at91sam926x.h>
+#include <mach/hardware.h>
+#include <mach/iomux.h>
+#include <mach/xload.h>
+#include <mach/gpio.h>
+
+typedef void (*func)(int zero, int arch, void *params);
+
+/*
+ * Load barebox.bin and start executing the first byte in the barebox image.
+ * barebox.bin is loaded to AT91_CHIPSELECT_1.
+ *
+ * To be able to load barebox.bin do a minimal init of the pheriferals
+ * used by MCI.
+ * This functions runs in PBL code and uses the PBL variant of the
+ * atmel_mci driver.
+ */
+void __noreturn sam9263_atmci_start_image(u32 mmc_id, unsigned int clock,
+ bool slot_b)
+{
+ void __iomem *pio = IOMEM(AT91SAM9263_BASE_PIOA);
+ void *buf = (void *)AT91_CHIPSELECT_1;
+ void __iomem *base;
+ struct pbl_bio bio;
+ int ret;
+
+ at91_pmc_enable_periph_clock(IOMEM(AT91SAM926X_BASE_PMC), AT91SAM9263_ID_PIOA);
+
+ if (mmc_id == 0) {
+ base = IOMEM(AT91SAM9263_BASE_MCI0);
+
+ /* CLK */
+ at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA12), AT91_MUX_PERIPH_A, 0);
+
+ if (!slot_b) {
+ /* CMD */
+ at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA1), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+
+ /* DAT0 to DAT3 */
+ at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA0), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+ at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA3), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+ at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA4), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+ at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA5), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+ } else {
+ /* CMD */
+ at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA16), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+
+ /* DAT0 to DAT3 */
+ at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA17), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+ at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA18), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+ at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA19), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+ at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA20), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+ }
+
+ at91_pmc_enable_periph_clock(IOMEM(AT91SAM926X_BASE_PMC), AT91SAM9263_ID_MCI0);
+ } else {
+ base = IOMEM(AT91SAM9263_BASE_MCI1);
+
+ /* CLK */
+ at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA6), AT91_MUX_PERIPH_A, 0);
+
+ if (!slot_b) {
+ /* CMD */
+ at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA7), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+
+ /* DAT0 to DAT3 */
+ at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA8), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+ at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA9), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+ at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA10), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+ at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA11), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+ } else {
+ /* CMD */
+ at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA21), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+
+ /* DAT0 to DAT3 */
+ at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA22), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+ at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA23), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+ at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA24), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+ at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA25), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+ }
+
+ at91_pmc_enable_periph_clock(IOMEM(AT91SAM926X_BASE_PMC), AT91SAM9263_ID_MCI1);
+ }
+
+ ret = at91_mci_bio_init(&bio, base, clock, (int)slot_b);
+ if (ret) {
+ pr_err("atmci_start_image: bio init faild: %d\n", ret);
+ goto out_panic;
+ }
+
+ /* at91sam9x do not support high capacity */
+ at91_mci_bio_set_highcapacity(false);
+
+ ret = pbl_fat_load(&bio, "barebox.bin", buf, SZ_16M);
+ if (ret < 0) {
+ pr_err("pbl_fat_load: error %d\n", ret);
+ goto out_panic;
+ }
+
+ sync_caches_for_execution();
+
+ ((func)buf)(0, 0, NULL);
+
+out_panic:
+ panic("FAT chainloading failed\n");
+}
diff --git a/arch/arm/mach-at91/include/mach/xload.h b/arch/arm/mach-at91/include/mach/xload.h
index 488279c1a..82db65e30 100644
--- a/arch/arm/mach-at91/include/mach/xload.h
+++ b/arch/arm/mach-at91/include/mach/xload.h
@@ -15,4 +15,8 @@ int at91_mci_bio_init(struct pbl_bio *bio, void __iomem *base,
unsigned int clock, unsigned int slot);
void at91_mci_bio_set_highcapacity(bool highcapacity_card);
+void __noreturn sam9263_atmci_start_image(u32 mmc_id, unsigned int clock,
+ bool slot_b);
+
+
#endif /* __MACH_XLOAD_H */
--
2.34.1
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [PATCH v2 06/11] ARM: at91: Add at91sam9 xload_mmc for PBL use
2022-06-28 20:38 ` [PATCH v2 06/11] ARM: at91: Add at91sam9 xload_mmc for PBL use Sam Ravnborg
@ 2022-06-29 6:50 ` Ahmad Fatoum
0 siblings, 0 replies; 21+ messages in thread
From: Ahmad Fatoum @ 2022-06-29 6:50 UTC (permalink / raw)
To: Sam Ravnborg, barebox
On 28.06.22 22:38, Sam Ravnborg wrote:
> Add xload support to at91sam9263 similar to what is already
> present for the sama5d3.
> The xload supports reading barebox.bin from a SDCARD from the
> PBL and load the full barebox.bin and starts it.
Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
>
> Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
> ---
> arch/arm/mach-at91/Makefile | 1 +
> arch/arm/mach-at91/at91sam9_xload_mmc.c | 118 ++++++++++++++++++++++++
> arch/arm/mach-at91/include/mach/xload.h | 4 +
> 3 files changed, 123 insertions(+)
> create mode 100644 arch/arm/mach-at91/at91sam9_xload_mmc.c
>
> diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
> index 12e64291b..b171d682f 100644
> --- a/arch/arm/mach-at91/Makefile
> +++ b/arch/arm/mach-at91/Makefile
> @@ -17,6 +17,7 @@ obj-y += at91sam9_reset.o
> obj-y += at91sam9g45_reset.o
> obj-pbl-$(CONFIG_HAVE_AT91_DDRAMC) += ddramc.o
> pbl-$(CONFIG_AT91_MCI_PBL) += xload-mmc.o
> +pbl-$(CONFIG_AT91_MCI_PBL) += at91sam9_xload_mmc.o
>
> obj-$(CONFIG_AT91SAM9_SMC) += sam9_smc.o
> obj-$(CONFIG_HAVE_AT91SAM9_RST) += at91sam9_rst.o
> diff --git a/arch/arm/mach-at91/at91sam9_xload_mmc.c b/arch/arm/mach-at91/at91sam9_xload_mmc.c
> new file mode 100644
> index 000000000..64266757d
> --- /dev/null
> +++ b/arch/arm/mach-at91/at91sam9_xload_mmc.c
> @@ -0,0 +1,118 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/* SPDX-FileCopyrightText: 2022 Sam Ravnborg */
> +
> +#include <debug_ll.h>
> +#include <common.h>
> +#include <pbl.h>
> +
> +#include <linux/sizes.h>
> +#include <asm/cache.h>
> +
> +#include <mach/at91_pmc_ll.h>
> +#include <mach/at91sam9263.h>
> +#include <mach/at91sam926x.h>
> +#include <mach/hardware.h>
> +#include <mach/iomux.h>
> +#include <mach/xload.h>
> +#include <mach/gpio.h>
> +
> +typedef void (*func)(int zero, int arch, void *params);
> +
> +/*
> + * Load barebox.bin and start executing the first byte in the barebox image.
> + * barebox.bin is loaded to AT91_CHIPSELECT_1.
> + *
> + * To be able to load barebox.bin do a minimal init of the pheriferals
> + * used by MCI.
> + * This functions runs in PBL code and uses the PBL variant of the
> + * atmel_mci driver.
> + */
> +void __noreturn sam9263_atmci_start_image(u32 mmc_id, unsigned int clock,
> + bool slot_b)
> +{
> + void __iomem *pio = IOMEM(AT91SAM9263_BASE_PIOA);
> + void *buf = (void *)AT91_CHIPSELECT_1;
> + void __iomem *base;
> + struct pbl_bio bio;
> + int ret;
> +
> + at91_pmc_enable_periph_clock(IOMEM(AT91SAM926X_BASE_PMC), AT91SAM9263_ID_PIOA);
> +
> + if (mmc_id == 0) {
> + base = IOMEM(AT91SAM9263_BASE_MCI0);
> +
> + /* CLK */
> + at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA12), AT91_MUX_PERIPH_A, 0);
> +
> + if (!slot_b) {
> + /* CMD */
> + at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA1), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
> +
> + /* DAT0 to DAT3 */
> + at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA0), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
> + at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA3), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
> + at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA4), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
> + at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA5), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
> + } else {
> + /* CMD */
> + at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA16), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
> +
> + /* DAT0 to DAT3 */
> + at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA17), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
> + at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA18), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
> + at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA19), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
> + at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA20), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
> + }
> +
> + at91_pmc_enable_periph_clock(IOMEM(AT91SAM926X_BASE_PMC), AT91SAM9263_ID_MCI0);
> + } else {
> + base = IOMEM(AT91SAM9263_BASE_MCI1);
> +
> + /* CLK */
> + at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA6), AT91_MUX_PERIPH_A, 0);
> +
> + if (!slot_b) {
> + /* CMD */
> + at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA7), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
> +
> + /* DAT0 to DAT3 */
> + at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA8), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
> + at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA9), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
> + at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA10), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
> + at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA11), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
> + } else {
> + /* CMD */
> + at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA21), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
> +
> + /* DAT0 to DAT3 */
> + at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA22), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
> + at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA23), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
> + at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA24), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
> + at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA25), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
> + }
> +
> + at91_pmc_enable_periph_clock(IOMEM(AT91SAM926X_BASE_PMC), AT91SAM9263_ID_MCI1);
> + }
> +
> + ret = at91_mci_bio_init(&bio, base, clock, (int)slot_b);
> + if (ret) {
> + pr_err("atmci_start_image: bio init faild: %d\n", ret);
> + goto out_panic;
> + }
> +
> + /* at91sam9x do not support high capacity */
> + at91_mci_bio_set_highcapacity(false);
> +
> + ret = pbl_fat_load(&bio, "barebox.bin", buf, SZ_16M);
> + if (ret < 0) {
> + pr_err("pbl_fat_load: error %d\n", ret);
> + goto out_panic;
> + }
> +
> + sync_caches_for_execution();
> +
> + ((func)buf)(0, 0, NULL);
> +
> +out_panic:
> + panic("FAT chainloading failed\n");
> +}
> diff --git a/arch/arm/mach-at91/include/mach/xload.h b/arch/arm/mach-at91/include/mach/xload.h
> index 488279c1a..82db65e30 100644
> --- a/arch/arm/mach-at91/include/mach/xload.h
> +++ b/arch/arm/mach-at91/include/mach/xload.h
> @@ -15,4 +15,8 @@ int at91_mci_bio_init(struct pbl_bio *bio, void __iomem *base,
> unsigned int clock, unsigned int slot);
> void at91_mci_bio_set_highcapacity(bool highcapacity_card);
>
> +void __noreturn sam9263_atmci_start_image(u32 mmc_id, unsigned int clock,
> + bool slot_b);
> +
> +
> #endif /* __MACH_XLOAD_H */
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v2 07/11] ARM: at91: Add extra register definitions
2022-06-28 20:38 [PATCH 0/11] ARM: at91: Add pbl support to skov-arm9cpu Sam Ravnborg
` (5 preceding siblings ...)
2022-06-28 20:38 ` [PATCH v2 06/11] ARM: at91: Add at91sam9 xload_mmc for PBL use Sam Ravnborg
@ 2022-06-28 20:38 ` Sam Ravnborg
2022-06-29 6:49 ` Ahmad Fatoum
2022-06-28 20:38 ` [PATCH v2 08/11] ARM: at91: Add lowlevel helpers for at91sam9263 Sam Ravnborg
` (4 subsequent siblings)
11 siblings, 1 reply; 21+ messages in thread
From: Sam Ravnborg @ 2022-06-28 20:38 UTC (permalink / raw)
To: barebox, Ahmad Fatoum; +Cc: Sam Ravnborg
Copied from at91bootstrap. Required in subsequent patches.
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
---
arch/arm/mach-at91/include/mach/at91_pmc.h | 2 +
arch/arm/mach-at91/include/mach/at91sam9263.h | 14 +++
.../include/mach/at91sam9263_matrix.h | 23 +++-
arch/arm/mach-at91/include/mach/at91sam926x.h | 2 +
.../mach-at91/include/mach/at91sam9_sdramc.h | 108 +++++++++++++++++-
5 files changed, 141 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
index 2860ea485..c5ce0f82a 100644
--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
+++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
@@ -170,6 +170,8 @@
#define AT91_PMC_IPLLA_1 (1 << 8)
#define AT91_PMC_IPLLA_2 (2 << 8)
#define AT91_PMC_IPLLA_3 (3 << 8)
+#define AT91SAM9_PMC_ICPPLLA (1 << 0)
+#define AT91SAM9_PMC_ICPPLLB (1 << 16)
#define AT91_PMC_PROT 0xe4 /* Write Protect Mode Register [some SAM9] */
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h
index 2ea9aadaf..229f8d16b 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9263.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9263.h
@@ -108,4 +108,18 @@
#define AT91SAM9263_DMAC_BASE 0x00800000 /* DMA Controller */
#define AT91SAM9263_UHP_BASE 0x00a00000 /* USB Host controller */
+/*
+ * External memory
+ */
+#define AT91SAM9263_BASE_EBI0_CS0 0x10000000
+#define AT91SAM9263_BASE_EBI0_CS1 0x20000000 /* EBI0 SDRAMC */
+#define AT91SAM9263_BASE_EBI0_CS2 0x30000000
+#define AT91SAM9263_BASE_EBI0_CS3 0x40000000 /* EBI0 NANDFlash */
+#define AT91SAM9263_BASE_EBI0_CS4 0x50000000 /* Compact Flash Slot 0 */
+#define AT91SAM9263_BASE_EBI0_CS5 0x60000000 /* Compact Flash Slot 1 */
+#define AT91SAM9263_BASE_EBI1_CS0 0x70000000
+#define AT91SAM9263_BASE_EBI1_CS1 0x80000000 /* EBI1 SDRAMC */
+#define AT91SAM9263_BASE_EBI1_CS2 0x90000000 /* EBI1 NANDFlash */
+
+
#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
index 2f10ce096..837cceb41 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
@@ -25,7 +25,7 @@
#define AT91SAM9263_MATRIX_ULBT_SINGLE (1 << 0)
#define AT91SAM9263_MATRIX_ULBT_FOUR (2 << 0)
#define AT91SAM9263_MATRIX_ULBT_EIGHT (3 << 0)
-#define AT91SAM9263_MATRIX_ULBT_SIXTEEN (4 << 0)
+#define AT91SAM9263_MATRIX_ULBT_SIXTEEN (4 << 0)
#define AT91SAM9263_MATRIX_SCFG0 (0x40) /* Slave Configuration Register 0 */
#define AT91SAM9263_MATRIX_SCFG1 (0x44) /* Slave Configuration Register 1 */
@@ -35,12 +35,22 @@
#define AT91SAM9263_MATRIX_SCFG5 (0x54) /* Slave Configuration Register 5 */
#define AT91SAM9263_MATRIX_SCFG6 (0x58) /* Slave Configuration Register 6 */
#define AT91SAM9263_MATRIX_SCFG7 (0x5C) /* Slave Configuration Register 7 */
-#define AT91SAM9263_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
+#define AT91SAM9263_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
+#define AT91SAM9263_MATRIX_SLOT_CYCLE_(x) (x << 0)
#define AT91SAM9263_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
#define AT91SAM9263_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
#define AT91SAM9263_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
#define AT91SAM9263_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
#define AT91SAM9263_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
+#define AT91SAM9263_MATRIX_FIXED_DEFMSTR_ARM926I (0x0 << 18)
+#define AT91SAM9263_MATRIX_FIXED_DEFMSTR_ARM926D (0x1 << 18)
+#define AT91SAM9263_MATRIX_FIXED_DEFMSTR_PDC (0x2 << 18)
+#define AT91SAM9263_MATRIX_FIXED_DEFMSTR_LCDC (0x3 << 18)
+#define AT91SAM9263_MATRIX_FIXED_DEFMSTR_2DGC (0x4 << 18)
+#define AT91SAM9263_MATRIX_FIXED_DEFMSTR_ISI (0x5 << 18)
+#define AT91SAM9263_MATRIX_FIXED_DEFMSTR_DMA (0x6 << 18)
+#define AT91SAM9263_MATRIX_FIXED_DEFMSTR_EMAC (0x7 << 18)
+#define AT91SAM9263_MATRIX_FIXED_DEFMSTR_USB (0x8 << 18)
#define AT91SAM9263_MATRIX_ARBT (3 << 24) /* Arbitration Type */
#define AT91SAM9263_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
#define AT91SAM9263_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
@@ -62,14 +72,23 @@
#define AT91SAM9263_MATRIX_PRAS7 (0xB8) /* Priority Register A for Slave 7 */
#define AT91SAM9263_MATRIX_PRBS7 (0xBC) /* Priority Register B for Slave 7 */
#define AT91SAM9263_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
+#define AT91SAM9263_MATRIX_M0PR_(x) (x << 0) /* ARM926EJ-S Instruction priority */
#define AT91SAM9263_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
+#define AT91SAM9263_MATRIX_M1PR_(x) (x << 4) /* ARM926EJ-S Data priority */
#define AT91SAM9263_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
+#define AT91SAM9263_MATRIX_M2PR_(x) (x << 8) /* PDC priority */
#define AT91SAM9263_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
+#define AT91SAM9263_MATRIX_M3PR_(x) (x << 12) /* LCDC priority */
#define AT91SAM9263_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
+#define AT91SAM9263_MATRIX_M4PR_(x) (x << 16) /* 2DGC priority */
#define AT91SAM9263_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
+#define AT91SAM9263_MATRIX_M5PR_(x) (x << 20) /* ISI priority */
#define AT91SAM9263_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
+#define AT91SAM9263_MATRIX_M6PR_(x) (x << 24) /* DMA priority */
#define AT91SAM9263_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
+#define AT91SAM9263_MATRIX_M7PR_(x) (x << 28) /* EMAC priority */
#define AT91SAM9263_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
+#define AT91SAM9263_MATRIX_M8PR_(x) (x << 0) /* USB Priority */
#define AT91SAM9263_MATRIX_MRCR (0x100) /* Master Remap Control Register */
#define AT91SAM9263_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
diff --git a/arch/arm/mach-at91/include/mach/at91sam926x.h b/arch/arm/mach-at91/include/mach/at91sam926x.h
index 8ef83010d..ae7e224a7 100644
--- a/arch/arm/mach-at91/include/mach/at91sam926x.h
+++ b/arch/arm/mach-at91/include/mach/at91sam926x.h
@@ -7,4 +7,6 @@
#define AT91SAM926X_BASE_RSTC 0xfffffd00
#define AT91SAM926X_BASE_WDT 0xfffffd40
+#define AT91SAM926X_ID_SYS 1 /* System Controller Interrupt */
+
#endif /* __MACH_AT91SAM926X_H */
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
index c5271af82..0e05387aa 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
@@ -47,12 +47,108 @@
#define AT91_SDRAMC_DBW (1 << 7) /* Data Bus Width */
#define AT91_SDRAMC_DBW_32 (0 << 7)
#define AT91_SDRAMC_DBW_16 (1 << 7)
-#define AT91_SDRAMC_TWR (0xf << 8) /* Write Recovery Delay */
-#define AT91_SDRAMC_TRC (0xf << 12) /* Row Cycle Delay */
-#define AT91_SDRAMC_TRP (0xf << 16) /* Row Precharge Delay */
-#define AT91_SDRAMC_TRCD (0xf << 20) /* Row to Column Delay */
-#define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */
-#define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */
+#define AT91_SDRAMC_TWR (0xF << 8) /* Number of Write Recovery Time Cycles */
+#define AT91_SDRAMC_TWR_0 (0x0 << 8)
+#define AT91_SDRAMC_TWR_1 (0x1 << 8)
+#define AT91_SDRAMC_TWR_2 (0x2 << 8)
+#define AT91_SDRAMC_TWR_3 (0x3 << 8)
+#define AT91_SDRAMC_TWR_4 (0x4 << 8)
+#define AT91_SDRAMC_TWR_5 (0x5 << 8)
+#define AT91_SDRAMC_TWR_6 (0x6 << 8)
+#define AT91_SDRAMC_TWR_7 (0x7 << 8)
+#define AT91_SDRAMC_TWR_8 (0x8 << 8)
+#define AT91_SDRAMC_TWR_9 (0x9 << 8)
+#define AT91_SDRAMC_TWR_10 (0xA << 8)
+#define AT91_SDRAMC_TWR_11 (0xB << 8)
+#define AT91_SDRAMC_TWR_12 (0xC << 8)
+#define AT91_SDRAMC_TWR_13 (0xD << 8)
+#define AT91_SDRAMC_TWR_14 (0xE << 8)
+#define AT91_SDRAMC_TWR_15 (0xF << 8)
+#define AT91_SDRAMC_TRC (0xF << 12) /* Number of Row Cycle Delay Time Cycles */
+#define AT91_SDRAMC_TRC_0 (0x0 << 12)
+#define AT91_SDRAMC_TRC_1 (0x1 << 12)
+#define AT91_SDRAMC_TRC_2 (0x2 << 12)
+#define AT91_SDRAMC_TRC_3 (0x3 << 12)
+#define AT91_SDRAMC_TRC_4 (0x4 << 12)
+#define AT91_SDRAMC_TRC_5 (0x5 << 12)
+#define AT91_SDRAMC_TRC_6 (0x6 << 12)
+#define AT91_SDRAMC_TRC_7 (0x7 << 12)
+#define AT91_SDRAMC_TRC_8 (0x8 << 12)
+#define AT91_SDRAMC_TRC_9 (0x9 << 12)
+#define AT91_SDRAMC_TRC_10 (0xA << 12)
+#define AT91_SDRAMC_TRC_11 (0xB << 12)
+#define AT91_SDRAMC_TRC_12 (0xC << 12)
+#define AT91_SDRAMC_TRC_13 (0xD << 12)
+#define AT91_SDRAMC_TRC_14 (0xE << 12)
+#define AT91_SDRAMC_TRC_15 (0xF << 12)
+#define AT91_SDRAMC_TRP (0xF << 16) /* Number of Row Precharge Delay Time Cycles */
+#define AT91_SDRAMC_TRP_0 (0x0 << 16)
+#define AT91_SDRAMC_TRP_1 (0x1 << 16)
+#define AT91_SDRAMC_TRP_2 (0x2 << 16)
+#define AT91_SDRAMC_TRP_3 (0x3 << 16)
+#define AT91_SDRAMC_TRP_4 (0x4 << 16)
+#define AT91_SDRAMC_TRP_5 (0x5 << 16)
+#define AT91_SDRAMC_TRP_6 (0x6 << 16)
+#define AT91_SDRAMC_TRP_7 (0x7 << 16)
+#define AT91_SDRAMC_TRP_8 (0x8 << 16)
+#define AT91_SDRAMC_TRP_9 (0x9 << 16)
+#define AT91_SDRAMC_TRP_10 (0xA << 16)
+#define AT91_SDRAMC_TRP_11 (0xB << 16)
+#define AT91_SDRAMC_TRP_12 (0xC << 16)
+#define AT91_SDRAMC_TRP_13 (0xD << 16)
+#define AT91_SDRAMC_TRP_14 (0xE << 16)
+#define AT91_SDRAMC_TRP_15 (0xF << 16)
+#define AT91_SDRAMC_TRCD (0xF << 20) /* Number of Row to Column Delay Time Cycles */
+#define AT91_SDRAMC_TRCD_0 (0x0 << 20)
+#define AT91_SDRAMC_TRCD_1 (0x1 << 20)
+#define AT91_SDRAMC_TRCD_2 (0x2 << 20)
+#define AT91_SDRAMC_TRCD_3 (0x3 << 20)
+#define AT91_SDRAMC_TRCD_4 (0x4 << 20)
+#define AT91_SDRAMC_TRCD_5 (0x5 << 20)
+#define AT91_SDRAMC_TRCD_6 (0x6 << 20)
+#define AT91_SDRAMC_TRCD_7 (0x7 << 20)
+#define AT91_SDRAMC_TRCD_8 (0x8 << 20)
+#define AT91_SDRAMC_TRCD_9 (0x9 << 20)
+#define AT91_SDRAMC_TRCD_10 (0xA << 20)
+#define AT91_SDRAMC_TRCD_11 (0xB << 20)
+#define AT91_SDRAMC_TRCD_12 (0xC << 20)
+#define AT91_SDRAMC_TRCD_13 (0xD << 20)
+#define AT91_SDRAMC_TRCD_14 (0xE << 20)
+#define AT91_SDRAMC_TRCD_15 (0xF << 20)
+#define AT91_SDRAMC_TRAS (0xF << 24) /* Number of Active to Precharge Delay Time Cycles */
+#define AT91_SDRAMC_TRAS_0 (0x0 << 24)
+#define AT91_SDRAMC_TRAS_1 (0x1 << 24)
+#define AT91_SDRAMC_TRAS_2 (0x2 << 24)
+#define AT91_SDRAMC_TRAS_3 (0x3 << 24)
+#define AT91_SDRAMC_TRAS_4 (0x4 << 24)
+#define AT91_SDRAMC_TRAS_5 (0x5 << 24)
+#define AT91_SDRAMC_TRAS_6 (0x6 << 24)
+#define AT91_SDRAMC_TRAS_7 (0x7 << 24)
+#define AT91_SDRAMC_TRAS_8 (0x8 << 24)
+#define AT91_SDRAMC_TRAS_9 (0x9 << 24)
+#define AT91_SDRAMC_TRAS_10 (0xA << 24)
+#define AT91_SDRAMC_TRAS_11 (0xB << 24)
+#define AT91_SDRAMC_TRAS_12 (0xC << 24)
+#define AT91_SDRAMC_TRAS_13 (0xD << 24)
+#define AT91_SDRAMC_TRAS_14 (0xE << 24)
+#define AT91_SDRAMC_TRAS_15 (0xF << 24)
+#define AT91_SDRAMC_TXS (0xF << 28) /* Number of Exit Self Refresh to Active Delay Time Cycles */
+#define AT91_SDRAMC_TXSR_0 (0x0 << 28)
+#define AT91_SDRAMC_TXSR_1 (0x1 << 28)
+#define AT91_SDRAMC_TXSR_2 (0x2 << 28)
+#define AT91_SDRAMC_TXSR_3 (0x3 << 28)
+#define AT91_SDRAMC_TXSR_4 (0x4 << 28)
+#define AT91_SDRAMC_TXSR_5 (0x5 << 28)
+#define AT91_SDRAMC_TXSR_6 (0x6 << 28)
+#define AT91_SDRAMC_TXSR_7 (0x7 << 28)
+#define AT91_SDRAMC_TXSR_8 (0x8 << 28)
+#define AT91_SDRAMC_TXSR_9 (0x9 << 28)
+#define AT91_SDRAMC_TXSR_10 (0xA << 28)
+#define AT91_SDRAMC_TXSR_11 (0xB << 28)
+#define AT91_SDRAMC_TXSR_12 (0xC << 28)
+#define AT91_SDRAMC_TXSR_13 (0xD << 28)
+#define AT91_SDRAMC_TXSR_14 (0xE << 28)
+#define AT91_SDRAMC_TXSR_15 (0xF << 28)
#define AT91_SDRAMC_LPR 0x10 /* SDRAM Controller Low Power Register */
#define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */
--
2.34.1
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [PATCH v2 07/11] ARM: at91: Add extra register definitions
2022-06-28 20:38 ` [PATCH v2 07/11] ARM: at91: Add extra register definitions Sam Ravnborg
@ 2022-06-29 6:49 ` Ahmad Fatoum
0 siblings, 0 replies; 21+ messages in thread
From: Ahmad Fatoum @ 2022-06-29 6:49 UTC (permalink / raw)
To: Sam Ravnborg, barebox
On 28.06.22 22:38, Sam Ravnborg wrote:
> Copied from at91bootstrap. Required in subsequent patches.
Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
>
> Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
> ---
> arch/arm/mach-at91/include/mach/at91_pmc.h | 2 +
> arch/arm/mach-at91/include/mach/at91sam9263.h | 14 +++
> .../include/mach/at91sam9263_matrix.h | 23 +++-
> arch/arm/mach-at91/include/mach/at91sam926x.h | 2 +
> .../mach-at91/include/mach/at91sam9_sdramc.h | 108 +++++++++++++++++-
> 5 files changed, 141 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
> index 2860ea485..c5ce0f82a 100644
> --- a/arch/arm/mach-at91/include/mach/at91_pmc.h
> +++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
> @@ -170,6 +170,8 @@
> #define AT91_PMC_IPLLA_1 (1 << 8)
> #define AT91_PMC_IPLLA_2 (2 << 8)
> #define AT91_PMC_IPLLA_3 (3 << 8)
> +#define AT91SAM9_PMC_ICPPLLA (1 << 0)
> +#define AT91SAM9_PMC_ICPPLLB (1 << 16)
>
>
> #define AT91_PMC_PROT 0xe4 /* Write Protect Mode Register [some SAM9] */
> diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h
> index 2ea9aadaf..229f8d16b 100644
> --- a/arch/arm/mach-at91/include/mach/at91sam9263.h
> +++ b/arch/arm/mach-at91/include/mach/at91sam9263.h
> @@ -108,4 +108,18 @@
> #define AT91SAM9263_DMAC_BASE 0x00800000 /* DMA Controller */
> #define AT91SAM9263_UHP_BASE 0x00a00000 /* USB Host controller */
>
> +/*
> + * External memory
> + */
> +#define AT91SAM9263_BASE_EBI0_CS0 0x10000000
> +#define AT91SAM9263_BASE_EBI0_CS1 0x20000000 /* EBI0 SDRAMC */
> +#define AT91SAM9263_BASE_EBI0_CS2 0x30000000
> +#define AT91SAM9263_BASE_EBI0_CS3 0x40000000 /* EBI0 NANDFlash */
> +#define AT91SAM9263_BASE_EBI0_CS4 0x50000000 /* Compact Flash Slot 0 */
> +#define AT91SAM9263_BASE_EBI0_CS5 0x60000000 /* Compact Flash Slot 1 */
> +#define AT91SAM9263_BASE_EBI1_CS0 0x70000000
> +#define AT91SAM9263_BASE_EBI1_CS1 0x80000000 /* EBI1 SDRAMC */
> +#define AT91SAM9263_BASE_EBI1_CS2 0x90000000 /* EBI1 NANDFlash */
> +
> +
> #endif
> diff --git a/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
> index 2f10ce096..837cceb41 100644
> --- a/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
> +++ b/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
> @@ -25,7 +25,7 @@
> #define AT91SAM9263_MATRIX_ULBT_SINGLE (1 << 0)
> #define AT91SAM9263_MATRIX_ULBT_FOUR (2 << 0)
> #define AT91SAM9263_MATRIX_ULBT_EIGHT (3 << 0)
> -#define AT91SAM9263_MATRIX_ULBT_SIXTEEN (4 << 0)
> +#define AT91SAM9263_MATRIX_ULBT_SIXTEEN (4 << 0)
>
> #define AT91SAM9263_MATRIX_SCFG0 (0x40) /* Slave Configuration Register 0 */
> #define AT91SAM9263_MATRIX_SCFG1 (0x44) /* Slave Configuration Register 1 */
> @@ -35,12 +35,22 @@
> #define AT91SAM9263_MATRIX_SCFG5 (0x54) /* Slave Configuration Register 5 */
> #define AT91SAM9263_MATRIX_SCFG6 (0x58) /* Slave Configuration Register 6 */
> #define AT91SAM9263_MATRIX_SCFG7 (0x5C) /* Slave Configuration Register 7 */
> -#define AT91SAM9263_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
> +#define AT91SAM9263_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
> +#define AT91SAM9263_MATRIX_SLOT_CYCLE_(x) (x << 0)
> #define AT91SAM9263_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
> #define AT91SAM9263_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
> #define AT91SAM9263_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
> #define AT91SAM9263_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
> #define AT91SAM9263_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
> +#define AT91SAM9263_MATRIX_FIXED_DEFMSTR_ARM926I (0x0 << 18)
> +#define AT91SAM9263_MATRIX_FIXED_DEFMSTR_ARM926D (0x1 << 18)
> +#define AT91SAM9263_MATRIX_FIXED_DEFMSTR_PDC (0x2 << 18)
> +#define AT91SAM9263_MATRIX_FIXED_DEFMSTR_LCDC (0x3 << 18)
> +#define AT91SAM9263_MATRIX_FIXED_DEFMSTR_2DGC (0x4 << 18)
> +#define AT91SAM9263_MATRIX_FIXED_DEFMSTR_ISI (0x5 << 18)
> +#define AT91SAM9263_MATRIX_FIXED_DEFMSTR_DMA (0x6 << 18)
> +#define AT91SAM9263_MATRIX_FIXED_DEFMSTR_EMAC (0x7 << 18)
> +#define AT91SAM9263_MATRIX_FIXED_DEFMSTR_USB (0x8 << 18)
> #define AT91SAM9263_MATRIX_ARBT (3 << 24) /* Arbitration Type */
> #define AT91SAM9263_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
> #define AT91SAM9263_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
> @@ -62,14 +72,23 @@
> #define AT91SAM9263_MATRIX_PRAS7 (0xB8) /* Priority Register A for Slave 7 */
> #define AT91SAM9263_MATRIX_PRBS7 (0xBC) /* Priority Register B for Slave 7 */
> #define AT91SAM9263_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
> +#define AT91SAM9263_MATRIX_M0PR_(x) (x << 0) /* ARM926EJ-S Instruction priority */
> #define AT91SAM9263_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
> +#define AT91SAM9263_MATRIX_M1PR_(x) (x << 4) /* ARM926EJ-S Data priority */
> #define AT91SAM9263_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
> +#define AT91SAM9263_MATRIX_M2PR_(x) (x << 8) /* PDC priority */
> #define AT91SAM9263_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
> +#define AT91SAM9263_MATRIX_M3PR_(x) (x << 12) /* LCDC priority */
> #define AT91SAM9263_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
> +#define AT91SAM9263_MATRIX_M4PR_(x) (x << 16) /* 2DGC priority */
> #define AT91SAM9263_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
> +#define AT91SAM9263_MATRIX_M5PR_(x) (x << 20) /* ISI priority */
> #define AT91SAM9263_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
> +#define AT91SAM9263_MATRIX_M6PR_(x) (x << 24) /* DMA priority */
> #define AT91SAM9263_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
> +#define AT91SAM9263_MATRIX_M7PR_(x) (x << 28) /* EMAC priority */
> #define AT91SAM9263_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
> +#define AT91SAM9263_MATRIX_M8PR_(x) (x << 0) /* USB Priority */
>
> #define AT91SAM9263_MATRIX_MRCR (0x100) /* Master Remap Control Register */
> #define AT91SAM9263_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
> diff --git a/arch/arm/mach-at91/include/mach/at91sam926x.h b/arch/arm/mach-at91/include/mach/at91sam926x.h
> index 8ef83010d..ae7e224a7 100644
> --- a/arch/arm/mach-at91/include/mach/at91sam926x.h
> +++ b/arch/arm/mach-at91/include/mach/at91sam926x.h
> @@ -7,4 +7,6 @@
> #define AT91SAM926X_BASE_RSTC 0xfffffd00
> #define AT91SAM926X_BASE_WDT 0xfffffd40
>
> +#define AT91SAM926X_ID_SYS 1 /* System Controller Interrupt */
> +
> #endif /* __MACH_AT91SAM926X_H */
> diff --git a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
> index c5271af82..0e05387aa 100644
> --- a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
> +++ b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
> @@ -47,12 +47,108 @@
> #define AT91_SDRAMC_DBW (1 << 7) /* Data Bus Width */
> #define AT91_SDRAMC_DBW_32 (0 << 7)
> #define AT91_SDRAMC_DBW_16 (1 << 7)
> -#define AT91_SDRAMC_TWR (0xf << 8) /* Write Recovery Delay */
> -#define AT91_SDRAMC_TRC (0xf << 12) /* Row Cycle Delay */
> -#define AT91_SDRAMC_TRP (0xf << 16) /* Row Precharge Delay */
> -#define AT91_SDRAMC_TRCD (0xf << 20) /* Row to Column Delay */
> -#define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */
> -#define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */
> +#define AT91_SDRAMC_TWR (0xF << 8) /* Number of Write Recovery Time Cycles */
> +#define AT91_SDRAMC_TWR_0 (0x0 << 8)
> +#define AT91_SDRAMC_TWR_1 (0x1 << 8)
> +#define AT91_SDRAMC_TWR_2 (0x2 << 8)
> +#define AT91_SDRAMC_TWR_3 (0x3 << 8)
> +#define AT91_SDRAMC_TWR_4 (0x4 << 8)
> +#define AT91_SDRAMC_TWR_5 (0x5 << 8)
> +#define AT91_SDRAMC_TWR_6 (0x6 << 8)
> +#define AT91_SDRAMC_TWR_7 (0x7 << 8)
> +#define AT91_SDRAMC_TWR_8 (0x8 << 8)
> +#define AT91_SDRAMC_TWR_9 (0x9 << 8)
> +#define AT91_SDRAMC_TWR_10 (0xA << 8)
> +#define AT91_SDRAMC_TWR_11 (0xB << 8)
> +#define AT91_SDRAMC_TWR_12 (0xC << 8)
> +#define AT91_SDRAMC_TWR_13 (0xD << 8)
> +#define AT91_SDRAMC_TWR_14 (0xE << 8)
> +#define AT91_SDRAMC_TWR_15 (0xF << 8)
> +#define AT91_SDRAMC_TRC (0xF << 12) /* Number of Row Cycle Delay Time Cycles */
> +#define AT91_SDRAMC_TRC_0 (0x0 << 12)
> +#define AT91_SDRAMC_TRC_1 (0x1 << 12)
> +#define AT91_SDRAMC_TRC_2 (0x2 << 12)
> +#define AT91_SDRAMC_TRC_3 (0x3 << 12)
> +#define AT91_SDRAMC_TRC_4 (0x4 << 12)
> +#define AT91_SDRAMC_TRC_5 (0x5 << 12)
> +#define AT91_SDRAMC_TRC_6 (0x6 << 12)
> +#define AT91_SDRAMC_TRC_7 (0x7 << 12)
> +#define AT91_SDRAMC_TRC_8 (0x8 << 12)
> +#define AT91_SDRAMC_TRC_9 (0x9 << 12)
> +#define AT91_SDRAMC_TRC_10 (0xA << 12)
> +#define AT91_SDRAMC_TRC_11 (0xB << 12)
> +#define AT91_SDRAMC_TRC_12 (0xC << 12)
> +#define AT91_SDRAMC_TRC_13 (0xD << 12)
> +#define AT91_SDRAMC_TRC_14 (0xE << 12)
> +#define AT91_SDRAMC_TRC_15 (0xF << 12)
> +#define AT91_SDRAMC_TRP (0xF << 16) /* Number of Row Precharge Delay Time Cycles */
> +#define AT91_SDRAMC_TRP_0 (0x0 << 16)
> +#define AT91_SDRAMC_TRP_1 (0x1 << 16)
> +#define AT91_SDRAMC_TRP_2 (0x2 << 16)
> +#define AT91_SDRAMC_TRP_3 (0x3 << 16)
> +#define AT91_SDRAMC_TRP_4 (0x4 << 16)
> +#define AT91_SDRAMC_TRP_5 (0x5 << 16)
> +#define AT91_SDRAMC_TRP_6 (0x6 << 16)
> +#define AT91_SDRAMC_TRP_7 (0x7 << 16)
> +#define AT91_SDRAMC_TRP_8 (0x8 << 16)
> +#define AT91_SDRAMC_TRP_9 (0x9 << 16)
> +#define AT91_SDRAMC_TRP_10 (0xA << 16)
> +#define AT91_SDRAMC_TRP_11 (0xB << 16)
> +#define AT91_SDRAMC_TRP_12 (0xC << 16)
> +#define AT91_SDRAMC_TRP_13 (0xD << 16)
> +#define AT91_SDRAMC_TRP_14 (0xE << 16)
> +#define AT91_SDRAMC_TRP_15 (0xF << 16)
> +#define AT91_SDRAMC_TRCD (0xF << 20) /* Number of Row to Column Delay Time Cycles */
> +#define AT91_SDRAMC_TRCD_0 (0x0 << 20)
> +#define AT91_SDRAMC_TRCD_1 (0x1 << 20)
> +#define AT91_SDRAMC_TRCD_2 (0x2 << 20)
> +#define AT91_SDRAMC_TRCD_3 (0x3 << 20)
> +#define AT91_SDRAMC_TRCD_4 (0x4 << 20)
> +#define AT91_SDRAMC_TRCD_5 (0x5 << 20)
> +#define AT91_SDRAMC_TRCD_6 (0x6 << 20)
> +#define AT91_SDRAMC_TRCD_7 (0x7 << 20)
> +#define AT91_SDRAMC_TRCD_8 (0x8 << 20)
> +#define AT91_SDRAMC_TRCD_9 (0x9 << 20)
> +#define AT91_SDRAMC_TRCD_10 (0xA << 20)
> +#define AT91_SDRAMC_TRCD_11 (0xB << 20)
> +#define AT91_SDRAMC_TRCD_12 (0xC << 20)
> +#define AT91_SDRAMC_TRCD_13 (0xD << 20)
> +#define AT91_SDRAMC_TRCD_14 (0xE << 20)
> +#define AT91_SDRAMC_TRCD_15 (0xF << 20)
> +#define AT91_SDRAMC_TRAS (0xF << 24) /* Number of Active to Precharge Delay Time Cycles */
> +#define AT91_SDRAMC_TRAS_0 (0x0 << 24)
> +#define AT91_SDRAMC_TRAS_1 (0x1 << 24)
> +#define AT91_SDRAMC_TRAS_2 (0x2 << 24)
> +#define AT91_SDRAMC_TRAS_3 (0x3 << 24)
> +#define AT91_SDRAMC_TRAS_4 (0x4 << 24)
> +#define AT91_SDRAMC_TRAS_5 (0x5 << 24)
> +#define AT91_SDRAMC_TRAS_6 (0x6 << 24)
> +#define AT91_SDRAMC_TRAS_7 (0x7 << 24)
> +#define AT91_SDRAMC_TRAS_8 (0x8 << 24)
> +#define AT91_SDRAMC_TRAS_9 (0x9 << 24)
> +#define AT91_SDRAMC_TRAS_10 (0xA << 24)
> +#define AT91_SDRAMC_TRAS_11 (0xB << 24)
> +#define AT91_SDRAMC_TRAS_12 (0xC << 24)
> +#define AT91_SDRAMC_TRAS_13 (0xD << 24)
> +#define AT91_SDRAMC_TRAS_14 (0xE << 24)
> +#define AT91_SDRAMC_TRAS_15 (0xF << 24)
> +#define AT91_SDRAMC_TXS (0xF << 28) /* Number of Exit Self Refresh to Active Delay Time Cycles */
> +#define AT91_SDRAMC_TXSR_0 (0x0 << 28)
> +#define AT91_SDRAMC_TXSR_1 (0x1 << 28)
> +#define AT91_SDRAMC_TXSR_2 (0x2 << 28)
> +#define AT91_SDRAMC_TXSR_3 (0x3 << 28)
> +#define AT91_SDRAMC_TXSR_4 (0x4 << 28)
> +#define AT91_SDRAMC_TXSR_5 (0x5 << 28)
> +#define AT91_SDRAMC_TXSR_6 (0x6 << 28)
> +#define AT91_SDRAMC_TXSR_7 (0x7 << 28)
> +#define AT91_SDRAMC_TXSR_8 (0x8 << 28)
> +#define AT91_SDRAMC_TXSR_9 (0x9 << 28)
> +#define AT91_SDRAMC_TXSR_10 (0xA << 28)
> +#define AT91_SDRAMC_TXSR_11 (0xB << 28)
> +#define AT91_SDRAMC_TXSR_12 (0xC << 28)
> +#define AT91_SDRAMC_TXSR_13 (0xD << 28)
> +#define AT91_SDRAMC_TXSR_14 (0xE << 28)
> +#define AT91_SDRAMC_TXSR_15 (0xF << 28)
>
> #define AT91_SDRAMC_LPR 0x10 /* SDRAM Controller Low Power Register */
> #define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v2 08/11] ARM: at91: Add lowlevel helpers for at91sam9263
2022-06-28 20:38 [PATCH 0/11] ARM: at91: Add pbl support to skov-arm9cpu Sam Ravnborg
` (6 preceding siblings ...)
2022-06-28 20:38 ` [PATCH v2 07/11] ARM: at91: Add extra register definitions Sam Ravnborg
@ 2022-06-28 20:38 ` Sam Ravnborg
2022-06-29 6:50 ` Ahmad Fatoum
2022-06-28 20:38 ` [WIP PATCH v2 09/11] atmel_lcdfb: add support for updated DT bindings Sam Ravnborg
` (3 subsequent siblings)
11 siblings, 1 reply; 21+ messages in thread
From: Sam Ravnborg @ 2022-06-28 20:38 UTC (permalink / raw)
To: barebox, Ahmad Fatoum; +Cc: Sam Ravnborg
Add lowlevel helpers like we already have for sama5d2 etc.
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
---
arch/arm/mach-at91/Makefile | 1 +
arch/arm/mach-at91/include/mach/sam92_ll.h | 54 ++++++
arch/arm/mach-at91/sam9263_ll.c | 215 +++++++++++++++++++++
3 files changed, 270 insertions(+)
create mode 100644 arch/arm/mach-at91/include/mach/sam92_ll.h
create mode 100644 arch/arm/mach-at91/sam9263_ll.c
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index b171d682f..390d49d03 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -31,6 +31,7 @@ ifeq ($(CONFIG_OFDEVICE),)
obj-$(CONFIG_SOC_AT91SAM9263) += at91sam9263.o at91sam9263_devices.o
obj-$(CONFIG_SOC_SAMA5D3) += sama5d3.o sama5d3_devices.o
endif
+lwl-$(CONFIG_SOC_AT91SAM9263) += sam9263_ll.o
lwl-$(CONFIG_SOC_SAMA5D2) += sama5d2_ll.o
obj-$(CONFIG_SOC_SAMA5D2) += sama5d2.o
lwl-$(CONFIG_SOC_SAMA5D3) += sama5d3_ll.o
diff --git a/arch/arm/mach-at91/include/mach/sam92_ll.h b/arch/arm/mach-at91/include/mach/sam92_ll.h
new file mode 100644
index 000000000..f5cef197d
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/sam92_ll.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __MACH_SAM92_LL_H__
+#define __MACH_SAM92_LL_H__
+
+#include <debug_ll.h>
+#include <common.h>
+
+#include <mach/at91_pmc_ll.h>
+#include <mach/at91sam9260.h>
+#include <mach/at91sam9261.h>
+#include <mach/at91sam9263.h>
+#include <mach/at91sam926x.h>
+#include <mach/debug_ll.h>
+#include <mach/early_udelay.h>
+#include <mach/iomux.h>
+
+struct sam92_pmc_config {
+ unsigned int diva;
+ unsigned int mula;
+};
+
+void sam9263_lowlevel_init(const struct sam92_pmc_config *config);
+
+static inline void sam92_pmc_enable_periph_clock(int clk)
+{
+ at91_pmc_enable_periph_clock(IOMEM(AT91SAM926X_BASE_PMC), clk);
+}
+
+/* requires relocation */
+static inline void sam92_udelay_init(unsigned int msc)
+{
+ early_udelay_init(IOMEM(AT91SAM926X_BASE_PMC), IOMEM(AT91SAM9263_BASE_PIT),
+ AT91SAM926X_ID_SYS, msc, 0);
+}
+
+static inline void sam92_dbgu_setup_ll(unsigned int mck)
+{
+ void __iomem *pio = IOMEM(AT91SAM9263_BASE_PIOC);
+
+ // Setup clock for pio
+ sam92_pmc_enable_periph_clock(AT91SAM9263_ID_PIOCDE);
+
+ // Setup DBGU uart
+ at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PC30), AT91_MUX_PERIPH_A, GPIO_PULL_UP); // DRXD
+ at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PC31), AT91_MUX_PERIPH_A, 0); // DTXD
+
+ // Setup dbgu
+ at91_dbgu_setup_ll(IOMEM(AT91_BASE_DBGU1), mck, CONFIG_BAUDRATE);
+ pbl_set_putc(at91_dbgu_putc, IOMEM(AT91_BASE_DBGU1));
+ putc_ll('#');
+}
+
+#endif
diff --git a/arch/arm/mach-at91/sam9263_ll.c b/arch/arm/mach-at91/sam9263_ll.c
new file mode 100644
index 000000000..ffde065f6
--- /dev/null
+++ b/arch/arm/mach-at91/sam9263_ll.c
@@ -0,0 +1,215 @@
+// SPDX-License-Identifier: GPL-2.0-only AND BSD-1-Clause
+// SPDX-FileCopyrightText: 2017, Microchip Corporation
+
+#include <mach/at91sam9263_matrix.h>
+#include <mach/barebox-arm.h>
+#include <mach/at91_rstc.h>
+#include <mach/at91_wdt.h>
+#include <mach/sam92_ll.h>
+
+static void sam9263_pmc_init(const struct sam92_pmc_config *config)
+{
+ at91_pmc_init(IOMEM(AT91SAM926X_BASE_PMC), 0);
+
+ /* Initialize PLL charge pump, must be done before PLLAR/PLLBR */
+ at91_pmc_init_pll(IOMEM(AT91SAM926X_BASE_PMC), AT91SAM9_PMC_ICPPLLA | AT91SAM9_PMC_ICPPLLB);
+
+ /* Setting PLL A and divider A */
+ at91_pmc_cfg_plla(IOMEM(AT91SAM926X_BASE_PMC),
+ AT91_PMC_MUL_(config->mula) |
+ AT91_PMC_OUT_2 | // 190 to 240 MHz
+ config->diva, // Divider
+ 0);
+
+ /* Selection of Master Clock and Processor Clock */
+
+ /* PCK = PLLA = 2 * MCK */
+ at91_pmc_cfg_mck(IOMEM(AT91SAM926X_BASE_PMC),
+ AT91_PMC_CSS_SLOW
+ | AT91_PMC_PRES_1
+ | AT91SAM9_PMC_MDIV_2
+ | AT91_PMC_PDIV_1,
+ 0);
+
+ /* Switch MCK on PLLA output */
+ at91_pmc_cfg_mck(IOMEM(AT91SAM926X_BASE_PMC),
+ AT91_PMC_CSS_PLLA
+ | AT91_PMC_PRES_1
+ | AT91SAM9_PMC_MDIV_2
+ | AT91_PMC_PDIV_1,
+ 0);
+}
+
+static inline void matrix_wr(unsigned int offset, const unsigned int value)
+{
+ writel(value, IOMEM(AT91SAM9263_BASE_MATRIX + offset));
+}
+
+static void sam9263_matrix_init(void)
+{
+ /* Bus Matrix Master Configuration Register */
+ matrix_wr(AT91SAM9263_MATRIX_MCFG0, AT91SAM9263_MATRIX_ULBT_SIXTEEN); /* OHCI */
+ matrix_wr(AT91SAM9263_MATRIX_MCFG1, AT91SAM9263_MATRIX_ULBT_EIGHT); /* ISI */
+ matrix_wr(AT91SAM9263_MATRIX_MCFG2, AT91SAM9263_MATRIX_ULBT_EIGHT); /* 2D */
+ matrix_wr(AT91SAM9263_MATRIX_MCFG3, AT91SAM9263_MATRIX_ULBT_EIGHT); /* DMAC */
+ matrix_wr(AT91SAM9263_MATRIX_MCFG4, AT91SAM9263_MATRIX_ULBT_FOUR); /* MACB */
+ matrix_wr(AT91SAM9263_MATRIX_MCFG5, AT91SAM9263_MATRIX_ULBT_SIXTEEN); /* LCDC */
+ matrix_wr(AT91SAM9263_MATRIX_MCFG6, AT91SAM9263_MATRIX_ULBT_SINGLE); /* PDC */
+ matrix_wr(AT91SAM9263_MATRIX_MCFG7, AT91SAM9263_MATRIX_ULBT_EIGHT); /* DBUS */
+ matrix_wr(AT91SAM9263_MATRIX_MCFG8, AT91SAM9263_MATRIX_ULBT_EIGHT); /* IBUS */
+
+ /* Bus Matrix Slave Configuration Registers */
+
+ /* ROM */
+ matrix_wr(AT91SAM9263_MATRIX_SCFG0,
+ AT91SAM9263_MATRIX_ARBT_FIXED_PRIORITY
+ | AT91SAM9263_MATRIX_FIXED_DEFMSTR_ARM926I
+ | AT91SAM9263_MATRIX_DEFMSTR_TYPE_LAST
+ | AT91SAM9263_MATRIX_SLOT_CYCLE_(32));
+
+ /* RAM80K */
+ matrix_wr(AT91SAM9263_MATRIX_SCFG1,
+ AT91SAM9263_MATRIX_ARBT_FIXED_PRIORITY
+ | AT91SAM9263_MATRIX_FIXED_DEFMSTR_EMAC
+ | AT91SAM9263_MATRIX_DEFMSTR_TYPE_LAST
+ | AT91SAM9263_MATRIX_SLOT_CYCLE_(32));
+
+ /* RAM16K */
+ matrix_wr(AT91SAM9263_MATRIX_SCFG2,
+ AT91SAM9263_MATRIX_ARBT_FIXED_PRIORITY
+ | AT91SAM9263_MATRIX_FIXED_DEFMSTR_USB
+ | AT91SAM9263_MATRIX_DEFMSTR_TYPE_LAST
+ | AT91SAM9263_MATRIX_SLOT_CYCLE_(16));
+
+ /* PERIPHERALS */
+ matrix_wr(AT91SAM9263_MATRIX_SCFG3,
+ AT91SAM9263_MATRIX_ARBT_FIXED_PRIORITY
+ | AT91SAM9263_MATRIX_FIXED_DEFMSTR_PDC
+ | AT91SAM9263_MATRIX_DEFMSTR_TYPE_LAST
+ | AT91SAM9263_MATRIX_SLOT_CYCLE_(4));
+
+ /* EBI0 */
+ matrix_wr(AT91SAM9263_MATRIX_SCFG4,
+ AT91SAM9263_MATRIX_ARBT_ROUND_ROBIN
+ | AT91SAM9263_MATRIX_FIXED_DEFMSTR_ARM926I
+ | AT91SAM9263_MATRIX_DEFMSTR_TYPE_LAST
+ | AT91SAM9263_MATRIX_SLOT_CYCLE_(32));
+
+ /* EBI1 */
+ matrix_wr(AT91SAM9263_MATRIX_SCFG5,
+ AT91SAM9263_MATRIX_ARBT_FIXED_PRIORITY
+ | AT91SAM9263_MATRIX_FIXED_DEFMSTR_LCDC
+ | AT91SAM9263_MATRIX_DEFMSTR_TYPE_LAST
+ | AT91SAM9263_MATRIX_SLOT_CYCLE_(64));
+
+ /* APB */
+ matrix_wr(AT91SAM9263_MATRIX_SCFG6,
+ AT91SAM9263_MATRIX_ARBT_FIXED_PRIORITY
+ | AT91SAM9263_MATRIX_FIXED_DEFMSTR_ARM926D
+ | AT91SAM9263_MATRIX_DEFMSTR_TYPE_LAST
+ | AT91SAM9263_MATRIX_SLOT_CYCLE_(4));
+
+ /* ROM */
+ matrix_wr(AT91SAM9263_MATRIX_PRAS0,
+ AT91SAM9263_MATRIX_M0PR_(1)
+ | AT91SAM9263_MATRIX_M1PR_(0)
+ | AT91SAM9263_MATRIX_M2PR_(2)
+ | AT91SAM9263_MATRIX_M3PR_(1)
+ | AT91SAM9263_MATRIX_M4PR_(0)
+ | AT91SAM9263_MATRIX_M5PR_(3)
+ | AT91SAM9263_MATRIX_M6PR_(2)
+ | AT91SAM9263_MATRIX_M7PR_(3));
+
+ matrix_wr(AT91SAM9263_MATRIX_PRBS0, AT91SAM9263_MATRIX_M8PR_(0));
+
+ /* RAM80K */
+ matrix_wr(AT91SAM9263_MATRIX_PRAS1,
+ AT91SAM9263_MATRIX_M0PR_(1)
+ | AT91SAM9263_MATRIX_M1PR_(2)
+ | AT91SAM9263_MATRIX_M2PR_(1)
+ | AT91SAM9263_MATRIX_M3PR_(3)
+ | AT91SAM9263_MATRIX_M4PR_(0)
+ | AT91SAM9263_MATRIX_M5PR_(0)
+ | AT91SAM9263_MATRIX_M6PR_(3)
+ | AT91SAM9263_MATRIX_M7PR_(0));
+
+ matrix_wr(AT91SAM9263_MATRIX_PRBS1, AT91SAM9263_MATRIX_M8PR_(2));
+
+ /* RAM16K */
+ matrix_wr(AT91SAM9263_MATRIX_PRAS2,
+ AT91SAM9263_MATRIX_M0PR_(1)
+ | AT91SAM9263_MATRIX_M1PR_(0)
+ | AT91SAM9263_MATRIX_M2PR_(2)
+ | AT91SAM9263_MATRIX_M3PR_(1)
+ | AT91SAM9263_MATRIX_M4PR_(0)
+ | AT91SAM9263_MATRIX_M5PR_(3)
+ | AT91SAM9263_MATRIX_M6PR_(3)
+ | AT91SAM9263_MATRIX_M7PR_(2));
+
+ matrix_wr(AT91SAM9263_MATRIX_PRBS2, AT91SAM9263_MATRIX_M8PR_(0));
+
+ /* PERIPHERALS */
+ matrix_wr(AT91SAM9263_MATRIX_PRAS3,
+ AT91SAM9263_MATRIX_M0PR_(0)
+ | AT91SAM9263_MATRIX_M1PR_(1)
+ | AT91SAM9263_MATRIX_M2PR_(0)
+ | AT91SAM9263_MATRIX_M3PR_(2)
+ | AT91SAM9263_MATRIX_M4PR_(1)
+ | AT91SAM9263_MATRIX_M5PR_(0)
+ | AT91SAM9263_MATRIX_M6PR_(3)
+ | AT91SAM9263_MATRIX_M7PR_(2));
+
+ matrix_wr(AT91SAM9263_MATRIX_PRBS3, AT91SAM9263_MATRIX_M8PR_(3));
+
+ /* EBI0 */
+ matrix_wr(AT91SAM9263_MATRIX_PRAS4,
+ AT91SAM9263_MATRIX_M0PR_(1)
+ | AT91SAM9263_MATRIX_M1PR_(3)
+ | AT91SAM9263_MATRIX_M2PR_(0)
+ | AT91SAM9263_MATRIX_M3PR_(2)
+ | AT91SAM9263_MATRIX_M4PR_(3)
+ | AT91SAM9263_MATRIX_M5PR_(0)
+ | AT91SAM9263_MATRIX_M6PR_(0)
+ | AT91SAM9263_MATRIX_M7PR_(1));
+
+ matrix_wr(AT91SAM9263_MATRIX_PRBS4, AT91SAM9263_MATRIX_M8PR_(2));
+
+ /* EBI1 */
+ matrix_wr(AT91SAM9263_MATRIX_PRAS5,
+ AT91SAM9263_MATRIX_M0PR_(0)
+ | AT91SAM9263_MATRIX_M1PR_(1)
+ | AT91SAM9263_MATRIX_M2PR_(0)
+ | AT91SAM9263_MATRIX_M3PR_(0)
+ | AT91SAM9263_MATRIX_M4PR_(3)
+ | AT91SAM9263_MATRIX_M5PR_(2)
+ | AT91SAM9263_MATRIX_M6PR_(3)
+ | AT91SAM9263_MATRIX_M7PR_(2));
+
+ matrix_wr(AT91SAM9263_MATRIX_PRBS5, AT91SAM9263_MATRIX_M8PR_(1));
+
+ /* APB */
+ matrix_wr(AT91SAM9263_MATRIX_PRAS6,
+ AT91SAM9263_MATRIX_M0PR_(1)
+ | AT91SAM9263_MATRIX_M1PR_(0)
+ | AT91SAM9263_MATRIX_M2PR_(2)
+ | AT91SAM9263_MATRIX_M3PR_(1)
+ | AT91SAM9263_MATRIX_M4PR_(0)
+ | AT91SAM9263_MATRIX_M5PR_(0)
+ | AT91SAM9263_MATRIX_M6PR_(3)
+ | AT91SAM9263_MATRIX_M7PR_(3));
+
+ matrix_wr(AT91SAM9263_MATRIX_PRBS6, AT91SAM9263_MATRIX_M8PR_(2));
+}
+
+static void sam9263_rstc_init(void)
+{
+ writel(AT91_RSTC_KEY | AT91_RSTC_URSTEN, IOMEM(AT91SAM926X_BASE_RSTC + AT91_RSTC_MR));
+}
+
+void sam9263_lowlevel_init(const struct sam92_pmc_config *config)
+{
+ at91_wdt_disable(IOMEM(AT91SAM9263_BASE_WDT));
+ sam9263_pmc_init(config);
+ sam9263_matrix_init();
+ sam9263_rstc_init();
+}
--
2.34.1
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [PATCH v2 08/11] ARM: at91: Add lowlevel helpers for at91sam9263
2022-06-28 20:38 ` [PATCH v2 08/11] ARM: at91: Add lowlevel helpers for at91sam9263 Sam Ravnborg
@ 2022-06-29 6:50 ` Ahmad Fatoum
0 siblings, 0 replies; 21+ messages in thread
From: Ahmad Fatoum @ 2022-06-29 6:50 UTC (permalink / raw)
To: Sam Ravnborg, barebox
On 28.06.22 22:38, Sam Ravnborg wrote:
> Add lowlevel helpers like we already have for sama5d2 etc.
Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
>
> Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
> ---
> arch/arm/mach-at91/Makefile | 1 +
> arch/arm/mach-at91/include/mach/sam92_ll.h | 54 ++++++
> arch/arm/mach-at91/sam9263_ll.c | 215 +++++++++++++++++++++
> 3 files changed, 270 insertions(+)
> create mode 100644 arch/arm/mach-at91/include/mach/sam92_ll.h
> create mode 100644 arch/arm/mach-at91/sam9263_ll.c
>
> diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
> index b171d682f..390d49d03 100644
> --- a/arch/arm/mach-at91/Makefile
> +++ b/arch/arm/mach-at91/Makefile
> @@ -31,6 +31,7 @@ ifeq ($(CONFIG_OFDEVICE),)
> obj-$(CONFIG_SOC_AT91SAM9263) += at91sam9263.o at91sam9263_devices.o
> obj-$(CONFIG_SOC_SAMA5D3) += sama5d3.o sama5d3_devices.o
> endif
> +lwl-$(CONFIG_SOC_AT91SAM9263) += sam9263_ll.o
> lwl-$(CONFIG_SOC_SAMA5D2) += sama5d2_ll.o
> obj-$(CONFIG_SOC_SAMA5D2) += sama5d2.o
> lwl-$(CONFIG_SOC_SAMA5D3) += sama5d3_ll.o
> diff --git a/arch/arm/mach-at91/include/mach/sam92_ll.h b/arch/arm/mach-at91/include/mach/sam92_ll.h
> new file mode 100644
> index 000000000..f5cef197d
> --- /dev/null
> +++ b/arch/arm/mach-at91/include/mach/sam92_ll.h
> @@ -0,0 +1,54 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +
> +#ifndef __MACH_SAM92_LL_H__
> +#define __MACH_SAM92_LL_H__
> +
> +#include <debug_ll.h>
> +#include <common.h>
> +
> +#include <mach/at91_pmc_ll.h>
> +#include <mach/at91sam9260.h>
> +#include <mach/at91sam9261.h>
> +#include <mach/at91sam9263.h>
> +#include <mach/at91sam926x.h>
> +#include <mach/debug_ll.h>
> +#include <mach/early_udelay.h>
> +#include <mach/iomux.h>
> +
> +struct sam92_pmc_config {
> + unsigned int diva;
> + unsigned int mula;
> +};
> +
> +void sam9263_lowlevel_init(const struct sam92_pmc_config *config);
> +
> +static inline void sam92_pmc_enable_periph_clock(int clk)
> +{
> + at91_pmc_enable_periph_clock(IOMEM(AT91SAM926X_BASE_PMC), clk);
> +}
> +
> +/* requires relocation */
> +static inline void sam92_udelay_init(unsigned int msc)
> +{
> + early_udelay_init(IOMEM(AT91SAM926X_BASE_PMC), IOMEM(AT91SAM9263_BASE_PIT),
> + AT91SAM926X_ID_SYS, msc, 0);
> +}
> +
> +static inline void sam92_dbgu_setup_ll(unsigned int mck)
> +{
> + void __iomem *pio = IOMEM(AT91SAM9263_BASE_PIOC);
> +
> + // Setup clock for pio
> + sam92_pmc_enable_periph_clock(AT91SAM9263_ID_PIOCDE);
> +
> + // Setup DBGU uart
> + at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PC30), AT91_MUX_PERIPH_A, GPIO_PULL_UP); // DRXD
> + at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PC31), AT91_MUX_PERIPH_A, 0); // DTXD
> +
> + // Setup dbgu
> + at91_dbgu_setup_ll(IOMEM(AT91_BASE_DBGU1), mck, CONFIG_BAUDRATE);
> + pbl_set_putc(at91_dbgu_putc, IOMEM(AT91_BASE_DBGU1));
> + putc_ll('#');
> +}
> +
> +#endif
> diff --git a/arch/arm/mach-at91/sam9263_ll.c b/arch/arm/mach-at91/sam9263_ll.c
> new file mode 100644
> index 000000000..ffde065f6
> --- /dev/null
> +++ b/arch/arm/mach-at91/sam9263_ll.c
> @@ -0,0 +1,215 @@
> +// SPDX-License-Identifier: GPL-2.0-only AND BSD-1-Clause
> +// SPDX-FileCopyrightText: 2017, Microchip Corporation
> +
> +#include <mach/at91sam9263_matrix.h>
> +#include <mach/barebox-arm.h>
> +#include <mach/at91_rstc.h>
> +#include <mach/at91_wdt.h>
> +#include <mach/sam92_ll.h>
> +
> +static void sam9263_pmc_init(const struct sam92_pmc_config *config)
> +{
> + at91_pmc_init(IOMEM(AT91SAM926X_BASE_PMC), 0);
> +
> + /* Initialize PLL charge pump, must be done before PLLAR/PLLBR */
> + at91_pmc_init_pll(IOMEM(AT91SAM926X_BASE_PMC), AT91SAM9_PMC_ICPPLLA | AT91SAM9_PMC_ICPPLLB);
> +
> + /* Setting PLL A and divider A */
> + at91_pmc_cfg_plla(IOMEM(AT91SAM926X_BASE_PMC),
> + AT91_PMC_MUL_(config->mula) |
> + AT91_PMC_OUT_2 | // 190 to 240 MHz
> + config->diva, // Divider
> + 0);
> +
> + /* Selection of Master Clock and Processor Clock */
> +
> + /* PCK = PLLA = 2 * MCK */
> + at91_pmc_cfg_mck(IOMEM(AT91SAM926X_BASE_PMC),
> + AT91_PMC_CSS_SLOW
> + | AT91_PMC_PRES_1
> + | AT91SAM9_PMC_MDIV_2
> + | AT91_PMC_PDIV_1,
> + 0);
> +
> + /* Switch MCK on PLLA output */
> + at91_pmc_cfg_mck(IOMEM(AT91SAM926X_BASE_PMC),
> + AT91_PMC_CSS_PLLA
> + | AT91_PMC_PRES_1
> + | AT91SAM9_PMC_MDIV_2
> + | AT91_PMC_PDIV_1,
> + 0);
> +}
> +
> +static inline void matrix_wr(unsigned int offset, const unsigned int value)
> +{
> + writel(value, IOMEM(AT91SAM9263_BASE_MATRIX + offset));
> +}
> +
> +static void sam9263_matrix_init(void)
> +{
> + /* Bus Matrix Master Configuration Register */
> + matrix_wr(AT91SAM9263_MATRIX_MCFG0, AT91SAM9263_MATRIX_ULBT_SIXTEEN); /* OHCI */
> + matrix_wr(AT91SAM9263_MATRIX_MCFG1, AT91SAM9263_MATRIX_ULBT_EIGHT); /* ISI */
> + matrix_wr(AT91SAM9263_MATRIX_MCFG2, AT91SAM9263_MATRIX_ULBT_EIGHT); /* 2D */
> + matrix_wr(AT91SAM9263_MATRIX_MCFG3, AT91SAM9263_MATRIX_ULBT_EIGHT); /* DMAC */
> + matrix_wr(AT91SAM9263_MATRIX_MCFG4, AT91SAM9263_MATRIX_ULBT_FOUR); /* MACB */
> + matrix_wr(AT91SAM9263_MATRIX_MCFG5, AT91SAM9263_MATRIX_ULBT_SIXTEEN); /* LCDC */
> + matrix_wr(AT91SAM9263_MATRIX_MCFG6, AT91SAM9263_MATRIX_ULBT_SINGLE); /* PDC */
> + matrix_wr(AT91SAM9263_MATRIX_MCFG7, AT91SAM9263_MATRIX_ULBT_EIGHT); /* DBUS */
> + matrix_wr(AT91SAM9263_MATRIX_MCFG8, AT91SAM9263_MATRIX_ULBT_EIGHT); /* IBUS */
> +
> + /* Bus Matrix Slave Configuration Registers */
> +
> + /* ROM */
> + matrix_wr(AT91SAM9263_MATRIX_SCFG0,
> + AT91SAM9263_MATRIX_ARBT_FIXED_PRIORITY
> + | AT91SAM9263_MATRIX_FIXED_DEFMSTR_ARM926I
> + | AT91SAM9263_MATRIX_DEFMSTR_TYPE_LAST
> + | AT91SAM9263_MATRIX_SLOT_CYCLE_(32));
> +
> + /* RAM80K */
> + matrix_wr(AT91SAM9263_MATRIX_SCFG1,
> + AT91SAM9263_MATRIX_ARBT_FIXED_PRIORITY
> + | AT91SAM9263_MATRIX_FIXED_DEFMSTR_EMAC
> + | AT91SAM9263_MATRIX_DEFMSTR_TYPE_LAST
> + | AT91SAM9263_MATRIX_SLOT_CYCLE_(32));
> +
> + /* RAM16K */
> + matrix_wr(AT91SAM9263_MATRIX_SCFG2,
> + AT91SAM9263_MATRIX_ARBT_FIXED_PRIORITY
> + | AT91SAM9263_MATRIX_FIXED_DEFMSTR_USB
> + | AT91SAM9263_MATRIX_DEFMSTR_TYPE_LAST
> + | AT91SAM9263_MATRIX_SLOT_CYCLE_(16));
> +
> + /* PERIPHERALS */
> + matrix_wr(AT91SAM9263_MATRIX_SCFG3,
> + AT91SAM9263_MATRIX_ARBT_FIXED_PRIORITY
> + | AT91SAM9263_MATRIX_FIXED_DEFMSTR_PDC
> + | AT91SAM9263_MATRIX_DEFMSTR_TYPE_LAST
> + | AT91SAM9263_MATRIX_SLOT_CYCLE_(4));
> +
> + /* EBI0 */
> + matrix_wr(AT91SAM9263_MATRIX_SCFG4,
> + AT91SAM9263_MATRIX_ARBT_ROUND_ROBIN
> + | AT91SAM9263_MATRIX_FIXED_DEFMSTR_ARM926I
> + | AT91SAM9263_MATRIX_DEFMSTR_TYPE_LAST
> + | AT91SAM9263_MATRIX_SLOT_CYCLE_(32));
> +
> + /* EBI1 */
> + matrix_wr(AT91SAM9263_MATRIX_SCFG5,
> + AT91SAM9263_MATRIX_ARBT_FIXED_PRIORITY
> + | AT91SAM9263_MATRIX_FIXED_DEFMSTR_LCDC
> + | AT91SAM9263_MATRIX_DEFMSTR_TYPE_LAST
> + | AT91SAM9263_MATRIX_SLOT_CYCLE_(64));
> +
> + /* APB */
> + matrix_wr(AT91SAM9263_MATRIX_SCFG6,
> + AT91SAM9263_MATRIX_ARBT_FIXED_PRIORITY
> + | AT91SAM9263_MATRIX_FIXED_DEFMSTR_ARM926D
> + | AT91SAM9263_MATRIX_DEFMSTR_TYPE_LAST
> + | AT91SAM9263_MATRIX_SLOT_CYCLE_(4));
> +
> + /* ROM */
> + matrix_wr(AT91SAM9263_MATRIX_PRAS0,
> + AT91SAM9263_MATRIX_M0PR_(1)
> + | AT91SAM9263_MATRIX_M1PR_(0)
> + | AT91SAM9263_MATRIX_M2PR_(2)
> + | AT91SAM9263_MATRIX_M3PR_(1)
> + | AT91SAM9263_MATRIX_M4PR_(0)
> + | AT91SAM9263_MATRIX_M5PR_(3)
> + | AT91SAM9263_MATRIX_M6PR_(2)
> + | AT91SAM9263_MATRIX_M7PR_(3));
> +
> + matrix_wr(AT91SAM9263_MATRIX_PRBS0, AT91SAM9263_MATRIX_M8PR_(0));
> +
> + /* RAM80K */
> + matrix_wr(AT91SAM9263_MATRIX_PRAS1,
> + AT91SAM9263_MATRIX_M0PR_(1)
> + | AT91SAM9263_MATRIX_M1PR_(2)
> + | AT91SAM9263_MATRIX_M2PR_(1)
> + | AT91SAM9263_MATRIX_M3PR_(3)
> + | AT91SAM9263_MATRIX_M4PR_(0)
> + | AT91SAM9263_MATRIX_M5PR_(0)
> + | AT91SAM9263_MATRIX_M6PR_(3)
> + | AT91SAM9263_MATRIX_M7PR_(0));
> +
> + matrix_wr(AT91SAM9263_MATRIX_PRBS1, AT91SAM9263_MATRIX_M8PR_(2));
> +
> + /* RAM16K */
> + matrix_wr(AT91SAM9263_MATRIX_PRAS2,
> + AT91SAM9263_MATRIX_M0PR_(1)
> + | AT91SAM9263_MATRIX_M1PR_(0)
> + | AT91SAM9263_MATRIX_M2PR_(2)
> + | AT91SAM9263_MATRIX_M3PR_(1)
> + | AT91SAM9263_MATRIX_M4PR_(0)
> + | AT91SAM9263_MATRIX_M5PR_(3)
> + | AT91SAM9263_MATRIX_M6PR_(3)
> + | AT91SAM9263_MATRIX_M7PR_(2));
> +
> + matrix_wr(AT91SAM9263_MATRIX_PRBS2, AT91SAM9263_MATRIX_M8PR_(0));
> +
> + /* PERIPHERALS */
> + matrix_wr(AT91SAM9263_MATRIX_PRAS3,
> + AT91SAM9263_MATRIX_M0PR_(0)
> + | AT91SAM9263_MATRIX_M1PR_(1)
> + | AT91SAM9263_MATRIX_M2PR_(0)
> + | AT91SAM9263_MATRIX_M3PR_(2)
> + | AT91SAM9263_MATRIX_M4PR_(1)
> + | AT91SAM9263_MATRIX_M5PR_(0)
> + | AT91SAM9263_MATRIX_M6PR_(3)
> + | AT91SAM9263_MATRIX_M7PR_(2));
> +
> + matrix_wr(AT91SAM9263_MATRIX_PRBS3, AT91SAM9263_MATRIX_M8PR_(3));
> +
> + /* EBI0 */
> + matrix_wr(AT91SAM9263_MATRIX_PRAS4,
> + AT91SAM9263_MATRIX_M0PR_(1)
> + | AT91SAM9263_MATRIX_M1PR_(3)
> + | AT91SAM9263_MATRIX_M2PR_(0)
> + | AT91SAM9263_MATRIX_M3PR_(2)
> + | AT91SAM9263_MATRIX_M4PR_(3)
> + | AT91SAM9263_MATRIX_M5PR_(0)
> + | AT91SAM9263_MATRIX_M6PR_(0)
> + | AT91SAM9263_MATRIX_M7PR_(1));
> +
> + matrix_wr(AT91SAM9263_MATRIX_PRBS4, AT91SAM9263_MATRIX_M8PR_(2));
> +
> + /* EBI1 */
> + matrix_wr(AT91SAM9263_MATRIX_PRAS5,
> + AT91SAM9263_MATRIX_M0PR_(0)
> + | AT91SAM9263_MATRIX_M1PR_(1)
> + | AT91SAM9263_MATRIX_M2PR_(0)
> + | AT91SAM9263_MATRIX_M3PR_(0)
> + | AT91SAM9263_MATRIX_M4PR_(3)
> + | AT91SAM9263_MATRIX_M5PR_(2)
> + | AT91SAM9263_MATRIX_M6PR_(3)
> + | AT91SAM9263_MATRIX_M7PR_(2));
> +
> + matrix_wr(AT91SAM9263_MATRIX_PRBS5, AT91SAM9263_MATRIX_M8PR_(1));
> +
> + /* APB */
> + matrix_wr(AT91SAM9263_MATRIX_PRAS6,
> + AT91SAM9263_MATRIX_M0PR_(1)
> + | AT91SAM9263_MATRIX_M1PR_(0)
> + | AT91SAM9263_MATRIX_M2PR_(2)
> + | AT91SAM9263_MATRIX_M3PR_(1)
> + | AT91SAM9263_MATRIX_M4PR_(0)
> + | AT91SAM9263_MATRIX_M5PR_(0)
> + | AT91SAM9263_MATRIX_M6PR_(3)
> + | AT91SAM9263_MATRIX_M7PR_(3));
> +
> + matrix_wr(AT91SAM9263_MATRIX_PRBS6, AT91SAM9263_MATRIX_M8PR_(2));
> +}
> +
> +static void sam9263_rstc_init(void)
> +{
> + writel(AT91_RSTC_KEY | AT91_RSTC_URSTEN, IOMEM(AT91SAM926X_BASE_RSTC + AT91_RSTC_MR));
> +}
> +
> +void sam9263_lowlevel_init(const struct sam92_pmc_config *config)
> +{
> + at91_wdt_disable(IOMEM(AT91SAM9263_BASE_WDT));
> + sam9263_pmc_init(config);
> + sam9263_matrix_init();
> + sam9263_rstc_init();
> +}
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 21+ messages in thread
* [WIP PATCH v2 09/11] atmel_lcdfb: add support for updated DT bindings
2022-06-28 20:38 [PATCH 0/11] ARM: at91: Add pbl support to skov-arm9cpu Sam Ravnborg
` (7 preceding siblings ...)
2022-06-28 20:38 ` [PATCH v2 08/11] ARM: at91: Add lowlevel helpers for at91sam9263 Sam Ravnborg
@ 2022-06-28 20:38 ` Sam Ravnborg
2022-06-28 20:38 ` [PATCH v2 10/11] ARM: at91: Add xload support to skov-arm9cpu Sam Ravnborg
` (2 subsequent siblings)
11 siblings, 0 replies; 21+ messages in thread
From: Sam Ravnborg @ 2022-06-28 20:38 UTC (permalink / raw)
To: barebox, Ahmad Fatoum; +Cc: Sam Ravnborg
The updated bindings for the display node uses graph nodes to
identify the panel.
Update the driver to support the new binding:
- Add support for the video pipeline (vpl)
- Add guard-time to the chip info
- Move deprecated display support to own function
With this update there is support for specifying a backlight node
as part of the panel node.
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
---
drivers/video/atmel_lcdfb.c | 6 ++
drivers/video/atmel_lcdfb.h | 4 +
drivers/video/atmel_lcdfb_core.c | 125 +++++++++++++++++++++++++------
3 files changed, 113 insertions(+), 22 deletions(-)
diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
index 38b4b8df3..1087102c4 100644
--- a/drivers/video/atmel_lcdfb.c
+++ b/drivers/video/atmel_lcdfb.c
@@ -231,26 +231,32 @@ static int atmel_lcdc_probe(struct device_d *dev)
static struct atmel_lcdfb_config at91sam9261_config = {
.have_hozval = true,
.have_intensity_bit = true,
+ .guard_time = 1,
};
static struct atmel_lcdfb_config at91sam9263_config = {
.have_intensity_bit = true,
+ .guard_time = 1,
};
static struct atmel_lcdfb_config at91sam9g10_config = {
.have_hozval = true,
+ .guard_time = 1,
};
static struct atmel_lcdfb_config at91sam9g45_config = {
.have_alt_pixclock = true,
+ .guard_time = 9,
};
static struct atmel_lcdfb_config at91sam9rl_config = {
.have_intensity_bit = true,
+ .guard_time = 1,
};
static struct atmel_lcdfb_config at32ap_config = {
.have_hozval = true,
+ .guard_time = 1,
};
static __maybe_unused struct of_device_id atmel_lcdfb_compatible[] = {
diff --git a/drivers/video/atmel_lcdfb.h b/drivers/video/atmel_lcdfb.h
index 110c71bdb..69a27cb23 100644
--- a/drivers/video/atmel_lcdfb.h
+++ b/drivers/video/atmel_lcdfb.h
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only
#include <fb.h>
+#include <video/vpl.h>
#include <video/atmel_lcdc.h>
struct atmel_lcdfb_info;
@@ -9,6 +10,7 @@ struct atmel_lcdfb_config {
bool have_alt_pixclock;
bool have_hozval;
bool have_intensity_bit;
+ unsigned int guard_time;
};
struct atmel_lcdfb_devdata {
@@ -25,6 +27,8 @@ struct atmel_lcdfb_info {
struct fb_info info;
void __iomem *mmio;
struct device_d *device;
+ int id;
+ struct vpl vpl;
unsigned int guard_time;
unsigned int smem_len;
diff --git a/drivers/video/atmel_lcdfb_core.c b/drivers/video/atmel_lcdfb_core.c
index 17f754b56..681b20a3d 100644
--- a/drivers/video/atmel_lcdfb_core.c
+++ b/drivers/video/atmel_lcdfb_core.c
@@ -13,6 +13,7 @@
#include <linux/err.h>
#include <linux/clk.h>
#include <malloc.h>
+#include <of_graph.h>
#include <mach/cpu.h>
@@ -30,10 +31,8 @@ static void atmel_lcdfb_stop_clock(struct atmel_lcdfb_info *sinfo)
clk_disable(sinfo->lcdc_clk);
}
-static void atmel_lcdc_power_controller(struct fb_info *fb_info, int on)
+static void atmel_lcdc_power_controller(struct atmel_lcdfb_info *sinfo, int on)
{
- struct atmel_lcdfb_info *sinfo = fb_info->priv;
-
if (sinfo->gpio_power_control < 0)
return;
@@ -48,7 +47,12 @@ static void atmel_lcdc_power_controller(struct fb_info *fb_info, int on)
*/
static void atmel_lcdc_enable_controller(struct fb_info *fb_info)
{
- atmel_lcdc_power_controller(fb_info, 1);
+ struct atmel_lcdfb_info *sinfo = fb_info->priv;
+ struct fb_videomode *mode = fb_info->mode;
+
+ vpl_ioctl_prepare(&sinfo->vpl, sinfo->id, mode);
+ atmel_lcdc_power_controller(sinfo, 1);
+ vpl_ioctl_enable(&sinfo->vpl, sinfo->id);
}
/**
@@ -56,7 +60,11 @@ static void atmel_lcdc_enable_controller(struct fb_info *fb_info)
*/
static void atmel_lcdc_disable_controller(struct fb_info *fb_info)
{
- atmel_lcdc_power_controller(fb_info, 0);
+ struct atmel_lcdfb_info *sinfo = fb_info->priv;
+
+ vpl_ioctl_disable(&sinfo->vpl, sinfo->id);
+ atmel_lcdc_power_controller(sinfo, 0);
+ vpl_ioctl_unprepare(&sinfo->vpl, sinfo->id);
}
@@ -311,28 +319,14 @@ static int of_get_power_control(struct device_d *dev,
return power_control_init(dev, sinfo, gpio, active_low);
}
-static int lcdfb_of_init(struct device_d *dev, struct atmel_lcdfb_info *sinfo)
+static int lcdfb_display_init(struct device_d *dev,
+ struct atmel_lcdfb_info *sinfo,
+ struct device_node *display)
{
struct fb_info *info = &sinfo->info;
struct display_timings *modes;
- struct device_node *display;
- struct atmel_lcdfb_config *config;
int ret;
- /* Driver data - optional */
- ret = dev_get_drvdata(dev, (const void **)&config);
- if (!ret) {
- sinfo->have_hozval = config->have_hozval;
- sinfo->have_intensity_bit = config->have_intensity_bit;
- sinfo->have_alt_pixclock = config->have_alt_pixclock;
- }
-
- /* Required properties */
- display = of_parse_phandle(dev->device_node, "display", 0);
- if (!display) {
- dev_err(dev, "no display phandle\n");
- return -ENOENT;
- }
ret = of_property_read_u32(display, "atmel,guard-time", &sinfo->guard_time);
if (ret < 0) {
dev_err(dev, "failed to get atmel,guard-time property\n");
@@ -373,9 +367,95 @@ static int lcdfb_of_init(struct device_d *dev, struct atmel_lcdfb_info *sinfo)
dev_err(dev, "failed to get power control gpio\n");
goto err;
}
+
return 0;
+
err:
return ret;
+
+}
+
+static int lcdfb_of_init(struct device_d *dev, struct atmel_lcdfb_info *sinfo)
+{
+ struct fb_info *info = &sinfo->info;
+ struct atmel_lcdfb_config *config;
+ struct device_node *display;
+ struct device_node *np = NULL;
+ struct of_endpoint ep;
+ int ret;
+
+ /* Driver data - optional */
+ ret = dev_get_drvdata(dev, (const void **)&config);
+ if (!ret) {
+ sinfo->have_hozval = config->have_hozval;
+ sinfo->have_intensity_bit = config->have_intensity_bit;
+ sinfo->have_alt_pixclock = config->have_alt_pixclock;
+
+ /* The display node will override the guard time if present */
+ sinfo->guard_time = config->guard_time;
+ }
+
+ /* The display handle is deprecated but still supported */
+ display = of_parse_phandle(dev->device_node, "display", 0);
+ if (display) {
+ return lcdfb_display_init(dev, sinfo, display);
+ }
+
+ for_each_available_child_of_node(dev->device_node, np) {
+ if (!of_graph_port_is_available(np))
+ continue;
+
+ ret = of_graph_parse_endpoint(np, &ep);
+ if (ret) {
+ dev_err(dev, "failed to parse endpoint\n");
+ return ret;
+ }
+ sinfo->id = ep.id;
+ break;
+ }
+
+ dev_dbg(dev, "register vpl for %s\n", dev->device_node->full_name);
+ ret = vpl_register(&sinfo->vpl);
+ if (ret)
+ return ret;
+
+ /* Only TFT panels - STN is obsolete */
+ sinfo->lcdcon2 = ATMEL_LCDC_DISTYPE_TFT;
+
+ /* LCDD Polarity normal */
+ sinfo->lcdcon2 |= ATMEL_LCDC_INVVD_NORMAL;
+
+ /* Clock is always active */
+ sinfo->lcdcon2 |= ATMEL_LCDC_CLKMOD_ALWAYSACTIVE;
+
+ /* Memory layout */
+ sinfo->lcdcon2 |= ATMEL_LCDC_MEMOR_LITTLE;
+
+ sinfo->dmacon = ATMEL_LCDC_DMAEN;
+
+ /* TODO: Maybe obtain this from panel */
+ info->bits_per_pixel = 16;
+
+ ret = vpl_ioctl(&sinfo->vpl, sinfo->id, VPL_GET_VIDEOMODES, &info->modes);
+ if (ret) {
+ dev_dbg(dev, "failed to get modes: %s\n", strerror(-ret));
+ return ret;
+ }
+
+ /* Optional properties */
+ ret = of_get_wiring_mode(dev->device_node, sinfo);
+ if (ret < 0) {
+ dev_err(dev, "failed to get atmel,lcd-wiring-mode property\n");
+ return ret;
+ }
+
+ ret = of_get_power_control(dev, dev->device_node, sinfo);
+ if (ret < 0) {
+ dev_err(dev, "failed to get power control gpio\n");
+ return ret;
+ }
+
+ return 0;
}
static int lcdfb_pdata_init(struct device_d *dev, struct atmel_lcdfb_info *sinfo)
@@ -441,6 +521,7 @@ int atmel_lcdc_register(struct device_d *dev, struct atmel_lcdfb_devdata *data)
info = &sinfo->info;
info->priv = sinfo;
info->fbops = &atmel_lcdc_ops;
+ sinfo->vpl.node = dev->device_node;
if (dev->platform_data) {
ret = lcdfb_pdata_init(dev, sinfo);
--
2.34.1
^ permalink raw reply [flat|nested] 21+ messages in thread* [PATCH v2 10/11] ARM: at91: Add xload support to skov-arm9cpu
2022-06-28 20:38 [PATCH 0/11] ARM: at91: Add pbl support to skov-arm9cpu Sam Ravnborg
` (8 preceding siblings ...)
2022-06-28 20:38 ` [WIP PATCH v2 09/11] atmel_lcdfb: add support for updated DT bindings Sam Ravnborg
@ 2022-06-28 20:38 ` Sam Ravnborg
2022-06-28 20:47 ` Sam Ravnborg
2022-06-28 20:38 ` [WIP PATCH v2 11/11] ARM: at91: Update DTS for skov-arm9cpu Sam Ravnborg
2022-06-30 12:19 ` [PATCH 0/11] ARM: at91: Add pbl support to skov-arm9cpu Sascha Hauer
11 siblings, 1 reply; 21+ messages in thread
From: Sam Ravnborg @ 2022-06-28 20:38 UTC (permalink / raw)
To: barebox, Ahmad Fatoum; +Cc: Sam Ravnborg
This updates skov-arm9cpu with xload support, and we can now
use barebox as a replacment for at91bootstrap.
Only boot via SD card is supported.
Includes several suggestions from: Ahmad Fatoum <a.fatoum@pengutronix.de>
- Use ENTRY_FUNCTION_WITHSTACK
- Reshuffeled order in early init
- SD card in not highcapacity
- Drop irrelevant max image size in images/Makefile.at91
NOTE: Actual status
[x] dbgu support in pbl works (can print)
[x] Other init stuff ifdeffed out - from at91bootstrap
[ ] Check what the original code used for div/mul - there is some confusion
[x] load barebox.bin and boots it. Right now mount fails
[ ] barebox.bin can start a linux kernel
[ ] support default SD card boots and nfsboot
[x] update Kconfig to work with xload
[x] xload image support
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
---
arch/arm/boards/skov-arm9cpu/board.c | 17 +--
arch/arm/boards/skov-arm9cpu/lowlevel.c | 158 +++++++++---------------
arch/arm/mach-at91/Kconfig | 4 +-
images/Makefile.at91 | 6 +-
4 files changed, 67 insertions(+), 118 deletions(-)
diff --git a/arch/arm/boards/skov-arm9cpu/board.c b/arch/arm/boards/skov-arm9cpu/board.c
index 8d5eadbb9..06bd9b70e 100644
--- a/arch/arm/boards/skov-arm9cpu/board.c
+++ b/arch/arm/boards/skov-arm9cpu/board.c
@@ -39,16 +39,12 @@ BAREBOX_MAGICVAR(board.mem, "The detected memory size in MiB");
static int mem;
-/*
- * Initialize of SMC must come after we
- * probe the at91sam9_smc_driver.
- * But is required before we start the other drives.
- * Use device_initcall() to maintain this order.
- */
static int skov_arm9_probe(struct device_d *dev)
{
unsigned long csa;
+ barebox_set_hostname("skov_arm9cpu");
+
add_generic_device("at91sam9-smc", 0, NULL, AT91SAM9263_BASE_SMC0, 0x200,
IORESOURCE_MEM, NULL);
add_generic_device("at91sam9-smc", 1, NULL, AT91SAM9263_BASE_SMC1, 0x200,
@@ -69,11 +65,8 @@ static int skov_arm9_probe(struct device_d *dev)
}
static __maybe_unused struct of_device_id skov_arm9_ids[] = {
- {
- .compatible = "skov,arm9-cpu",
- }, {
- /* sentinel */
- }
+ { .compatible = "skov,arm9-cpu", },
+ { /* sentinel */ }
};
static struct driver_d skov_arm9_driver = {
@@ -81,4 +74,4 @@ static struct driver_d skov_arm9_driver = {
.probe = skov_arm9_probe,
.of_compatible = DRV_OF_COMPAT(skov_arm9_ids),
};
-device_platform_driver(skov_arm9_driver);
+coredevice_platform_driver(skov_arm9_driver);
diff --git a/arch/arm/boards/skov-arm9cpu/lowlevel.c b/arch/arm/boards/skov-arm9cpu/lowlevel.c
index d335953a7..78f770043 100644
--- a/arch/arm/boards/skov-arm9cpu/lowlevel.c
+++ b/arch/arm/boards/skov-arm9cpu/lowlevel.c
@@ -1,127 +1,81 @@
// SPDX-License-Identifier: GPL-2.0
-// PDX-FileCopyrightText: 2018 Sam Ravnborg <sam@ravnborg.org>
+// PDX-FileCopyrightText: 2022 Sam Ravnborg <sam@ravnborg.org>
-#include <linux/sizes.h>
+#include <debug_ll.h>
#include <asm/barebox-arm.h>
-#include <mach/at91sam926x_board_init.h>
#include <mach/at91sam9263_matrix.h>
+#include <mach/at91sam9_sdramc.h>
+#include <mach/sam92_ll.h>
+#include <mach/xload.h>
-#define MASTER_PLL_MUL 171
-#define MASTER_PLL_DIV 14
+/* MCK = 20 MHz */
+#define MAIN_CLOCK 200000000
+#define MASTER_CLOCK (MAIN_CLOCK / 2) /* PMC_MCKR divides by 2 */
-static void __bare_init skovarm9cpu_board_config(struct at91sam926x_board_cfg *cfg)
+static void sam9263_sdramc_init(unsigned int mck)
{
- /* Disable Watchdog */
- cfg->wdt_mr =
- AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT |
- AT91_WDT_WDV |
- AT91_WDT_WDDIS |
- AT91_WDT_WDD;
-
- /* define PDC[31:16] as DATA[31:16] */
- cfg->ebi_pio_pdr = 0xFFFF0000;
- /* no pull-up for D[31:16] */
- cfg->ebi_pio_ppudr = 0xFFFF0000;
+ const struct at91sam9_sdramc_config config =
+ {
+ .sdramc = IOMEM(AT91SAM9263_BASE_SDRAMC0),
+ .mr = 0,
+ .tr = (mck * 7) / 1000000, // TODO 140 versus 0x13c (316)?
+ .cr = AT91_SDRAMC_NC_10 | AT91_SDRAMC_NR_13 | AT91_SDRAMC_CAS_2
+ | AT91_SDRAMC_NB_4 | AT91_SDRAMC_DBW_32
+ | AT91_SDRAMC_TWR_2 | AT91_SDRAMC_TRC_7
+ | AT91_SDRAMC_TRP_2 | AT91_SDRAMC_TRCD_2
+ | AT91_SDRAMC_TRAS_5 | AT91_SDRAMC_TXSR_8,
+ .lpr = 0,
+ .mdr = AT91_SDRAMC_MD_SDRAM,
+ };
+
+ /* Define PDC[31:16] as DATA[31:16] */
+ at91_mux_gpio_disable(IOMEM(AT91SAM9263_BASE_PIOD), 0xffff0000);
+ /* No pull-up for D[31:16] */
+ at91_mux_set_pullup(IOMEM(AT91SAM9263_BASE_PIOD), 0xffff0000, true);
+ /* PD16 to PD31 are pheripheral A */
+ at91_mux_set_A_periph(IOMEM(AT91SAM9263_BASE_PIOD), 0xffff0000);
+
/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
- cfg->ebi_csa =
- AT91SAM9263_MATRIX_EBI0_DBPUC | AT91SAM9263_MATRIX_EBI0_VDDIOMSEL_3_3V |
- AT91SAM9263_MATRIX_EBI0_CS1A_SDRAMC;
-
- cfg->smc_cs = 0;
- cfg->smc_mode =
- AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
- AT91_SMC_DBW_16 |
- AT91_SMC_TDFMODE |
- AT91_SMC_TDF_(6);
- cfg->smc_cycle =
- AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22);
- cfg->smc_pulse =
- AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) |
- AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11);
- cfg->smc_setup =
- AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) |
- AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10);
-
- cfg->pmc_mor =
- AT91_PMC_MOSCEN |
- (255 << 8); /* Main Oscillator Start-up Time */
- cfg->pmc_pllar =
- AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */
- AT91_PMC_OUT |
- AT91_PMC_PLLCOUNT | /* PLL Counter */
- (2 << 28) | /* PLL Clock Frequency Range */
- ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV);
- /* PCK/2 = MCK Master Clock from PLLA */
- cfg->pmc_mckr1 =
- AT91_PMC_CSS_SLOW |
- AT91_PMC_PRES_1 |
- AT91SAM9_PMC_MDIV_2 |
- AT91_PMC_PDIV_1;
- /* PCK/2 = MCK Master Clock from PLLA */
- cfg->pmc_mckr2 =
- AT91_PMC_CSS_PLLA |
- AT91_PMC_PRES_1 |
- AT91SAM9_PMC_MDIV_2 |
- AT91_PMC_PDIV_1;
-
- /* SDRAM */
- /* SDRAMC_TR - Refresh Timer register */
- cfg->sdrc_tr1 = 0x13C;
- /* SDRAMC_CR - Configuration register*/
- cfg->sdrc_cr =
- AT91_SDRAMC_NC_10 | /* Assume 128MiB */
- AT91_SDRAMC_NR_13 |
- AT91_SDRAMC_NB_4 |
- AT91_SDRAMC_CAS_3 |
- AT91_SDRAMC_DBW_32 |
- (1 << 8) | /* Write Recovery Delay */
- (7 << 12) | /* Row Cycle Delay */
- (2 << 16) | /* Row Precharge Delay */
- (2 << 20) | /* Row to Column Delay */
- (5 << 24) | /* Active to Precharge Delay */
- (1 << 28); /* Exit Self Refresh to Active Delay */
-
- /* Memory Device Register -> SDRAM */
- cfg->sdrc_mdr = AT91_SDRAMC_MD_SDRAM;
- /* SDRAM_TR */
- cfg->sdrc_tr2 = 1200;
-
- /* user reset enable */
- cfg->rstc_rmr =
- AT91_RSTC_KEY |
- AT91_RSTC_PROCRST |
- AT91_RSTC_RSTTYP_WAKEUP |
- AT91_RSTC_RSTTYP_WATCHDOG;
+ writel(AT91SAM9263_MATRIX_EBI0_DBPUC
+ | AT91SAM9263_MATRIX_EBI0_VDDIOMSEL_3_3V
+ | AT91SAM9263_MATRIX_EBI0_CS1A_SDRAMC,
+ IOMEM(AT91SAM9263_BASE_MATRIX + AT91SAM9263_MATRIX_EBI0CSA));
+
+ at91sam9_sdramc_initialize(&config, AT91SAM9263_BASE_EBI0_CS1);
}
-static void __bare_init skov_arm9cpu_init(void *fdt)
+/* Top of stack is the top of the internal SRAM */
+#define STACK_TOP (AT91SAM9263_SRAM0_BASE + AT91SAM9263_SRAM0_SIZE)
+
+ENTRY_FUNCTION_WITHSTACK(start_skov_arm9cpu_xload, STACK_TOP, r0, r1, r2)
{
- struct at91sam926x_board_cfg cfg;
+ const struct sam92_pmc_config sam92_pmc_config = {
+ /* X-tal is 16.000 MHz so 16 / 4 * (31 + 1) = 200 */
+ .diva = 14,
+ .mula = 171,
+ };
- cfg.pio = IOMEM(AT91SAM9263_BASE_PIOD);
- cfg.sdramc = IOMEM(AT91SAM9263_BASE_SDRAMC0);
- cfg.ebi_pio_is_peripha = true;
- cfg.matrix_csa = IOMEM(AT91SAM9263_BASE_MATRIX + AT91SAM9263_MATRIX_EBI0CSA);
+ /* Configure system so we are less constrained */
+ arm_cpu_lowlevel_init();
+ relocate_to_current_adr();
+ setup_c();
- skovarm9cpu_board_config(&cfg);
- at91sam9263_board_init(&cfg);
+ sam9263_lowlevel_init(&sam92_pmc_config);
+ sam92_dbgu_setup_ll(MASTER_CLOCK);
- barebox_arm_entry(AT91_CHIPSELECT_1, at91_get_sdram_size(cfg.sdramc),
- fdt);
+ sam92_udelay_init(MASTER_CLOCK);
+ sam9263_sdramc_init(MASTER_CLOCK);
+ sam9263_atmci_start_image(1, MASTER_CLOCK, 0);
}
extern char __dtb_at91_skov_arm9cpu_start[];
-ENTRY_FUNCTION(start_skov_arm9cpu, r0, r1, r2)
+ENTRY_FUNCTION_WITHSTACK(start_skov_arm9cpu, STACK_TOP, r0, r1, r2)
{
void *fdt;
- arm_cpu_lowlevel_init();
-
- arm_setup_stack(AT91SAM9263_SRAM0_BASE + AT91SAM9263_SRAM0_SIZE);
fdt = __dtb_at91_skov_arm9cpu_start + get_runtime_offset();
-
- skov_arm9cpu_init(fdt);
+ barebox_arm_entry(AT91_CHIPSELECT_1, at91sam9263_get_sdram_size(0), fdt);
}
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index bc55b1c4e..f5f674d82 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -577,9 +577,7 @@ config MACH_SKOV_ARM9CPU
select SOC_AT91SAM9263
select OFDEVICE
select COMMON_CLK_OF_PROVIDER
- select HAVE_AT91_USB_CLK
- select HAVE_AT91_BOOTSTRAP
- select AT91SAM926X_BOARD_INIT
+ select MCI_ATMEL_PBL
help
Say y here if you are using SKOV's ARM9 CPU board
diff --git a/images/Makefile.at91 b/images/Makefile.at91
index 71cc959f5..076981339 100644
--- a/images/Makefile.at91
+++ b/images/Makefile.at91
@@ -47,7 +47,11 @@ FILE_barebox-groboards-sama5d27-giantboard-xload-mmc.img = start_sama5d27_giantb
MAX_PBL_IMAGE_SIZE_start_sama5d27_giantboard_xload_mmc = 0xffff
image-$(CONFIG_MACH_SAMA5D27_GIANTBOARD) += barebox-groboards-sama5d27-giantboard-xload-mmc.img
+pblb-$(CONFIG_MACH_SKOV_ARM9CPU) += start_skov_arm9cpu_xload
+FILE_barebox-skov-arm9cpu-xload.img = start_skov_arm9cpu_xload.pblb
+MAX_PBL_MEMORY_SIZE_start_skov_arm9cpu = 0x12000
+image-$(CONFIG_MACH_SKOV_ARM9CPU) += barebox-skov-arm9cpu-xload.img
+
pblb-$(CONFIG_MACH_SKOV_ARM9CPU) += start_skov_arm9cpu
FILE_barebox-skov-arm9cpu.img = start_skov_arm9cpu.pblb
-MAX_PBL_MEMORY_SIZE_start_skov_arm9cpu = 0x12000
image-$(CONFIG_MACH_SKOV_ARM9CPU) += barebox-skov-arm9cpu.img
--
2.34.1
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [PATCH v2 10/11] ARM: at91: Add xload support to skov-arm9cpu
2022-06-28 20:38 ` [PATCH v2 10/11] ARM: at91: Add xload support to skov-arm9cpu Sam Ravnborg
@ 2022-06-28 20:47 ` Sam Ravnborg
0 siblings, 0 replies; 21+ messages in thread
From: Sam Ravnborg @ 2022-06-28 20:47 UTC (permalink / raw)
To: barebox, Ahmad Fatoum
Hi myself,
On Tue, Jun 28, 2022 at 10:38:48PM +0200, Sam Ravnborg wrote:
> This updates skov-arm9cpu with xload support, and we can now
> use barebox as a replacment for at91bootstrap.
>
> Only boot via SD card is supported.
>
> Includes several suggestions from: Ahmad Fatoum <a.fatoum@pengutronix.de>
> - Use ENTRY_FUNCTION_WITHSTACK
> - Reshuffeled order in early init
> - SD card in not highcapacity
> - Drop irrelevant max image size in images/Makefile.at91
>
> NOTE: Actual status
> [x] dbgu support in pbl works (can print)
> [x] Other init stuff ifdeffed out - from at91bootstrap
> [ ] Check what the original code used for div/mul - there is some confusion
> [x] load barebox.bin and boots it. Right now mount fails
> [ ] barebox.bin can start a linux kernel
> [ ] support default SD card boots and nfsboot
> [x] update Kconfig to work with xload
> [x] xload image support
This patch is also WIP - I still need to check some details and the todo
list needs a refresh as I have completed more of the items.
Sam
^ permalink raw reply [flat|nested] 21+ messages in thread
* [WIP PATCH v2 11/11] ARM: at91: Update DTS for skov-arm9cpu
2022-06-28 20:38 [PATCH 0/11] ARM: at91: Add pbl support to skov-arm9cpu Sam Ravnborg
` (9 preceding siblings ...)
2022-06-28 20:38 ` [PATCH v2 10/11] ARM: at91: Add xload support to skov-arm9cpu Sam Ravnborg
@ 2022-06-28 20:38 ` Sam Ravnborg
2022-06-30 12:19 ` [PATCH 0/11] ARM: at91: Add pbl support to skov-arm9cpu Sascha Hauer
11 siblings, 0 replies; 21+ messages in thread
From: Sam Ravnborg @ 2022-06-28 20:38 UTC (permalink / raw)
To: barebox, Ahmad Fatoum; +Cc: Sam Ravnborg
Update the device tree with the following:
- Add backlight node
- Add panel node for the Logic L2 panel
- Add graph node to connect display with the panel
- Drop all obsolete properties for the display node
The updates was done to have proper support for backlight and
to be compatible with the updated bindings for the display node.
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
---
arch/arm/dts/at91-skov-arm9cpu.dts | 107 +++++++++++++----------------
1 file changed, 49 insertions(+), 58 deletions(-)
diff --git a/arch/arm/dts/at91-skov-arm9cpu.dts b/arch/arm/dts/at91-skov-arm9cpu.dts
index 8e4fddfd3..c8d88050d 100644
--- a/arch/arm/dts/at91-skov-arm9cpu.dts
+++ b/arch/arm/dts/at91-skov-arm9cpu.dts
@@ -202,43 +202,31 @@
0x04050056 /* col5 row4 KEY_102ND */
>;
};
-};
-&{/ahb/apb} {
- pinctrl: pinctrl@fffff200 {
+ panel_reg: panel_reg {
+ compatible = "regulator-fixed";
+ regulator-name = "panel-power-supply";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ status = "okay";
};
- watchdog@fffffd40 {
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm0 1 100000 1>;
+ brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
+ default-brightness-level = <8>;
status = "okay";
};
-};
-
-&dbgu {
- status = "okay";
-};
-&fb0 {
- status = "okay";
- display = <&display0>;
- display0: display0 {
- bits-per-pixel = <16>;
- atmel,lcdcon-backlight;
- atmel,dmacon = <0x1>;
- atmel,lcdcon2 = <0x80008002>;
- atmel,guard-time = <1>;
- atmel,lcd-wiring-mode = "BRG";
- pinctrl-names = "default";
- pinctrl-0 = <
- &pinctrl_board_fb
- &pinctrl_disp_type
- &pinctrl_logic_type
- >;
- atmel,power-control-gpio = <&pioA 30 GPIO_ACTIVE_HIGH>;
+ panel: panel {
+ compatible = "logictechno,lttd800480070-l2rt", "simple-panel";
+ backlight = <&backlight>;
+ power-supply = <&panel_reg>;
+ status = "okay";
display-timings {
- native-mode = <&l2rt>;
-
l2rt: l2rt {
/* LTTD800480070-L2RT @ 55 */
clock-frequency = <30000000>;
@@ -264,39 +252,42 @@
vsync-active = <0>;
de-active = <1>;
};
+ };
- l6whrt: l6whrt {
- clock-frequency = <33000000>;
- hactive = <800>;
- vactive = <480>;
- hback-porch = <43>;
- hfront-porch = <154>;
- vback-porch = <20>;
- vfront-porch = <47>;
- hsync-len = <3>;
- vsync-len = <3>;
- pixelclk-active = <1>;
- hsync-active = <0>;
- vsync-active = <0>;
- de-active = <1>;
+ port {
+ panel_input: endpoint {
+ remote-endpoint = <&panel_output>;
};
+ };
+ };
+};
- seiko: seiko {
- /* 70WVW2AZ0 @ 55 */
- clock-frequency = <33000000>;
- hactive = <800>;
- vactive = <480>;
- hback-porch = <0>;
- hfront-porch = <256>;
- vback-porch = <45>;
- vfront-porch = <0>;
- hsync-len = <0>;
- vsync-len = <0>;
- pixelclk-active = <1>;
- hsync-active = <0>;
- vsync-active = <0>;
- de-active = <1>;
- };
+&{/ahb/apb} {
+ pinctrl: pinctrl@fffff200 {
+ };
+
+ watchdog@fffffd40 {
+ status = "okay";
+ };
+};
+
+&dbgu {
+ status = "okay";
+};
+
+&fb0 {
+ status = "okay";
+
+ pinctrl-0 = <
+ &pinctrl_board_fb
+ &pinctrl_disp_type
+ &pinctrl_logic_type>;
+
+ atmel,lcd-wiring-mode = "BRG";
+
+ port {
+ panel_output: endpoint {
+ remote-endpoint = <&panel_input>;
};
};
};
--
2.34.1
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [PATCH 0/11] ARM: at91: Add pbl support to skov-arm9cpu
2022-06-28 20:38 [PATCH 0/11] ARM: at91: Add pbl support to skov-arm9cpu Sam Ravnborg
` (10 preceding siblings ...)
2022-06-28 20:38 ` [WIP PATCH v2 11/11] ARM: at91: Update DTS for skov-arm9cpu Sam Ravnborg
@ 2022-06-30 12:19 ` Sascha Hauer
11 siblings, 0 replies; 21+ messages in thread
From: Sascha Hauer @ 2022-06-30 12:19 UTC (permalink / raw)
To: Sam Ravnborg; +Cc: barebox, Ahmad Fatoum
On Tue, Jun 28, 2022 at 10:38:38PM +0200, Sam Ravnborg wrote:
> The following is the current set of patches so far to support
> PBL for the skov-arm9cpu.
>
> The pwm is not really part of this - but it is part of the story.
> The patch-set was triggered when someone reported a bug in the
> atmel pwm code. The code did not build - so I ported it over.
> Now I wanted to boot the target, but at91bootstrap no longer
> supports the at91sam9263. So I decided to try to make it work
> in barebox. I have tried this before and failed - but it should
> be possible...
>
> What I have made is modelled on top of all the great work
> for other more modern atmel bouards.
>
> v2:
> - The first stage bootloader works - thanks to feedback from Ahmad!
> - Add support for non-high capacity SD cards, as required by at91sam9 (Ahmad)
> - Replace hardcoded delay loops with pit based early delays (Ahmad)
> - Several adjustments to skov-arm9cpu code to fit the changes
>
> The following patches are not ready:
> - atmel_lcdfb: add support for updated DT bindings
> - ARM: at91: Update DTS for skov-arm9cpu
>
> They both rely on updated bindings that has not landed yet,
> and which may end up not being compatible with the changes
> implemented here.
> So the patches works - but bindings are work-in-progress.
>
> My plan is to resurrect my drm driver for at91sam9 and
> with that the update the binding file. But timeline
> for this work is unknowm.
>
> In other words - I assume patch 1 to 8 + 10 as ready.
> Patch 9 + 11 are WIP.
>
> Sam
>
> Sam Ravnborg (11):
> pwm: atmel: Fix build and update
> ARM: at91: Make sdramc.h useable in multi image builds
> ARM: at91: Add initialize function to sdramc
> ARM: at91: Provide at91_mux_pio_pin for use in lowlevel
> mci: atmel_mci: Add PBL helper to configure highcapacity
> ARM: at91: Add at91sam9 xload_mmc for PBL use
> ARM: at91: Add extra register definitions
> ARM: at91: Add lowlevel helpers for at91sam9263
> atmel_lcdfb: add support for updated DT bindings
> ARM: at91: Add xload support to skov-arm9cpu
> ARM: at91: Update DTS for skov-arm9cpu
Applied 1-8, thanks
Sascha
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^ permalink raw reply [flat|nested] 21+ messages in thread