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* [PATCH master v2] ARM: i.MX7: enable caches when booted over USB
@ 2022-10-10  6:34 Ahmad Fatoum
  2022-10-10  7:10 ` Sascha Hauer
  0 siblings, 1 reply; 2+ messages in thread
From: Ahmad Fatoum @ 2022-10-10  6:34 UTC (permalink / raw)
  To: barebox; +Cc: mfe, Ahmad Fatoum

BootROM on the i.MX7 doesn't set the SMP bit when booted
over serial download. This leads to vastly worse performance
when doing memory-heavy operations in a USB-booted system,
as the caches are not utilized. Example running md5sum over
a 25M image in ramfs:

  without patch: 10796ms
  with    patch: 457ms

This issue isn't unique to the i.MX7, but exists for the i.MX6UL as
well, which also has the Cortex-A7 as CPU. Like with
imx6ul_cpu_lowlevel_init(), adapt imx7_cpu_lowlevel_init() to avoid this
slow down.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Johannes Zink <j.zink@pengutronix.de>
---
v1 -> v2:
  - don't drop arm arm_cpu_lowlevel_init as cortex_a7_lowlevel_init
    does not call it (Marco)
---
 arch/arm/mach-imx/cpu_init.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-imx/cpu_init.c b/arch/arm/mach-imx/cpu_init.c
index ea3621541979..3f16ca70ce26 100644
--- a/arch/arm/mach-imx/cpu_init.c
+++ b/arch/arm/mach-imx/cpu_init.c
@@ -49,6 +49,7 @@ void imx6ul_cpu_lowlevel_init(void)
 
 void imx7_cpu_lowlevel_init(void)
 {
+	cortex_a7_lowlevel_init();
 	arm_cpu_lowlevel_init();
 	imx_cpu_timer_init(IOMEM(MX7_SYSCNT_CTRL_BASE_ADDR));
 }
-- 
2.30.2




^ permalink raw reply	[flat|nested] 2+ messages in thread

* Re: [PATCH master v2] ARM: i.MX7: enable caches when booted over USB
  2022-10-10  6:34 [PATCH master v2] ARM: i.MX7: enable caches when booted over USB Ahmad Fatoum
@ 2022-10-10  7:10 ` Sascha Hauer
  0 siblings, 0 replies; 2+ messages in thread
From: Sascha Hauer @ 2022-10-10  7:10 UTC (permalink / raw)
  To: Ahmad Fatoum; +Cc: barebox, mfe

On Mon, Oct 10, 2022 at 08:34:30AM +0200, Ahmad Fatoum wrote:
> BootROM on the i.MX7 doesn't set the SMP bit when booted
> over serial download. This leads to vastly worse performance
> when doing memory-heavy operations in a USB-booted system,
> as the caches are not utilized. Example running md5sum over
> a 25M image in ramfs:
> 
>   without patch: 10796ms
>   with    patch: 457ms
> 
> This issue isn't unique to the i.MX7, but exists for the i.MX6UL as
> well, which also has the Cortex-A7 as CPU. Like with
> imx6ul_cpu_lowlevel_init(), adapt imx7_cpu_lowlevel_init() to avoid this
> slow down.
> 
> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> Signed-off-by: Johannes Zink <j.zink@pengutronix.de>
> ---
> v1 -> v2:
>   - don't drop arm arm_cpu_lowlevel_init as cortex_a7_lowlevel_init
>     does not call it (Marco)
> ---
>  arch/arm/mach-imx/cpu_init.c | 1 +
>  1 file changed, 1 insertion(+)

Applied, thanks

Sascha

> 
> diff --git a/arch/arm/mach-imx/cpu_init.c b/arch/arm/mach-imx/cpu_init.c
> index ea3621541979..3f16ca70ce26 100644
> --- a/arch/arm/mach-imx/cpu_init.c
> +++ b/arch/arm/mach-imx/cpu_init.c
> @@ -49,6 +49,7 @@ void imx6ul_cpu_lowlevel_init(void)
>  
>  void imx7_cpu_lowlevel_init(void)
>  {
> +	cortex_a7_lowlevel_init();
>  	arm_cpu_lowlevel_init();
>  	imx_cpu_timer_init(IOMEM(MX7_SYSCNT_CTRL_BASE_ADDR));
>  }
> -- 
> 2.30.2
> 
> 
> 

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^ permalink raw reply	[flat|nested] 2+ messages in thread

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2022-10-10  6:34 [PATCH master v2] ARM: i.MX7: enable caches when booted over USB Ahmad Fatoum
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