From: Vyacheslav Yurkov <uvv.mail@gmail.com>
To: barebox@lists.infradead.org
Cc: Vyacheslav Yurkov <Vyacheslav.Yurkov@bruker.com>
Subject: [PATCH 2/2] ARM: socfpga: Configure F2SDRAM bridges
Date: Tue, 1 Nov 2022 10:52:41 +0100 [thread overview]
Message-ID: <20221101095241.984845-2-uvv.mail@gmail.com> (raw)
In-Reply-To: <20221101095241.984845-1-uvv.mail@gmail.com>
From: Vyacheslav Yurkov <Vyacheslav.Yurkov@bruker.com>
When DDR firewall configuration is updated the F2SDRAM bridges need to
be brought from reset.
Signed-off-by: Vyacheslav Yurkov <Vyacheslav.Yurkov@bruker.com>
---
arch/arm/mach-socfpga/arria10-sdram.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/mach-socfpga/arria10-sdram.c b/arch/arm/mach-socfpga/arria10-sdram.c
index b7eade0b17..a6eb63299a 100644
--- a/arch/arm/mach-socfpga/arria10-sdram.c
+++ b/arch/arm/mach-socfpga/arria10-sdram.c
@@ -468,6 +468,18 @@ static void arria10_sdram_mmr_init(void)
}
}
+static void arria10_f2sdram_bridges_reset(void)
+{
+ uint32_t val;
+
+ /* Release F2SDRAM bridges from reset */
+ val = readl(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_BRGMODRST);
+ val &= ~(ARRIA10_RSTMGR_BRGMODRST_F2SSDRAM0 |
+ ARRIA10_RSTMGR_BRGMODRST_F2SSDRAM1 |
+ ARRIA10_RSTMGR_BRGMODRST_F2SSDRAM2);
+ writel(val, ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_BRGMODRST);
+}
+
static int arria10_sdram_firewall_setup(void)
{
uint32_t mpu_en = 0;
@@ -512,6 +524,8 @@ static int arria10_sdram_firewall_setup(void)
writel(0xffff0000, ARRIA10_NOC_FW_DDR_L3_HPSREGION0ADDR);
writel(ARRIA10_NOC_FW_DDR_L3_HPSREG0EN, ARRIA10_NOC_FW_DDR_L3_EN);
+ arria10_f2sdram_bridges_reset();
+
return 0;
}
--
2.25.1
next prev parent reply other threads:[~2022-11-01 9:54 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-01 9:52 [PATCH 1/2] ARM: socfpga: Fix SDRAM firewall init Vyacheslav Yurkov
2022-11-01 9:52 ` Vyacheslav Yurkov [this message]
2022-11-01 9:58 ` Ahmad Fatoum
2022-11-01 10:05 ` Vyacheslav Yurkov
2022-11-01 10:13 ` Ahmad Fatoum
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