From: Sascha Hauer <sha@pengutronix.de>
To: Vyacheslav Yurkov <uvv.mail@gmail.com>
Cc: barebox@lists.infradead.org,
Vyacheslav Yurkov <Vyacheslav.Yurkov@bruker.com>
Subject: Re: [PATCH v2 1/2] ARM: socfpga: Fix SDRAM firewall init
Date: Wed, 2 Nov 2022 09:07:22 +0100 [thread overview]
Message-ID: <20221102080722.GF3143@pengutronix.de> (raw)
In-Reply-To: <20221101103327.985435-1-uvv.mail@gmail.com>
On Tue, Nov 01, 2022 at 11:33:26AM +0100, Vyacheslav Yurkov wrote:
> From: Vyacheslav Yurkov <Vyacheslav.Yurkov@bruker.com>
>
> Incorrect enable bits were used in initialization sequence of SDRAM
> firewall. This enables the FPGA to access regions of SDRAM, which were
> previously inaccessible.
>
> Signed-off-by: Vyacheslav Yurkov <Vyacheslav.Yurkov@bruker.com>
> ---
> arch/arm/mach-socfpga/arria10-sdram.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
Applied, thanks
Sascha
>
> diff --git a/arch/arm/mach-socfpga/arria10-sdram.c b/arch/arm/mach-socfpga/arria10-sdram.c
> index 35c355df71..b7eade0b17 100644
> --- a/arch/arm/mach-socfpga/arria10-sdram.c
> +++ b/arch/arm/mach-socfpga/arria10-sdram.c
> @@ -486,7 +486,7 @@ static int arria10_sdram_firewall_setup(void)
> writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_MPUREGION3ADDR);
> writel(0xffff0000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION0ADDR);
>
> - mpu_en |= ARRIA10_NOC_FW_DDR_MPU_MPUREG1EN;
> + mpu_en |= ARRIA10_NOC_FW_DDR_MPU_F2SDR0REG0EN;
> writel(mpu_en, ARRIA10_SDR_FW_MPU_FPGA_EN);
>
> writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION1ADDR);
> @@ -494,7 +494,7 @@ static int arria10_sdram_firewall_setup(void)
> writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION3ADDR);
> writel(0xffff0000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION0ADDR);
>
> - mpu_en |= ARRIA10_NOC_FW_DDR_MPU_MPUREG2EN;
> + mpu_en |= ARRIA10_NOC_FW_DDR_MPU_F2SDR1REG0EN;
> writel(mpu_en, ARRIA10_SDR_FW_MPU_FPGA_EN);
>
> writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION1ADDR);
> @@ -502,7 +502,7 @@ static int arria10_sdram_firewall_setup(void)
> writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION3ADDR);
> writel(0xffff0000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM2REGION0ADDR);
>
> - mpu_en |= ARRIA10_NOC_FW_DDR_MPU_MPUREG3EN;
> + mpu_en |= ARRIA10_NOC_FW_DDR_MPU_F2SDR2REG0EN;
> writel(mpu_en, ARRIA10_SDR_FW_MPU_FPGA_EN);
>
> writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM2REGION1ADDR);
> --
> 2.25.1
>
>
>
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prev parent reply other threads:[~2022-11-02 8:08 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-01 10:33 Vyacheslav Yurkov
2022-11-01 10:33 ` [PATCH v2 2/2] ARM: socfpga: Configure F2SDRAM bridges Vyacheslav Yurkov
2022-11-02 8:07 ` Sascha Hauer [this message]
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