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* [PATCH v2 1/2] ARM: socfpga: Fix SDRAM firewall init
@ 2022-11-01 10:33 Vyacheslav Yurkov
  2022-11-01 10:33 ` [PATCH v2 2/2] ARM: socfpga: Configure F2SDRAM bridges Vyacheslav Yurkov
  2022-11-02  8:07 ` [PATCH v2 1/2] ARM: socfpga: Fix SDRAM firewall init Sascha Hauer
  0 siblings, 2 replies; 3+ messages in thread
From: Vyacheslav Yurkov @ 2022-11-01 10:33 UTC (permalink / raw)
  To: barebox; +Cc: Vyacheslav Yurkov

From: Vyacheslav Yurkov <Vyacheslav.Yurkov@bruker.com>

Incorrect enable bits were used in initialization sequence of SDRAM
firewall. This enables the FPGA to access regions of SDRAM, which were
previously inaccessible.

Signed-off-by: Vyacheslav Yurkov <Vyacheslav.Yurkov@bruker.com>
---
 arch/arm/mach-socfpga/arria10-sdram.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-socfpga/arria10-sdram.c b/arch/arm/mach-socfpga/arria10-sdram.c
index 35c355df71..b7eade0b17 100644
--- a/arch/arm/mach-socfpga/arria10-sdram.c
+++ b/arch/arm/mach-socfpga/arria10-sdram.c
@@ -486,7 +486,7 @@ static int arria10_sdram_firewall_setup(void)
 	writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_MPUREGION3ADDR);
 	writel(0xffff0000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION0ADDR);
 
-	mpu_en |= ARRIA10_NOC_FW_DDR_MPU_MPUREG1EN;
+	mpu_en |= ARRIA10_NOC_FW_DDR_MPU_F2SDR0REG0EN;
 	writel(mpu_en, ARRIA10_SDR_FW_MPU_FPGA_EN);
 
 	writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION1ADDR);
@@ -494,7 +494,7 @@ static int arria10_sdram_firewall_setup(void)
 	writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION3ADDR);
 	writel(0xffff0000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION0ADDR);
 
-	mpu_en |= ARRIA10_NOC_FW_DDR_MPU_MPUREG2EN;
+	mpu_en |= ARRIA10_NOC_FW_DDR_MPU_F2SDR1REG0EN;
 	writel(mpu_en, ARRIA10_SDR_FW_MPU_FPGA_EN);
 
 	writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION1ADDR);
@@ -502,7 +502,7 @@ static int arria10_sdram_firewall_setup(void)
 	writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION3ADDR);
 	writel(0xffff0000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM2REGION0ADDR);
 
-	mpu_en |= ARRIA10_NOC_FW_DDR_MPU_MPUREG3EN;
+	mpu_en |= ARRIA10_NOC_FW_DDR_MPU_F2SDR2REG0EN;
 	writel(mpu_en, ARRIA10_SDR_FW_MPU_FPGA_EN);
 
 	writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM2REGION1ADDR);
-- 
2.25.1




^ permalink raw reply	[flat|nested] 3+ messages in thread

end of thread, other threads:[~2022-11-02  8:08 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-11-01 10:33 [PATCH v2 1/2] ARM: socfpga: Fix SDRAM firewall init Vyacheslav Yurkov
2022-11-01 10:33 ` [PATCH v2 2/2] ARM: socfpga: Configure F2SDRAM bridges Vyacheslav Yurkov
2022-11-02  8:07 ` [PATCH v2 1/2] ARM: socfpga: Fix SDRAM firewall init Sascha Hauer

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