[PATCH 09/10] arm: socfpga: iossm: add memory initialization with inline ecc

[Michael Tretter <m.tretter@pengutronix.de>]

The memory interfaces may support for inline ECC and report their
configuration via the ECC status. The software is responsible for
initializing the memory accordingly.

Check the memory interface configuration and initialize the memory if
necessary.

Inline ECC uses 1/8 of the available memory for error correction. Thus,
only 7/8 of the reported memory size is actually available.

Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
 arch/arm/mach-socfpga/agilex5-sdram.c |  2 ++
 arch/arm/mach-socfpga/iossm_mailbox.c | 31 +++++++++++++++++++++++++++----
 arch/arm/mach-socfpga/iossm_mailbox.h |  1 +
 3 files changed, 30 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-socfpga/agilex5-sdram.c b/arch/arm/mach-socfpga/agilex5-sdram.c
index 5fb59d413e8f..4e7994985d26 100644
--- a/arch/arm/mach-socfpga/agilex5-sdram.c
+++ b/arch/arm/mach-socfpga/agilex5-sdram.c
@@ -323,6 +323,8 @@ int agilex5_ddr_init_full(void)
 	}
 
 	hw_size = io96b_ctrl.overall_size;
+	if (io96b_ctrl.inline_ecc)
+		hw_size -= hw_size / 8;
 	pr_debug("%s: %lld MiB\n", io96b_ctrl.ddr_type, hw_size / SZ_1M);
 
 	sdram_set_firewall(hw_size);
diff --git a/arch/arm/mach-socfpga/iossm_mailbox.c b/arch/arm/mach-socfpga/iossm_mailbox.c
index 6be1119724d6..4c6a84feccc5 100644
--- a/arch/arm/mach-socfpga/iossm_mailbox.c
+++ b/arch/arm/mach-socfpga/iossm_mailbox.c
@@ -456,6 +456,7 @@ int io96b_ecc_enable_status(struct io96b_info *io96b_ctrl)
 	u32 ecc_enable_intf;
 	bool ecc_stat_set = false;
 	bool ecc_stat;
+	bool inline_ecc = false;
 
 	/* Initialize ECC status */
 	io96b_ctrl->ecc_status = false;
@@ -472,13 +473,19 @@ int io96b_ecc_enable_status(struct io96b_info *io96b_ctrl)
 			ecc_enable_intf = IOSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status)
 
 			ecc_stat = (ecc_enable_intf & GENMASK(1, 0)) == 0 ? false : true;
+			inline_ecc = FIELD_GET(BIT(8), ecc_enable_intf);
 
 			if (!ecc_stat_set) {
 				io96b_ctrl->ecc_status = ecc_stat;
+
+				if (io96b_ctrl->ecc_status)
+					io96b_ctrl->inline_ecc = inline_ecc;
+
 				ecc_stat_set = true;
 			}
 
-			if (ecc_stat != io96b_ctrl->ecc_status) {
+			if (ecc_stat != io96b_ctrl->ecc_status ||
+			    (io96b_ctrl->ecc_status && inline_ecc != io96b_ctrl->inline_ecc)) {
 				pr_err("%s: Mismatch DDR ECC status on IO96B_%d\n",
 				       __func__, i);
 				return -ENOEXEC;
@@ -539,9 +546,25 @@ static int bist_mem_init_by_addr(struct io96b_info *io96b_ctrl,
 	int ret = 0;
 	u32 mem_exp;
 
-	pr_debug("%s: Start memory initialization BIST on full memory address",
-		 __func__);
-	mem_exp = 0x40;
+	if (io96b_ctrl->inline_ecc) {
+		phys_size_t chunk_size;
+
+		/* Check if size is a power of 2 */
+		if (size == 0 || (size & (size - 1)) != 0)
+			return -EINVAL;
+
+		mem_exp = 0;
+		chunk_size = size;
+		while (chunk_size >>= 1)
+			mem_exp++;
+
+		pr_debug("%s: Initializing memory: Addr=0x%llx, Size=2^%u\n",
+			 __func__, base_addr, mem_exp);
+	} else {
+		pr_debug("%s: Start memory initialization BIST on full memory address",
+			 __func__);
+		mem_exp = 0x40;
+	}
 
 	ret = io96b_mb_req(io96b_csr_addr,
 			   mb_ctrl->ip_type[interface],
diff --git a/arch/arm/mach-socfpga/iossm_mailbox.h b/arch/arm/mach-socfpga/iossm_mailbox.h
index 1b1bb1c7a19a..940678fa9d2b 100644
--- a/arch/arm/mach-socfpga/iossm_mailbox.h
+++ b/arch/arm/mach-socfpga/iossm_mailbox.h
@@ -127,6 +127,7 @@ struct io96b_info {
 	bool			 overall_cal_status;
 	const char		*ddr_type;
 	bool			 ecc_status;
+	bool			 inline_ecc;
 	phys_size_t		 overall_size;
 	struct io96b_instance	 io96b[MAX_IO96B_SUPPORTED];
 	bool			 ckgen_lock;

-- 
2.47.3