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From: Ahmad Fatoum <a.fatoum@pengutronix.de>
To: barebox@lists.infradead.org
Cc: Ahmad Fatoum <a.fatoum@barebox.org>
Subject: [PATCH 1/8] clk: stm32f4: allow building under COMPILE_TEST and fix the build
Date: Mon, 31 Aug 2026 21:35:48 +0200	[thread overview]
Message-ID: <20260831193605.1474749-1-a.fatoum@pengutronix.de> (raw)

From: Ahmad Fatoum <a.fatoum@barebox.org>

No in-tree defconfig combines ARCH_STM32 with this driver, so it has
never been compiled and doesn't build:

  clk-stm32f4.c:1665:20: error: 'struct clk_mux' has no member named 'width'

barebox' struct clk_mux carries a mask like Linux', so assign it
verbatim as upstream does; the tables already hold unshifted masks.

The symbol can't be enabled at all either: its prompt is gated on
COMPILE_TEST and it has no default, and the only in-tree selector of
ARCH_STM32 is ARCH_STM32MP, which uses clk-stm32mp1.c instead.

As I still hope to finish upstreaming my STM32F support one day, let's
just ensure the driver compile tests for now.

Fixes: 27923adcd1b7 ("clk: add clock driver for stm32f4 and stm32f7")
Signed-off-by: Ahmad Fatoum <a.fatoum@barebox.org>
---
 drivers/clk/Kconfig       | 4 ++--
 drivers/clk/clk-stm32f4.c | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index fe7056f8971b..e11361c43895 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -43,8 +43,8 @@ config CLK_SOCFPGA
 if COMMON_CLK
 
 config COMMON_CLK_STM32F
-	bool "STM32F4 and STM32F7 clock driver" if COMPILE_TEST
-	depends on ARCH_STM32
+	bool "STM32F4 and STM32F7 clock driver"
+	depends on ARCH_STM32 || COMPILE_TEST
 	help
 	  Support for stm32f4 and stm32f7 SoC families clocks
 
diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c
index 343ee0e6e9b5..764603cc473a 100644
--- a/drivers/clk/clk-stm32f4.c
+++ b/drivers/clk/clk-stm32f4.c
@@ -1659,7 +1659,7 @@ static struct clk_hw *stm32_register_aux_clk(const char *name,
 
 		mux->reg = base + offset_mux;
 		mux->shift = shift;
-		mux->width = hweight8(mask);
+		mux->mask = mask;
 		mux->flags = 0;
 		mux_hw = &mux->hw;
 		mux_ops = &clk_mux_ops;
-- 
2.47.3




             reply	other threads:[~2026-08-31 19:37 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-31 19:35 Ahmad Fatoum [this message]
2026-08-31 19:35 ` [PATCH 2/8] clk: at91: sam9x60-pll: " Ahmad Fatoum
2026-08-31 19:35 ` [PATCH 3/8] clk: composite: return ERR_PTR on registration failure Ahmad Fatoum
2026-08-31 19:35 ` [PATCH 4/8] clk: fixed-factor: use 64-bit arithmetic in recalc_rate Ahmad Fatoum
2026-08-31 19:35 ` [PATCH 5/8] clk: imx: pllv3: use 64-bit arithmetic in fractional PLL recalc_rate Ahmad Fatoum
2026-08-31 19:35 ` [PATCH 6/8] clk: divider: use 64-bit division in _div_round_up and divider_get_val Ahmad Fatoum
2026-08-31 19:35 ` [PATCH 7/8] clk: divider: round up when searching for the best divider Ahmad Fatoum
2026-08-31 19:35 ` [PATCH 8/8] clk: divider: fix calculation of maximal parent rate for a given divider Ahmad Fatoum

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