[PATCH 5/8] clk: imx: pllv3: use 64-bit arithmetic in fractional PLL recalc_rate

[Ahmad Fatoum <a.fatoum@pengutronix.de>]

From: Ahmad Fatoum <a.fatoum@barebox.org>

(parent_rate / mfd) * mfn truncates the intermediate division in
clk_pllv3_av_recalc_rate() and clk_pllv3_sys_vf610_recalc_rate(). Use
u64 multiplication and do_div, as Linux does since commit ba7f4f557eb6
("clk: imx: correct AV PLL rate formula") and 5c2f117a22e4 ("clk: imx:
fix integer overflow in AV PLL round rate"), the latter having widened
the truncated result from u32 to unsigned long.

Fixes: 809549b1bf93 ("ARM i.MX: initial clk support")
Fixes: 7a8d295cdf60 ("i.MX: clk: Add IMX_PLLV3_SYS_VF610 subtype")
Reported-by: Claude:opus-4.6
Signed-off-by: Ahmad Fatoum <a.fatoum@barebox.org>
---
 drivers/clk/imx/clk-pllv3.c | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
index eb806e7f9892..8d41b76df826 100644
--- a/drivers/clk/imx/clk-pllv3.c
+++ b/drivers/clk/imx/clk-pllv3.c
@@ -192,7 +192,12 @@ static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw,
 	u32 mfd = readl(pll->base + PLL_DENOM_OFFSET);
 	u32 div = readl(pll->base) & pll->div_mask;
 
-	return (parent_rate * div) + ((parent_rate / mfd) * mfn);
+	u64 temp64 = (u64)parent_rate;
+
+	temp64 *= mfn;
+	do_div(temp64, mfd);
+
+	return parent_rate * div + (unsigned long)temp64;
 }
 
 static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate,
@@ -293,7 +298,12 @@ static unsigned long clk_pllv3_sys_vf610_recalc_rate(struct clk_hw *hw,
 	u32 mfd = readl(pll->base + SYS_VF610_PLL_OFFSET + PLL_DENOM_OFFSET);
 	u32 div = (readl(pll->base) & pll->div_mask) ? 22 : 20;
 
-	return (parent_rate * div) + ((parent_rate / mfd) * mfn);
+	u64 temp64 = (u64)parent_rate;
+
+	temp64 *= mfn;
+	do_div(temp64, mfd);
+
+	return parent_rate * div + (unsigned long)temp64;
 }
 
 static long clk_pllv3_sys_vf610_round_rate(struct clk_hw *hw, unsigned long rate,
-- 
2.47.3