* [PATCH 0/4] arm: socfpga: iossm: cleanup and fix SDRAM setup
@ 2026-09-03 16:12 Michael Tretter
2026-09-03 16:12 ` [PATCH 1/4] arm: socfpga: iossm: remove unused num_port Michael Tretter
` (4 more replies)
0 siblings, 5 replies; 6+ messages in thread
From: Michael Tretter @ 2026-09-03 16:12 UTC (permalink / raw)
To: Sascha Hauer, BAREBOX; +Cc: Michael Tretter
barebox needs to wait for PLL lock before starting the SDRAM calibration
in the EMIF.
A developer can configure the PLLs that are used for the EMIF at device
configuration time. The SDM firmware writes the configured PLLs into the
handoff data.
Up until now, barebox always waited for the EMIF instance 0 PLL A, which
is likely to be the configured PLL, but actually barebox should wait for
the actually configured PLL.
Patches 1-3 are preparatory cleanup for Patch 4, which actually reads
the configuration from the handoff data and fixes the poll for the PLL
lock.
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
Michael Tretter (4):
arm: socfpga: iossm: remove unused num_port
arm: socfpga: iossm: fix macro
arm: socfpga: iossm: refactor register access
arm: socfpga: iossm: wait for PLL lock from handoff table
arch/arm/mach-socfpga/agilex5-sdram.c | 11 +++---
arch/arm/mach-socfpga/iossm_mailbox.c | 72 ++++++++++++++++++++++++-----------
arch/arm/mach-socfpga/iossm_mailbox.h | 4 +-
3 files changed, 58 insertions(+), 29 deletions(-)
---
base-commit: a59cb95e1133c7f4844c68398c570694d1c7d9ed
change-id: 20260903-socfpga-fix-sdram-setup-60c41664791e
Best regards,
--
Michael Tretter <m.tretter@pengutronix.de>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/4] arm: socfpga: iossm: remove unused num_port
2026-09-03 16:12 [PATCH 0/4] arm: socfpga: iossm: cleanup and fix SDRAM setup Michael Tretter
@ 2026-09-03 16:12 ` Michael Tretter
2026-09-03 16:12 ` [PATCH 2/4] arm: socfpga: iossm: fix macro Michael Tretter
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Michael Tretter @ 2026-09-03 16:12 UTC (permalink / raw)
To: Sascha Hauer, BAREBOX; +Cc: Michael Tretter
The dualport configuration is read from the handoff table and used for
configuration, but num_port is never read or used.
Remove the unused field.
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
arch/arm/mach-socfpga/agilex5-sdram.c | 5 -----
arch/arm/mach-socfpga/iossm_mailbox.c | 5 ++---
arch/arm/mach-socfpga/iossm_mailbox.h | 2 --
3 files changed, 2 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-socfpga/agilex5-sdram.c b/arch/arm/mach-socfpga/agilex5-sdram.c
index fa940958d104..4a28713a3588 100644
--- a/arch/arm/mach-socfpga/agilex5-sdram.c
+++ b/arch/arm/mach-socfpga/agilex5-sdram.c
@@ -98,11 +98,6 @@ static int populate_ddr_handoff(struct altera_sdram_plat *plat, struct io96b_inf
plat->dualport = FIELD_GET(BIT(0), handoff_table[PORT_EMIF_CONFIG_OFFSET]);
pr_debug("%s: dualport from handoff: 0x%x\n", __func__, plat->dualport);
- if (plat->dualport)
- io96b_ctrl->num_port = 2;
- else
- io96b_ctrl->num_port = 1;
-
/* Read handoff - dual EMIF */
plat->dualemif = FIELD_GET(BIT(1), handoff_table[PORT_EMIF_CONFIG_OFFSET]);
pr_debug("%s: dualemif from handoff: 0x%x\n", __func__, plat->dualemif);
diff --git a/arch/arm/mach-socfpga/iossm_mailbox.c b/arch/arm/mach-socfpga/iossm_mailbox.c
index 6a9a7a489b75..b79ec87b4f46 100644
--- a/arch/arm/mach-socfpga/iossm_mailbox.c
+++ b/arch/arm/mach-socfpga/iossm_mailbox.c
@@ -49,7 +49,7 @@ static const char *ddr_type_list[7] = {
"DDR4", "DDR5", "DDR5_RDIMM", "LPDDR4", "LPDDR5", "QDRIV", "UNKNOWN"
};
-static int is_ddr_csr_clkgen_locked(u32 clkgen_mask, u8 num_port)
+static int is_ddr_csr_clkgen_locked(u32 clkgen_mask)
{
int ret;
u32 tmp;
@@ -289,8 +289,7 @@ void io96b_init_mem_cal(struct io96b_info *io96b_ctrl)
count = 0;
for (i = 0; i < io96b_ctrl->num_instance; i++) {
if (io96b_ctrl->ckgen_lock) {
- ret = is_ddr_csr_clkgen_locked(DDR_CSR_CLKGEN_LOCKED_IO96B_MASK(i),
- io96b_ctrl->num_port);
+ ret = is_ddr_csr_clkgen_locked(DDR_CSR_CLKGEN_LOCKED_IO96B_MASK(i));
if (ret) {
pr_err("%s: ckgena_lock iossm IO96B_%d is not locked\n",
__func__, i);
diff --git a/arch/arm/mach-socfpga/iossm_mailbox.h b/arch/arm/mach-socfpga/iossm_mailbox.h
index 0e942a632847..954bfcdf382e 100644
--- a/arch/arm/mach-socfpga/iossm_mailbox.h
+++ b/arch/arm/mach-socfpga/iossm_mailbox.h
@@ -119,7 +119,6 @@ struct io96b_instance {
* @overall_size: Total DDR memory size
* @io96b[]: IO96B instance specific information
* @ckgen_lock: IO96B GEN PLL lock (false = not locked, true = locked)
- * @num_port: Number of IO96B port.
*/
struct io96b_info {
int version;
@@ -131,7 +130,6 @@ struct io96b_info {
phys_size_t overall_size;
struct io96b_instance io96b[MAX_IO96B_SUPPORTED];
bool ckgen_lock;
- u8 num_port;
};
int io96b_mb_req(void __iomem *io96b_csr_addr, u32 ip_type, u32 instance_id,
--
2.47.3
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 2/4] arm: socfpga: iossm: fix macro
2026-09-03 16:12 [PATCH 0/4] arm: socfpga: iossm: cleanup and fix SDRAM setup Michael Tretter
2026-09-03 16:12 ` [PATCH 1/4] arm: socfpga: iossm: remove unused num_port Michael Tretter
@ 2026-09-03 16:12 ` Michael Tretter
2026-09-03 16:12 ` [PATCH 3/4] arm: socfpga: iossm: refactor register access Michael Tretter
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Michael Tretter @ 2026-09-03 16:12 UTC (permalink / raw)
To: Sascha Hauer, BAREBOX; +Cc: Michael Tretter
The argument x of the macro is not used, but the macro uses i instead,
which works, because i is defined, when the macro is used.
Fix this by using the proper argument names.
While at it, simplify the macro and fix the formatting.
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
arch/arm/mach-socfpga/iossm_mailbox.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-socfpga/iossm_mailbox.c b/arch/arm/mach-socfpga/iossm_mailbox.c
index b79ec87b4f46..b66056a91279 100644
--- a/arch/arm/mach-socfpga/iossm_mailbox.c
+++ b/arch/arm/mach-socfpga/iossm_mailbox.c
@@ -18,11 +18,14 @@
#define ECC_INTSTATUS_SERR SOCFPGA_SYSMGR_ADDRESS + 0x9C
#define ECC_INISTATUS_DERR SOCFPGA_SYSMGR_ADDRESS + 0xA0
+
#define DDR_CSR_CLKGEN_LOCKED_IO96B0_MASK BIT(16)
#define DDR_CSR_CLKGEN_LOCKED_IO96B1_MASK BIT(17)
+#define DDR_CSR_CLKGEN_LOCKED_IO96B_MASK(i) \
+ (i == 0 ? \
+ DDR_CSR_CLKGEN_LOCKED_IO96B0_MASK : \
+ DDR_CSR_CLKGEN_LOCKED_IO96B1_MASK)
-#define DDR_CSR_CLKGEN_LOCKED_IO96B_MASK(x) (i == 0 ? DDR_CSR_CLKGEN_LOCKED_IO96B0_MASK : \
- DDR_CSR_CLKGEN_LOCKED_IO96B1_MASK)
#define MAX_RETRY_COUNT 3
#define NUM_CMD_RESPONSE_DATA 3
--
2.47.3
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 3/4] arm: socfpga: iossm: refactor register access
2026-09-03 16:12 [PATCH 0/4] arm: socfpga: iossm: cleanup and fix SDRAM setup Michael Tretter
2026-09-03 16:12 ` [PATCH 1/4] arm: socfpga: iossm: remove unused num_port Michael Tretter
2026-09-03 16:12 ` [PATCH 2/4] arm: socfpga: iossm: fix macro Michael Tretter
@ 2026-09-03 16:12 ` Michael Tretter
2026-09-03 16:12 ` [PATCH 4/4] arm: socfpga: iossm: wait for PLL lock from handoff table Michael Tretter
2026-09-04 9:31 ` [PATCH 0/4] arm: socfpga: iossm: cleanup and fix SDRAM setup Sascha Hauer
4 siblings, 0 replies; 6+ messages in thread
From: Michael Tretter @ 2026-09-03 16:12 UTC (permalink / raw)
To: Sascha Hauer, BAREBOX; +Cc: Michael Tretter
Don't add the base register address when defining the register, but add
it, when the register is accessed. This is how all other accesses to the
SOCFPGA_SYSMGR_ADDRESS are made.
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
arch/arm/mach-socfpga/iossm_mailbox.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-socfpga/iossm_mailbox.c b/arch/arm/mach-socfpga/iossm_mailbox.c
index b66056a91279..28070121ee6b 100644
--- a/arch/arm/mach-socfpga/iossm_mailbox.c
+++ b/arch/arm/mach-socfpga/iossm_mailbox.c
@@ -16,11 +16,11 @@
#include <mach/socfpga/soc64-regs.h>
#include <mach/socfpga/soc64-system-manager.h>
-#define ECC_INTSTATUS_SERR SOCFPGA_SYSMGR_ADDRESS + 0x9C
-#define ECC_INISTATUS_DERR SOCFPGA_SYSMGR_ADDRESS + 0xA0
+#define ECC_INTSTATUS_SERR 0x9C
+#define ECC_INISTATUS_DERR 0xA0
-#define DDR_CSR_CLKGEN_LOCKED_IO96B0_MASK BIT(16)
-#define DDR_CSR_CLKGEN_LOCKED_IO96B1_MASK BIT(17)
+#define DDR_CSR_CLKGEN_LOCKED_IO96B0_MASK BIT(16)
+#define DDR_CSR_CLKGEN_LOCKED_IO96B1_MASK BIT(17)
#define DDR_CSR_CLKGEN_LOCKED_IO96B_MASK(i) \
(i == 0 ? \
DDR_CSR_CLKGEN_LOCKED_IO96B0_MASK : \
@@ -57,7 +57,7 @@ static int is_ddr_csr_clkgen_locked(u32 clkgen_mask)
int ret;
u32 tmp;
- ret = readl_poll_timeout(IOMEM(ECC_INTSTATUS_SERR),
+ ret = readl_poll_timeout(IOMEM(SOCFPGA_SYSMGR_ADDRESS) + ECC_INTSTATUS_SERR,
tmp, tmp & clkgen_mask, 10 * USEC_PER_SEC);
if (ret) {
pr_debug("%s: ddr csr clkgena locked is timeout\n", __func__);
--
2.47.3
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 4/4] arm: socfpga: iossm: wait for PLL lock from handoff table
2026-09-03 16:12 [PATCH 0/4] arm: socfpga: iossm: cleanup and fix SDRAM setup Michael Tretter
` (2 preceding siblings ...)
2026-09-03 16:12 ` [PATCH 3/4] arm: socfpga: iossm: refactor register access Michael Tretter
@ 2026-09-03 16:12 ` Michael Tretter
2026-09-04 9:31 ` [PATCH 0/4] arm: socfpga: iossm: cleanup and fix SDRAM setup Sascha Hauer
4 siblings, 0 replies; 6+ messages in thread
From: Michael Tretter @ 2026-09-03 16:12 UTC (permalink / raw)
To: Sascha Hauer, BAREBOX; +Cc: Michael Tretter
The PLL setting in the handoff table tells barebox, for which PLL it
needs to wait to be locked before configuring the IOSSM.
While at it, fix the typo in the ECC_INTSTATUS_DERR register.
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
arch/arm/mach-socfpga/agilex5-sdram.c | 6 ++++
arch/arm/mach-socfpga/iossm_mailbox.c | 58 +++++++++++++++++++++++++----------
arch/arm/mach-socfpga/iossm_mailbox.h | 2 ++
3 files changed, 50 insertions(+), 16 deletions(-)
diff --git a/arch/arm/mach-socfpga/agilex5-sdram.c b/arch/arm/mach-socfpga/agilex5-sdram.c
index 4a28713a3588..e3c6c414b261 100644
--- a/arch/arm/mach-socfpga/agilex5-sdram.c
+++ b/arch/arm/mach-socfpga/agilex5-sdram.c
@@ -107,6 +107,12 @@ static int populate_ddr_handoff(struct altera_sdram_plat *plat, struct io96b_inf
else
io96b_ctrl->num_instance = 1;
+ /* Read PLL from handoff */
+ io96b_ctrl->selected_plls = FIELD_GET(GENMASK(19, 16),
+ handoff_table[PORT_EMIF_CONFIG_OFFSET]);
+ pr_debug("%s: selected PLLs from handoff: 0x%x\n",
+ __func__, io96b_ctrl->selected_plls);
+
/* Assign IO96B CSR base address if it is valid */
for (i = 0; i < io96b_ctrl->num_instance; i++) {
io96b_ctrl->io96b[i].io96b_csr_addr = IOMEM(io96b_csr_reg_addr[i]);
diff --git a/arch/arm/mach-socfpga/iossm_mailbox.c b/arch/arm/mach-socfpga/iossm_mailbox.c
index 28070121ee6b..2822920ebdf0 100644
--- a/arch/arm/mach-socfpga/iossm_mailbox.c
+++ b/arch/arm/mach-socfpga/iossm_mailbox.c
@@ -17,7 +17,7 @@
#include <mach/socfpga/soc64-system-manager.h>
#define ECC_INTSTATUS_SERR 0x9C
-#define ECC_INISTATUS_DERR 0xA0
+#define ECC_INTSTATUS_DERR 0xA0
#define DDR_CSR_CLKGEN_LOCKED_IO96B0_MASK BIT(16)
#define DDR_CSR_CLKGEN_LOCKED_IO96B1_MASK BIT(17)
@@ -47,21 +47,49 @@
#define IOSSM_MEM_INIT_STATUS_INTF0_OFFSET 0x260
#define IOSSM_MEM_INIT_STATUS_INTF1_OFFSET 0x2E0
+#define IO96B0_PLL_A BIT(0)
+#define IO96B0_PLL_B BIT(1)
+#define IO96B1_PLL_A BIT(2)
+#define IO96B1_PLL_B BIT(3)
+
+static const unsigned int plls[] = {
+ IO96B0_PLL_A, IO96B0_PLL_B, IO96B1_PLL_A, IO96B1_PLL_B
+};
+
+#define IO96B_PLL_REG(pll) \
+ (pll & (IO96B0_PLL_A | IO96B1_PLL_A) ? ECC_INTSTATUS_SERR : ECC_INTSTATUS_DERR)
+#define IO96B_PLL_INSTANCE(pll) \
+ (pll & (IO96B0_PLL_A | IO96B0_PLL_B) ? 0 : 1)
+#define IO96B_PLL_LOCATION(pll) \
+ (pll & (IO96B0_PLL_A | IO96B1_PLL_A) ? "A" : "B")
+
/* supported DDR type list */
static const char *ddr_type_list[7] = {
"DDR4", "DDR5", "DDR5_RDIMM", "LPDDR4", "LPDDR5", "QDRIV", "UNKNOWN"
};
-static int is_ddr_csr_clkgen_locked(u32 clkgen_mask)
+static int io96b_pll_locked_poll_timeout(unsigned int pll)
{
- int ret;
+ u32 mask = DDR_CSR_CLKGEN_LOCKED_IO96B_MASK(IO96B_PLL_INSTANCE(pll));
+ void __iomem *reg = IOMEM(SOCFPGA_SYSMGR_ADDRESS) + IO96B_PLL_REG(pll);
u32 tmp;
- ret = readl_poll_timeout(IOMEM(SOCFPGA_SYSMGR_ADDRESS) + ECC_INTSTATUS_SERR,
- tmp, tmp & clkgen_mask, 10 * USEC_PER_SEC);
- if (ret) {
- pr_debug("%s: ddr csr clkgena locked is timeout\n", __func__);
- return ret;
+ pr_debug("poll for locked PLL: instance %d, location %s\n",
+ IO96B_PLL_INSTANCE(pll), IO96B_PLL_LOCATION(pll));
+ return readl_poll_timeout(reg, tmp, tmp & mask, 10 * USEC_PER_SEC);
+}
+
+static int is_ddr_csr_clkgen_locked(unsigned int selected_plls)
+{
+ int ret;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(plls); i++) {
+ if (!(selected_plls & plls[i]))
+ continue;
+ ret = io96b_pll_locked_poll_timeout(plls[i]);
+ if (ret)
+ return ret;
}
return 0;
@@ -288,17 +316,15 @@ void io96b_init_mem_cal(struct io96b_info *io96b_ctrl)
/* Initialize overall calibration status */
io96b_ctrl->overall_cal_status = false;
+ if (io96b_ctrl->ckgen_lock) {
+ ret = is_ddr_csr_clkgen_locked(io96b_ctrl->selected_plls);
+ if (ret)
+ hang();
+ }
+
/* Check initial calibration status for the assigned IO96B*/
count = 0;
for (i = 0; i < io96b_ctrl->num_instance; i++) {
- if (io96b_ctrl->ckgen_lock) {
- ret = is_ddr_csr_clkgen_locked(DDR_CSR_CLKGEN_LOCKED_IO96B_MASK(i));
- if (ret) {
- pr_err("%s: ckgena_lock iossm IO96B_%d is not locked\n",
- __func__, i);
- hang();
- }
- }
ret = io96b_cal_status(io96b_ctrl->io96b[i].io96b_csr_addr);
if (ret) {
io96b_ctrl->io96b[i].cal_status = false;
diff --git a/arch/arm/mach-socfpga/iossm_mailbox.h b/arch/arm/mach-socfpga/iossm_mailbox.h
index 954bfcdf382e..55c51c2c091c 100644
--- a/arch/arm/mach-socfpga/iossm_mailbox.h
+++ b/arch/arm/mach-socfpga/iossm_mailbox.h
@@ -119,6 +119,7 @@ struct io96b_instance {
* @overall_size: Total DDR memory size
* @io96b[]: IO96B instance specific information
* @ckgen_lock: IO96B GEN PLL lock (false = not locked, true = locked)
+ * @selected_plls: Selected IO96B PLLs
*/
struct io96b_info {
int version;
@@ -130,6 +131,7 @@ struct io96b_info {
phys_size_t overall_size;
struct io96b_instance io96b[MAX_IO96B_SUPPORTED];
bool ckgen_lock;
+ unsigned int selected_plls;
};
int io96b_mb_req(void __iomem *io96b_csr_addr, u32 ip_type, u32 instance_id,
--
2.47.3
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 0/4] arm: socfpga: iossm: cleanup and fix SDRAM setup
2026-09-03 16:12 [PATCH 0/4] arm: socfpga: iossm: cleanup and fix SDRAM setup Michael Tretter
` (3 preceding siblings ...)
2026-09-03 16:12 ` [PATCH 4/4] arm: socfpga: iossm: wait for PLL lock from handoff table Michael Tretter
@ 2026-09-04 9:31 ` Sascha Hauer
4 siblings, 0 replies; 6+ messages in thread
From: Sascha Hauer @ 2026-09-04 9:31 UTC (permalink / raw)
To: BAREBOX, Michael Tretter
On Thu, 03 Sep 2026 18:12:41 +0200, Michael Tretter wrote:
> barebox needs to wait for PLL lock before starting the SDRAM calibration
> in the EMIF.
>
> A developer can configure the PLLs that are used for the EMIF at device
> configuration time. The SDM firmware writes the configured PLLs into the
> handoff data.
>
> [...]
Applied, thanks!
[1/4] arm: socfpga: iossm: remove unused num_port
https://git.pengutronix.de/cgit/barebox/commit/?id=2ca865edd2a1 (link may not be stable)
[2/4] arm: socfpga: iossm: fix macro
https://git.pengutronix.de/cgit/barebox/commit/?id=566ce1d63e32 (link may not be stable)
[3/4] arm: socfpga: iossm: refactor register access
https://git.pengutronix.de/cgit/barebox/commit/?id=a99ea763fb4d (link may not be stable)
[4/4] arm: socfpga: iossm: wait for PLL lock from handoff table
https://git.pengutronix.de/cgit/barebox/commit/?id=cbac8f42939c (link may not be stable)
Best regards,
--
Sascha Hauer <s.hauer@pengutronix.de>
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2026-09-04 9:32 UTC | newest]
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