From: Ahmad Fatoum <a.fatoum@pengutronix.de>
To: barebox@lists.infradead.org
Cc: Ahmad Fatoum <a.fatoum@pengutronix.de>, Abel Vesa <abel.vesa@nxp.com>
Subject: [PATCH 2/4] clk: imx: pll14xx: Drop wrong shifting
Date: Wed, 30 Sep 2026 12:15:54 +0200 [thread overview]
Message-ID: <20260930101606.2097864-2-a.fatoum@pengutronix.de> (raw)
In-Reply-To: <20260930101606.2097864-1-a.fatoum@pengutronix.de>
From: Sascha Hauer <s.hauer@pengutronix.de>
The code tries to mask the bits in SDIV_MASK from 'tmp'. SDIV_MASK
already contains the shifted value, so shifting it again is wrong.
No functional change though as SDIV_SHIFT is zero.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Link: https://lore.kernel.org/r/20220304125256.2125023-3-s.hauer@pengutronix.de
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
[ahmad: cherry-picked from Linux commit d77461a616b659bd88d]
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
drivers/clk/imx/clk-pll14xx.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c
index c1d5a6b88f41..a4aa9ce548cb 100644
--- a/drivers/clk/imx/clk-pll14xx.c
+++ b/drivers/clk/imx/clk-pll14xx.c
@@ -191,7 +191,7 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate,
tmp = readl(pll->base + DIV_CTL0);
if (!clk_pll14xx_mp_change(rate, tmp)) {
- tmp &= ~(SDIV_MASK) << SDIV_SHIFT;
+ tmp &= ~SDIV_MASK;
tmp |= rate->sdiv << SDIV_SHIFT;
writel(tmp, pll->base + DIV_CTL0);
@@ -273,7 +273,7 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate,
tmp = readl(pll->base + DIV_CTL0);
if (!clk_pll14xx_mp_change(rate, tmp)) {
- tmp &= ~(SDIV_MASK) << SDIV_SHIFT;
+ tmp &= ~SDIV_MASK;
tmp |= rate->sdiv << SDIV_SHIFT;
writel(tmp, pll->base + DIV_CTL0);
--
2.47.3
next prev parent reply other threads:[~2026-09-30 10:16 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-30 10:15 [PATCH 1/4] clk: imx: pll14xx: use register defines consistently Ahmad Fatoum
2026-09-30 10:15 ` Ahmad Fatoum [this message]
2026-09-30 10:15 ` [PATCH 3/4] clk: imx: pll14xx: Use FIELD_GET/FIELD_PREP Ahmad Fatoum
2026-09-30 10:15 ` [PATCH 4/4] clk: imx: pll14xx: hit 393216000 and 361267200 Hz exactly Ahmad Fatoum
2026-10-01 20:21 ` [PATCH 1/4] clk: imx: pll14xx: use register defines consistently Sascha Hauer
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