[PATCH] ARM: boards: phytec-som-imx6: Add ADIN1300 PHY fixup

[PATCH] ARM: boards: phytec-som-imx6: Add ADIN1300 PHY fixup

[Florijan Plohl]

From: Stefan Riedmueller <s.riedmueller@phytec.de>

The i.MX 6 requires a ref clock from the PHY when running in RGMII mode.
Since the clock output from the GP_CLK pin is disabled by default on the
ADIN1300 PHY we need a fixup to enable it.

Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
Signed-off-by: Florijan Plohl <florijan.plohl@norik.com>
---
 arch/arm/boards/phytec-som-imx6/board.c | 39 +++++++++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/arch/arm/boards/phytec-som-imx6/board.c b/arch/arm/boards/phytec-som-imx6/board.c
index 7e6f61bc36..22805ad99e 100644
--- a/arch/arm/boards/phytec-som-imx6/board.c
+++ b/arch/arm/boards/phytec-som-imx6/board.c
@@ -45,6 +45,9 @@
 #define DA9062_BUCK4_CFG		0x9f
 #define DA9062_BUCKx_MODE_SYNCHRONOUS	(2 << 6)
 
+#define PHY_ID_ADIN1300			0x0283bc30
+#define ADIN_PHY_ID_MASK		0x0fffffff
+
 static void phyflex_err006282_workaround(void)
 {
 	/*
@@ -99,6 +102,33 @@ static int ksz8081_phy_fixup(struct phy_device *phydev)
 	return 0;
 }
 
+static int adin1300_phy_fixup(struct phy_device *phydev)
+{
+	u16 val;
+	/*
+	 * Enable 125 MHz PHY clock at GP_CLK pin to the ENET_REF_CLK pin
+	 * of the i.MX 6
+	 */
+
+	phy_write(phydev, 0x1c, 0x2109);
+	phy_write(phydev, 0x1b, 0x401);
+	phy_write(phydev, 0x10, 0xff1f);
+	phy_write(phydev, 0x11, 0x28);
+	phy_write(phydev, 0x10, 0xff3c);
+	phy_write(phydev, 0x11, 0x1);
+
+	/*
+	 * Disable advertisement of 100BASE-TX and 1000BASE-T EEE capabilities
+	 * by clearing EEE_100_ADV and EEE_1000_ADV bits in EEE_ADV (0x8001) reg.
+	 */
+	phy_write(phydev, 0x10, 0x8001);
+	val = phy_read(phydev, 0x11);
+	val &= ~(BIT(1) | BIT(2));
+	phy_write(phydev, 0x11, 0x0);
+
+	return 0;
+}
+
 static int phycore_da9062_setup_buck_mode(void)
 {
 	struct i2c_adapter *adapter = NULL;
@@ -180,6 +210,9 @@ static int physom_imx6_probe(struct device *dev)
 		default_environment_path = "/chosen/environment-spinor";
 		default_envdev = "SPI NOR flash";
 
+		phy_register_fixup_for_uid(PHY_ID_ADIN1300, ADIN_PHY_ID_MASK,
+				adin1300_phy_fixup);
+
 		imx6_bbu_internal_mmc_register_handler("mmc2",
 						"/dev/mmc2", 0);
 
@@ -188,6 +221,9 @@ static int physom_imx6_probe(struct device *dev)
 		default_environment_path = "/chosen/environment-nand";
 		default_envdev = "NAND flash";
 
+		phy_register_fixup_for_uid(PHY_ID_ADIN1300, ADIN_PHY_ID_MASK,
+				adin1300_phy_fixup);
+
 		imx6_bbu_internal_mmc_register_handler("mmc2",
 						"/dev/mmc2", 0);
 	} else if (flags & IS_PHYCORE) {
@@ -198,6 +234,9 @@ static int physom_imx6_probe(struct device *dev)
 		default_environment_path = "/chosen/environment-spinor";
 		default_envdev = "SPI NOR flash";
 
+		phy_register_fixup_for_uid(PHY_ID_ADIN1300, ADIN_PHY_ID_MASK,
+				adin1300_phy_fixup);
+
 		imx6_bbu_internal_mmc_register_handler("mmc0",
 						"/dev/mmc0", 0);
 
-- 
2.43.0