[PATCH master 4/5] ARM: i.MX8M: source dram_apb from sys_pll2_200m in early clock init

[Ahmad Fatoum <a.fatoum@pengutronix.de>]

barebox derives the 200MHz dram_apb clock from sys_pll1_800m divided
by 4, while U-Boot's clock_init() selects sys_pll2_200m, which needs
no divider. Let's do the same, so both can be compared side by side.

Move the DRAM clock setup below the code enabling the SYS_PLL2 outputs,
where U-Boot has it as well. This is ordering only: all SYS_PLL2
outputs are enabled at reset already.

No functional change: imx8m_ddr_init() reconfigures DRAM_APB_CLK_ROOT
via ddrphy_init_set_dfi_clk() before the DDRC is first accessed, so
the value set here is overwritten before any register access uses it.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 arch/arm/mach-imx/imx8m.c | 27 +++++++++++++--------------
 1 file changed, 13 insertions(+), 14 deletions(-)

diff --git a/arch/arm/mach-imx/imx8m.c b/arch/arm/mach-imx/imx8m.c
index 66a3b376ed94..23a920ffae2e 100644
--- a/arch/arm/mach-imx/imx8m.c
+++ b/arch/arm/mach-imx/imx8m.c
@@ -59,20 +59,6 @@ static void __imx8m_early_clock_init(int cpu_type)
 	void __iomem *ana = IOMEM(MX8M_ANATOP_BASE_ADDR);
 	u32 val;
 
-	imx8m_ccgr_clock_disable(IMX8M_CCM_CCGR_DDR1);
-
-	imx8m_clock_set_target_val(IMX8M_DRAM_ALT_CLK_ROOT,
-				   IMX8M_CCM_TARGET_ROOTn_ENABLE |
-				   IMX8M_CCM_TARGET_ROOTn_MUX(1));
-
-	/* change the clock source of dram_apb_clk_root: source 4 800MHz /4 = 200MHz */
-	imx8m_clock_set_target_val(IMX8M_DRAM_APB_CLK_ROOT,
-				   IMX8M_CCM_TARGET_ROOTn_ENABLE |
-				   IMX8M_CCM_TARGET_ROOTn_MUX(4) |
-				   IMX8M_CCM_TARGET_ROOTn_POST_DIV(4 - 1));
-
-	imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_DDR1);
-
 	/*
 	 * The gate is not exported to clk tree, so configure them here.
 	 * According to ANAMIX SPEC
@@ -96,6 +82,19 @@ static void __imx8m_early_clock_init(int cpu_type)
 		INTPLL_DIV20_CLKE_MASK;
 	writel(val, ana + IMX8MM_CCM_ANALOG_SYS_PLL2_GEN_CTRL);
 
+	imx8m_ccgr_clock_disable(IMX8M_CCM_CCGR_DDR1);
+
+	imx8m_clock_set_target_val(IMX8M_DRAM_ALT_CLK_ROOT,
+				   IMX8M_CCM_TARGET_ROOTn_ENABLE |
+				   IMX8M_CCM_TARGET_ROOTn_MUX(1));
+
+	/* change the clock source of dram_apb_clk_root: source 1 sys_pll2_200m */
+	imx8m_clock_set_target_val(IMX8M_DRAM_APB_CLK_ROOT,
+				   IMX8M_CCM_TARGET_ROOTn_ENABLE |
+				   IMX8M_CCM_TARGET_ROOTn_MUX(1));
+
+	imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_DDR1);
+
 	if (cpu_type != IMX_CPU_IMX8MP) {
 		/* 8MP ROM already set GIC to 400Mhz, system_pll1_800m with div = 2 */
 		/* For everything else, config GIC to sys_pll2_100m */
-- 
2.47.3