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From: Lucas Stach <l.stach@pengutronix.de>
To: Michael Graichen <michael.graichen@hotmail.com>,
	barebox <barebox@lists.infradead.org>
Subject: Re: [PATCH 1/1] Zynq: add support to chainload another barebox
Date: Wed, 05 May 2021 10:15:52 +0200	[thread overview]
Message-ID: <369badc3290605924915f46e445041dd8e3a0ff1.camel@pengutronix.de> (raw)
In-Reply-To: <AM9P192MB0870CBDAD8B3CC328A1C2D6CAB5B9@AM9P192MB0870.EURP192.PROD.OUTLOOK.COM>

Hi Michael,

Am Montag, dem 03.05.2021 um 10:07 +0000 schrieb Michael Graichen:
> Since OCRAM is only 192K this introduces CONFIG_ZYNQ_BUILD_FSBL so we can can chainload a more feature rich barebox via bootm.
> 
> From 1f1a95eca42198d73c38cc12b9b44f061980cef8 Mon Sep 17 00:00:00 2001
> From: Michael Graichen <michael.graichen@hotmail.com>
> Date: Mon, 3 May 2021 12:03:05 +0200
> Subject: [PATCH] zynq: add support to chainload another barebox

Seems you imported this patch from somewhere and it left some traces in
the commit message?

Also I don't understand what this change is supposed to be doing. You
are building just another Barebox binary, with no real differences in
the configuration. I would much prefer a proper 2-stage loading in the
PBL, but that requires FAT support for the SDcard boot, which I didn't
get around to take a look at yet.

Regards,
Lucas

> Signed-off-by: Michael Graichen <michael.graichen@hotmail.com>
> ---
>  arch/arm/mach-zynq/Kconfig |  6 +++++-
>  images/Makefile.zynq       | 21 +++++++++++++++------
>  2 files changed, 20 insertions(+), 7 deletions(-)
> 
> diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
> index 3e07633e5..0800b55e6 100644
> --- a/arch/arm/mach-zynq/Kconfig
> +++ b/arch/arm/mach-zynq/Kconfig
> @@ -21,7 +21,11 @@ config ARCH_ZYNQ7000
>  	select OFDEVICE
>  	select RELOCATABLE
> 
> -
> +config ZYNQ_BUILD_FSBL
> +	prompt "build FSBL binary (BOOT.BIN)"
> +	bool
> +	help
> +	  Say Y here if you want to build an FSBL binary for the Zynq.
> 
>  menu "select Zynq boards to be built"
> 
> diff --git a/images/Makefile.zynq b/images/Makefile.zynq
> index b00e74869..39c72bd88 100644
> --- a/images/Makefile.zynq
> +++ b/images/Makefile.zynq
> @@ -7,17 +7,26 @@ zynqcfg_cpp_flags  = -Wp,-MD,$(depfile) -nostdinc -x assembler-with-cpp \
> 
>  zynqcfg-tmp = $(subst $(comma),_,$(dot-target).zynqcfg.tmp)
> 
> -quiet_cmd_zynq_image = ZYNQIMG  $@
> +quiet_cmd_zynq_image = ZYNQIMG $@
>        cmd_zynq_image = \
>           $(CPP) $(zynqcfg_cpp_flags) -o $(zynqcfg-tmp) $(CFG_$(@F)) ; \
>           $(objtree)/scripts/zynq_mkimage -c $(zynqcfg-tmp) \
> -           -f $(subst .zynqimg,,$@) -o $@
> +           -f $(subst .zynqimg_fsbl,,$@) -o $@
> 
> -$(obj)/%.zynqimg: $(obj)/% FORCE
> +$(obj)/%.zynqimg_fsbl: $(obj)/% FORCE
>  	$(call if_changed,zynq_image)
> 
>  #------------------------------------------------------------------------------
> 
> -CFG_start_avnet_zedboard.pblb.zynqimg = $(board)/avnet-zedboard/zedboard.zynqcfg
> -FILE_barebox-avnet-zedboard.img = start_avnet_zedboard.pblb.zynqimg
> -image-$(CONFIG_MACH_ZEDBOARD) += barebox-avnet-zedboard.img
> +FILE_barebox-avnet-zedboard.img = start_avnet_zedboard.pblb
> +zynq-barebox-$(CONFIG_MACH_ZEDBOARD) += barebox-avnet-zedboard.img
> +
> +CFG_start_avnet_zedboard.pblb.zynqimg_fsbl = $(board)/avnet-zedboard/zedboard.zynqcfg
> +FILE_barebox-avnet-zedboard-fsbl.img = start_avnet_zedboard.pblb.zynqimg_fsbl
> +zynq-fsbl-$(CONFIG_MACH_ZEDBOARD) += barebox-avnet-zedboard-fsbl.img
> +
> +ifdef CONFIG_ZYNQ_BUILD_FSBL
> +image-y += $(zynq-fsbl-y)
> +else
> +image-y += $(zynq-barebox-y)
> +endif
> --
> 2.25.1
> 
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox



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  reply	other threads:[~2021-05-05  8:17 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-03 10:07 Michael Graichen
2021-05-05  8:15 ` Lucas Stach [this message]
2021-05-05  8:27   ` Ahmad Fatoum
2021-05-05  9:40   ` AW: " Michael Graichen
2021-05-17  8:23     ` Michael Tretter
2021-05-18  8:09       ` AW: " Michael Graichen
2021-05-19  7:38         ` [PATCH 1/2] mci: arasan: wait for data available only on read Michael Tretter
2021-05-19  7:38           ` [PATCH 2/2] mci: arasan: configure data transfer only if we actually have data Michael Tretter
2021-05-25  7:17             ` Sascha Hauer
2021-05-25  7:16           ` [PATCH 1/2] mci: arasan: wait for data available only on read Sascha Hauer

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