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From: Ahmad Fatoum <a.fatoum@pengutronix.de>
To: Renaud Barbier <renaud.barbier@abaco.com>, barebox@lists.infradead.org
Subject: Re: [PATCH 3/3] ls1046ardb: enable IFC NAND.
Date: Mon, 9 Aug 2021 12:49:37 +0200	[thread overview]
Message-ID: <471e6659-459f-f6e6-7abf-9b6141e6c7a3@pengutronix.de> (raw)
In-Reply-To: <1627900804-15814-4-git-send-email-renaud.barbier@abaco.com>

Hello Renaud,

On 02.08.21 12:40, Renaud Barbier wrote:
> Set the NAND timings and enable the IFC NAND driver.
> 
> Signed-off-by: Renaud Barbier <renaud.barbier@abaco.com>
> ---
>  arch/arm/boards/ls1046ardb/board.c    | 42 +++++++++++++++++++++++++++
>  arch/arm/configs/layerscape_defconfig | 11 +++++++
>  2 files changed, 53 insertions(+)
> 
> diff --git a/arch/arm/boards/ls1046ardb/board.c b/arch/arm/boards/ls1046ardb/board.c
> index ef68e9c7f9..b2cfba58a8 100644
> --- a/arch/arm/boards/ls1046ardb/board.c
> +++ b/arch/arm/boards/ls1046ardb/board.c
> @@ -8,10 +8,12 @@
>  #include <fs.h>
>  #include <envfs.h>
>  #include <libfile.h>
> +#include <of_address.h>
>  #include <asm/memory.h>
>  #include <linux/sizes.h>
>  #include <linux/clk.h>
>  #include <linux/clkdev.h>
> +#include <linux/fsl_ifc.h>
>  #include <asm/system.h>
>  #include <mach/layerscape.h>
>  #include <mach/bbu.h>
> @@ -35,6 +37,11 @@ struct nxid {
>  	u32 crc;          /* 0xfc - 0xff CRC32 checksum */
>  } __packed;
>  
> +static const struct of_device_id fsl_ifc_of_ids[] = {
> +	{ .compatible = "fsl,ifc", },
> +	{ },
> +};
> +
>  static int nxid_is_valid(struct nxid *nxid)
>  {
>  	unsigned char id[] = { 'N', 'X', 'I', 'D' };
> @@ -161,3 +168,38 @@ static int rdb_postcore_init(void)
>  }
>  
>  postcore_initcall(rdb_postcore_init);
> +
> +static int rdb_nand_init(void)
> +{
> +	struct device_node *np;
> +	void __iomem *ifc;
> +

If you think this configuration should be done for _all_ boards,
you should move it to arch/arm/mach-layerscape. If you intend it
to be done only for this specific board, you should check the
board compatible, otherwise this function is called even for
boards that don't have NAND physically. Throwing an error
there is inappropriate. If this is board-specific, please add:


	if (!of_machine_is_compatible("fsl,ls1046a-rdb"))

		return 0;

> +	np = of_find_matching_node(NULL, fsl_ifc_of_ids);

You can use of_find_compatible_node, which lets you drop the struct.

> +	if (!np)
> +		return -EINVAL;
> +
> +	ifc = of_iomap(np, 0);
> +	if (!ifc)
> +		return -EINVAL;
> +
> +	set_ifc_cspr(ifc, IFC_CS0, CSPR_PHYS_ADDR(0x7e800000) |
> +			CSPR_PORT_SIZE_8 | CSPR_MSEL_NAND | CSPR_V);
> +	set_ifc_csor(ifc, IFC_CS0, CSOR_NAND_ECC_ENC_EN | CSOR_NAND_ECC_DEC_EN |
> +			CSOR_NAND_ECC_MODE_8 |
> +			CSOR_NAND_RAL_3 | CSOR_NAND_PGS_4K |
> +			CSOR_NAND_SPRZ_224 |  CSOR_NAND_PB(64) |
> +			CSOR_NAND_TRHZ_20);
> +	set_ifc_amask(ifc, IFC_CS0, IFC_AMASK(64*1024));
> +	set_ifc_ftim(ifc, IFC_CS0, IFC_FTIM0, FTIM0_NAND_TCCST(0x07) |
> +			FTIM0_NAND_TWP(0x18) | FTIM0_NAND_TWCHT(0x07) |
> +			FTIM0_NAND_TWH(0x0a));
> +	set_ifc_ftim(ifc, IFC_CS0, IFC_FTIM1, FTIM1_NAND_TADLE(0x32) |
> +			FTIM1_NAND_TWBE(0x39) | FTIM1_NAND_TRR(0x0e)|
> +			FTIM1_NAND_TRP(0x18));
> +	set_ifc_ftim(ifc, IFC_CS0, IFC_FTIM2, FTIM2_NAND_TRAD(0xf) |
> +			FTIM2_NAND_TREH(0xa) | FTIM2_NAND_TWHRE(0x1e));
> +	set_ifc_ftim(ifc, IFC_CS0, IFC_FTIM3, 0);
> +
> +	return 0;
> +}
> +postcore_initcall(rdb_nand_init);
> diff --git a/arch/arm/configs/layerscape_defconfig b/arch/arm/configs/layerscape_defconfig
> index 394cd95c98..fb8e885353 100644
> --- a/arch/arm/configs/layerscape_defconfig
> +++ b/arch/arm/configs/layerscape_defconfig
> @@ -34,6 +34,10 @@ CONFIG_CMD_GO=y
>  CONFIG_CMD_RESET=y
>  CONFIG_CMD_UIMAGE=y
>  CONFIG_CMD_PARTITION=y
> +CONFIG_CMD_MOUNT=y
> +CONFIG_CMD_UBI=y
> +CONFIG_CMD_UBIFORMAT=y
> +CONFIG_CMD_UMOUNT=y
>  CONFIG_CMD_EXPORT=y
>  CONFIG_CMD_LOADENV=y
>  CONFIG_CMD_PRINTENV=y
> @@ -69,6 +73,7 @@ CONFIG_CMD_GPIO=y
>  CONFIG_CMD_I2C=y
>  CONFIG_CMD_LED=y
>  CONFIG_CMD_SPI=y
> +CONFIG_CMD_NAND=y
>  CONFIG_CMD_LED_TRIGGER=y
>  CONFIG_CMD_WD=y
>  CONFIG_CMD_BAREBOX_UPDATE=y
> @@ -85,6 +90,10 @@ CONFIG_DP83867_PHY=y
>  CONFIG_REALTEK_PHY=y
>  CONFIG_NET_DSA_MV88E6XXX=y
>  CONFIG_DRIVER_SPI_FSL_QUADSPI=y
> +CONFIG_NAND=y
> +CONFIG_NAND_FSL_IFC=y
> +CONFIG_MTD_UBI=y
> +CONFIG_MTD_UBI_BEB_LIMIT=20
>  CONFIG_I2C=y
>  CONFIG_I2C_IMX=y
>  CONFIG_I2C_MUX=y
> @@ -112,5 +121,7 @@ CONFIG_FS_NFS=y
>  CONFIG_FS_FAT=y
>  CONFIG_FS_FAT_WRITE=y
>  CONFIG_FS_FAT_LFN=y
> +CONFIG_FS_UBIFS=y
> +CONFIG_FS_UBIFS_COMPRESSION_LZO=y
>  CONFIG_ZLIB=y
>  CONFIG_LZO_DECOMPRESS=y
> 


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  reply	other threads:[~2021-08-09 10:51 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-02 10:40 [PATCH v2 0/3] NXP IFC nand driver Renaud Barbier
2021-08-02 10:40 ` [PATCH 1/3] ARM: atomic.h: add 64-bit counter support Renaud Barbier
2021-08-09 11:01   ` Ahmad Fatoum
2021-08-02 10:40 ` [PATCH 2/3] nand: add NXP IFC nand driver Renaud Barbier
2021-08-09 19:16   ` Sascha Hauer
2021-08-10  8:33     ` Barbier, Renaud
2021-08-02 10:40 ` [PATCH 3/3] ls1046ardb: enable IFC NAND Renaud Barbier
2021-08-09 10:49   ` Ahmad Fatoum [this message]
2021-08-10 10:33     ` Barbier, Renaud
2021-08-13  8:16 [PATCH v3 0/3] NXP IFC nand driver Renaud Barbier
2021-08-13  8:16 ` [PATCH 3/3] ls1046ardb: enable IFC NAND Renaud Barbier
2021-08-23 14:03   ` Sascha Hauer

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