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From: Teresa Remmet <T.Remmet@phytec.de>
To: "barebox@lists.infradead.org" <barebox@lists.infradead.org>,
	"a.fatoum@pengutronix.de" <a.fatoum@pengutronix.de>,
	"lst@pengutronix.de" <lst@pengutronix.de>
Cc: "upstream@phytec.de" <upstream@phytec.de>
Subject: Re: [PATCH] arm: imx: mmdc_size: Increase row_max for imx8m
Date: Mon, 20 Jun 2022 12:47:22 +0000	[thread overview]
Message-ID: <8f346a89044203c38012861a3aa3cf7c63499c96.camel@phytec.de> (raw)
In-Reply-To: <4dbe99f8-0ae7-b24e-9596-2abdce6152f4@pengutronix.de>

Am Montag, dem 20.06.2022 um 14:38 +0200 schrieb Ahmad Fatoum:
> Hello Teresa,
> 
> On 20.06.22 14:27, Teresa Remmet wrote:
> > Hello Ahmad,
> > 
> > Am Montag, dem 20.06.2022 um 14:02 +0200 schrieb Ahmad Fatoum:
> > > Hello,
> > > 
> > > On 20.05.22 16:23, Teresa Remmet wrote:
> > > > As DDRC_ADDRMAP7_ROW_B16 and DDRC_ADDRMAP7_ROW_B17 are used
> > > > now for the row size calculation we need to increase row_max to
> > > > 18.
> > > > 
> > > > For LPDDR4 this only works in combination with ram timings
> > > > created with recent configuration spreadsheet versions.
> > > > With older versions the register DDRC_ADDRMAP7 may not be set
> > > > and
> > > > calculation will lead to wrong results even with this patch.
> > > > 
> > > > Fixes: dad2b5636bd8 ("ARM: imx: Add imx8 support for 18 bit
> > > > SDRAM
> > > > row size handle")
> > > > Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
> > > 
> > > I have an out-of-tree i.MX8MM board with LPDDR4 that reported a
> > > correct size of 1G
> > > prior to this patch and now it reports 4G. DDRC_ADDRMAP7 is not
> > > explicitly initialized,
> > > but it's being read as zero, so the calculation seems to still be
> > > broken..
> > 
> > yes, this is why I added the note to the commit message. The RAM
> > timings of the board you are using have been created with a old
> > version
> > of the spreadsheet ( < version 19 for i.MX8MM).
> > This issue is worked around when this patch is reverted as
> > DDRC_ADDRMAP7 is not taken into account. But calculating big ram
> > sizes
> > will probably not work then.
> > 
> > I have set the DDRC_ADDRMAP7 register manually in the RAM
> > configuration
> > in such a case. As I don't see a solution that fits for all. But
> > would
> > be happy for one. :)
> 
> What would the 'neutral' value to write into this register be? zero
> seems to not be it.

it's 

0xf0f for ADDRMAP7.

Reference Manual says: "If set to 15, row address bit X is set to 0"

Regards,
Teresa


> 
> Thanks,
> Ahmad
> 
> > Regards,
> > Teresa
> > 
> > > > ---
> > > >  arch/arm/mach-imx/esdctl.c | 2 +-
> > > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > > > 
> > > > diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-
> > > > imx/esdctl.c
> > > > index 8dd0ddbbc965..b070ebc62a45 100644
> > > > --- a/arch/arm/mach-imx/esdctl.c
> > > > +++ b/arch/arm/mach-imx/esdctl.c
> > > > @@ -488,7 +488,7 @@ static resource_size_t
> > > > imx8m_ddrc_sdram_size(void __iomem *ddrc)
> > > >  
> > > >  	return imx_ddrc_sdram_size(ddrc, addrmap,
> > > >  				   12, ARRAY_AND_SIZE(col_b),
> > > > -				   16, ARRAY_AND_SIZE(row_b),
> > > > +				   18, ARRAY_AND_SIZE(row_b),
> > > >  				   reduced_adress_space, true);
> > > >  }
> > > >  
> 
> 
-- 
PHYTEC Messtechnik GmbH | Robert-Koch-Str. 39 | 55129 Mainz, Germany

Geschäftsführer: Dipl.-Ing. Michael Mitezki, Dipl.-Ing. Bodo Huber |
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149059855

  reply	other threads:[~2022-06-20 13:12 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-20 14:23 Teresa Remmet
2022-05-24  7:10 ` Sascha Hauer
2022-06-20 12:02 ` Ahmad Fatoum
2022-06-20 12:27   ` Teresa Remmet
2022-06-20 12:38     ` Ahmad Fatoum
2022-06-20 12:47       ` Teresa Remmet [this message]
2022-06-20 13:19         ` Ahmad Fatoum
2022-06-21 12:59           ` Teresa Remmet

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