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From: Ahmad Fatoum <a.fatoum@pengutronix.de>
To: Antony Pavlov <antonynpavlov@gmail.com>, barebox@lists.infradead.org
Subject: Re: [PATCH RESEND v4 1/8] clocksource: timer-riscv: select CSR from device tree
Date: Mon, 23 Aug 2021 14:08:52 +0200
Message-ID: <ce1667b1-e42f-3836-9747-393a5fd8afc7@pengutronix.de> (raw)
In-Reply-To: <20210817101104.114945-2-antonynpavlov@gmail.com>

On 17.08.21 12:10, Antony Pavlov wrote:
> barebox timer-riscv driver supports one of user counters:
> 
>   * 'cycle', counter for RDCYCLE instruction (CSR 0xc00);
>   * 'time', timer for RDTIME instruction (CSR 0xc01).
> 
> At the moment in M-mode timer-riscv uses the 'cycle' counter,
> and in S-mode timer-riscv uses the 'time' timer.
> 
> Alas picorv32 CPU core supports only the 'cycle' counter.
> VexRiscV CPU core in M-mode supports only the 'time' timer.
> 
> This patch makes it possible to use the 'time' timer
> for VexRiscV CPU in M-mode.
> 
> See also http://lists.infradead.org/pipermail/barebox/2021-May/036067.html

Comment from earlier series:

"It also changes the default for M-Mode from cycle to time.

I can't comment on whether this is ok, I just copied the logic

from Linux."

Can you say why this is ok?

> 
> Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
> ---
>  arch/riscv/dts/erizo.dtsi         |  2 ++
>  drivers/clocksource/timer-riscv.c | 24 ++++++++++++------------
>  2 files changed, 14 insertions(+), 12 deletions(-)
> 
> diff --git a/arch/riscv/dts/erizo.dtsi b/arch/riscv/dts/erizo.dtsi
> index 228711bd69..4eb92ae6f1 100644
> --- a/arch/riscv/dts/erizo.dtsi
> +++ b/arch/riscv/dts/erizo.dtsi
> @@ -22,6 +22,8 @@
>  
>  		timebase-frequency = <24000000>;
>  
> +		barebox,csr-cycle;
> +
>  		cpu@0 {
>  			device_type = "cpu";
>  			compatible = "cliffordwolf,picorv32", "riscv";
> diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
> index 5a517fe6b4..96637f988a 100644
> --- a/drivers/clocksource/timer-riscv.c
> +++ b/drivers/clocksource/timer-riscv.c
> @@ -12,9 +12,8 @@
>  #include <clock.h>
>  #include <asm/timer.h>
>  #include <asm/csr.h>
> -#include <asm/system.h>
>  
> -static u64 notrace riscv_timer_get_count_sbi(void)
> +static u64 notrace riscv_timer_get_count_time(void)
>  {
>  	__maybe_unused u32 hi, lo;
>  
> @@ -29,7 +28,7 @@ static u64 notrace riscv_timer_get_count_sbi(void)
>  	return ((u64)hi << 32) | lo;
>  }
>  
> -static u64 notrace riscv_timer_get_count_rdcycle(void)
> +static u64 notrace riscv_timer_get_count_cycle(void)
>  {
>  	__maybe_unused u32 hi, lo;
>  
> @@ -44,24 +43,25 @@ static u64 notrace riscv_timer_get_count_rdcycle(void)
>  	return ((u64)hi << 32) | lo;
>  }
>  
> -static u64 notrace riscv_timer_get_count(void)
> -{
> -	if (riscv_mode() == RISCV_S_MODE)
> -		return riscv_timer_get_count_sbi();
> -	else
> -		return riscv_timer_get_count_rdcycle();
> -}
> -
>  static struct clocksource riscv_clocksource = {
> -	.read		= riscv_timer_get_count,
>  	.mask		= CLOCKSOURCE_MASK(64),
>  	.priority	= 100,
>  };
>  
>  static int riscv_timer_init(struct device_d* dev)
>  {
> +	struct device_node *cpu;
> +
>  	dev_dbg(dev, "running at %lu Hz\n", riscv_timebase);
>  
> +	cpu = of_find_node_by_path("/cpus");
> +
> +	if (of_property_read_bool(cpu, "barebox,csr-cycle")) {
> +		riscv_clocksource.read = riscv_timer_get_count_cycle;
> +	} else {
> +		riscv_clocksource.read = riscv_timer_get_count_time;
> +	}
> +
>  	riscv_clocksource.mult = clocksource_hz2mult(riscv_timebase, riscv_clocksource.shift);
>  
>  	return init_clock(&riscv_clocksource);
> 


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  reply	other threads:[~2021-08-23 12:10 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-17 10:10 [PATCH RESEND v4 0/8] RISC-V: add LiteX SoC support Antony Pavlov
2021-08-17 10:10 ` [PATCH RESEND v4 1/8] clocksource: timer-riscv: select CSR from device tree Antony Pavlov
2021-08-23 12:08   ` Ahmad Fatoum [this message]
2021-08-31  4:07     ` Antony Pavlov
2021-10-01 10:12       ` Ahmad Fatoum
2021-08-17 10:10 ` [PATCH RESEND v4 2/8] serial: add litex UART driver Antony Pavlov
2021-08-23 11:58   ` Ahmad Fatoum
2021-08-17 10:10 ` [PATCH RESEND v4 3/8] console: support set baudrate for fixed baudrate drivers Antony Pavlov
2021-08-23 12:01   ` Ahmad Fatoum
2021-08-17 10:11 ` [PATCH RESEND v4 4/8] gpio: add driver for 74xx-ICs with MMIO access Antony Pavlov
2021-10-01 10:13   ` Ahmad Fatoum
2021-08-17 10:11 ` [PATCH RESEND v4 5/8] spi: add litex spiflash driver Antony Pavlov
2021-08-23 11:57   ` [PATCH] fixup! " Ahmad Fatoum
2021-10-01 10:13   ` [PATCH RESEND v4 5/8] " Ahmad Fatoum
2021-08-17 10:11 ` [PATCH RESEND v4 6/8] net: add LiteEth driver Antony Pavlov
2021-10-01 10:14   ` Ahmad Fatoum
2021-08-17 10:11 ` [PATCH RESEND v4 7/8] RISC-V: add LiteX SoC and linux-on-litex-vexriscv support Antony Pavlov
2021-08-23 12:06   ` Ahmad Fatoum
2021-08-31  4:38     ` Antony Pavlov
2021-10-01 10:21       ` Ahmad Fatoum
2021-08-17 10:11 ` [PATCH RESEND v4 8/8] RISC-V: add litex_linux_defconfig Antony Pavlov
2021-10-01 10:18   ` Ahmad Fatoum
2021-10-04 12:02 ` [PATCH RESEND v4 0/8] RISC-V: add LiteX SoC support Sascha Hauer

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