[PATCH 03/13] clk: mxs: Do not enable enet_out clock

[Sascha Hauer <s.hauer@pengutronix.de>]

The enet_out clock gate is wrongly abstracted. The bit it is controlling
is not just a bit to enable the clock, it also controls the direction of
the ethernet reference clock. When the bit is cleared, the ethernet
reference clock must be fed into the SoC from an external oscillator;
when it's set then the ethernet reference clock is generated internally.
The correct setting depends on the board, so we must not set the bit
unconditionally during probe of the clock driver. Whether or not the
clock is enabled can be selected by the board by removing the clock from
the FEC in its dts.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/clk/mxs/clk-imx28.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/clk/mxs/clk-imx28.c b/drivers/clk/mxs/clk-imx28.c
index 4adb1c6866..aedd8d4a7c 100644
--- a/drivers/clk/mxs/clk-imx28.c
+++ b/drivers/clk/mxs/clk-imx28.c
@@ -131,7 +131,6 @@ static int __init mx28_clocks_init(void __iomem *regs)
 	clk_set_rate(clks[ssp2], 96000000);
 	clk_set_rate(clks[ssp3], 96000000);
 	clk_set_parent(clks[lcdif_sel], clks[ref_pix]);
-	clk_enable(clks[enet_out]);
 
 	clkdev_add_physbase(clks[ssp0], IMX_SSP0_BASE, NULL);
 	clkdev_add_physbase(clks[ssp1], IMX_SSP1_BASE, NULL);
-- 
2.26.2


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