* [PATCH 0/3] RISC-V cycle timer fixes
@ 2021-03-29 22:31 Antony Pavlov
2021-03-29 22:31 ` [PATCH 1/3] clocksource: timer-riscv: adapt riscv_timer_get_count_rdcycle() for RV32 Antony Pavlov
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: Antony Pavlov @ 2021-03-29 22:31 UTC (permalink / raw)
To: barebox; +Cc: Ahmad Fatoum
Antony Pavlov (3):
clocksource: timer-riscv: adapt riscv_timer_get_count_rdcycle() for
RV32
RISC-V: erizo.dtsi: set timebase-frequency = <24000000>
RISC-V: drop old timer handling code
arch/riscv/dts/erizo.dtsi | 2 +
arch/riscv/lib/Makefile | 2 +-
arch/riscv/lib/riscv_timer.c | 63 -------------------------------
drivers/clocksource/timer-riscv.c | 13 +++++--
4 files changed, 13 insertions(+), 67 deletions(-)
delete mode 100644 arch/riscv/lib/riscv_timer.c
--
2.30.1
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* [PATCH 1/3] clocksource: timer-riscv: adapt riscv_timer_get_count_rdcycle() for RV32
2021-03-29 22:31 [PATCH 0/3] RISC-V cycle timer fixes Antony Pavlov
@ 2021-03-29 22:31 ` Antony Pavlov
2021-03-29 22:31 ` [PATCH 2/3] RISC-V: erizo.dtsi: set timebase-frequency = <24000000> Antony Pavlov
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Antony Pavlov @ 2021-03-29 22:31 UTC (permalink / raw)
To: barebox; +Cc: Ahmad Fatoum
On RV64 rdcycle instruction reads 64-bit counter which holds
a count of the number of clock cycles executed by the processor
core.
On RV32 rdcycle instruction reads only bits 31-0 of the same
counter; RDCYCLEH should be used to read bits 63–32.
The code of this patch is based on Figure 2.5: 'Sample code
for reading the 64-bit cycle counter in RV32' [1]:
again:
rdcycleh x3
rdcycle x2
rdcycleh x4
bne x3, x4, again
[1] The RISC-V Instruction Set Manual. Volume I:
User-Level ISA, Document Version 2.2
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
drivers/clocksource/timer-riscv.c | 13 ++++++++++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
index eb5ba2d8c2..ef67cff475 100644
--- a/drivers/clocksource/timer-riscv.c
+++ b/drivers/clocksource/timer-riscv.c
@@ -30,10 +30,17 @@ static u64 notrace riscv_timer_get_count_sbi(void)
static u64 notrace riscv_timer_get_count_rdcycle(void)
{
- u64 ticks;
- asm volatile("rdcycle %0" : "=r" (ticks));
+ __maybe_unused u32 hi, lo;
- return ticks;
+ if (IS_ENABLED(CONFIG_64BIT))
+ return csr_read(CSR_CYCLE);
+
+ do {
+ hi = csr_read(CSR_CYCLEH);
+ lo = csr_read(CSR_CYCLE);
+ } while (hi != csr_read(CSR_CYCLEH));
+
+ return ((u64)hi << 32) | lo;
}
static u64 notrace riscv_timer_get_count(void)
--
2.30.1
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* [PATCH 2/3] RISC-V: erizo.dtsi: set timebase-frequency = <24000000>
2021-03-29 22:31 [PATCH 0/3] RISC-V cycle timer fixes Antony Pavlov
2021-03-29 22:31 ` [PATCH 1/3] clocksource: timer-riscv: adapt riscv_timer_get_count_rdcycle() for RV32 Antony Pavlov
@ 2021-03-29 22:31 ` Antony Pavlov
2021-03-29 22:31 ` [PATCH 3/3] RISC-V: drop old timer handling code Antony Pavlov
2021-03-30 5:36 ` [PATCH 0/3] RISC-V cycle timer fixes Sascha Hauer
3 siblings, 0 replies; 5+ messages in thread
From: Antony Pavlov @ 2021-03-29 22:31 UTC (permalink / raw)
To: barebox; +Cc: Ahmad Fatoum
This patch makes it possible to use drivers/clocksource/timer-riscv.c
with erizo. Without timebase-frequency initialized we have
this warning at startup:
RISC-V system with no 'timebase-frequency' in DTS
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
arch/riscv/dts/erizo.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/riscv/dts/erizo.dtsi b/arch/riscv/dts/erizo.dtsi
index e854a48ae5..228711bd69 100644
--- a/arch/riscv/dts/erizo.dtsi
+++ b/arch/riscv/dts/erizo.dtsi
@@ -20,6 +20,8 @@
#address-cells = <1>;
#size-cells = <0>;
+ timebase-frequency = <24000000>;
+
cpu@0 {
device_type = "cpu";
compatible = "cliffordwolf,picorv32", "riscv";
--
2.30.1
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* [PATCH 3/3] RISC-V: drop old timer handling code
2021-03-29 22:31 [PATCH 0/3] RISC-V cycle timer fixes Antony Pavlov
2021-03-29 22:31 ` [PATCH 1/3] clocksource: timer-riscv: adapt riscv_timer_get_count_rdcycle() for RV32 Antony Pavlov
2021-03-29 22:31 ` [PATCH 2/3] RISC-V: erizo.dtsi: set timebase-frequency = <24000000> Antony Pavlov
@ 2021-03-29 22:31 ` Antony Pavlov
2021-03-30 5:36 ` [PATCH 0/3] RISC-V cycle timer fixes Sascha Hauer
3 siblings, 0 replies; 5+ messages in thread
From: Antony Pavlov @ 2021-03-29 22:31 UTC (permalink / raw)
To: barebox; +Cc: Ahmad Fatoum
Use drivers/clocksource/timer-riscv.c driver introduced in
'2ee369dcf7a5 ("clocksource: add driver for RISC-V and CLINT
timers")' instead.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
arch/riscv/lib/Makefile | 2 +-
arch/riscv/lib/riscv_timer.c | 63 ------------------------------------
2 files changed, 1 insertion(+), 64 deletions(-)
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index a9bf68bca5..a4eaa1005d 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -2,7 +2,7 @@
extra-y += barebox.lds
-obj-y += riscv_timer.o dtb.o
+obj-y += dtb.o
obj-pbl-y += sections.o setupc.o reloc.o sections.o runtime-offset.o
obj-$(CONFIG_HAS_ARCH_SJLJ) += setjmp.o longjmp.o
obj-$(CONFIG_RISCV_OPTIMZED_STRING_FUNCTIONS) += memcpy.o memset.o memmove.o
diff --git a/arch/riscv/lib/riscv_timer.c b/arch/riscv/lib/riscv_timer.c
deleted file mode 100644
index 919d77d4b5..0000000000
--- a/arch/riscv/lib/riscv_timer.c
+++ /dev/null
@@ -1,63 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2017 Antony Pavlov <antonynpavlov@gmail.com>
- *
- * This file is part of barebox.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-/**
- * @file
- * @brief Clocksource based on RISC-V cycle CSR timer
- */
-
-#include <init.h>
-#include <of.h>
-#include <linux/clk.h>
-#include <clock.h>
-
-static uint64_t rdcycle_read(void)
-{
- register unsigned long __v;
-
- __asm__ __volatile__ ("rdcycle %0" : "=r" (__v));
-
- return __v;
-}
-
-static struct clocksource rdcycle_cs = {
- .read = rdcycle_read,
- .mask = CLOCKSOURCE_MASK(32),
-};
-
-static int rdcycle_cs_init(void)
-{
- unsigned int cycle_frequency;
-
- /* default rate: 100 MHz */
- cycle_frequency = 100000000;
-
- if (IS_ENABLED(CONFIG_OFTREE)) {
- struct device_node *np;
- struct clk *clk;
-
- np = of_get_cpu_node(0, NULL);
- if (np) {
- clk = of_clk_get(np, 0);
- if (!IS_ERR(clk)) {
- cycle_frequency = clk_get_rate(clk);
- }
- }
- }
-
- clocks_calc_mult_shift(&rdcycle_cs.mult, &rdcycle_cs.shift,
- cycle_frequency, NSEC_PER_SEC, 10);
-
- return init_clock(&rdcycle_cs);
-}
-postcore_initcall(rdcycle_cs_init);
--
2.30.1
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^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 0/3] RISC-V cycle timer fixes
2021-03-29 22:31 [PATCH 0/3] RISC-V cycle timer fixes Antony Pavlov
` (2 preceding siblings ...)
2021-03-29 22:31 ` [PATCH 3/3] RISC-V: drop old timer handling code Antony Pavlov
@ 2021-03-30 5:36 ` Sascha Hauer
3 siblings, 0 replies; 5+ messages in thread
From: Sascha Hauer @ 2021-03-30 5:36 UTC (permalink / raw)
To: Antony Pavlov; +Cc: barebox, Ahmad Fatoum
On Tue, Mar 30, 2021 at 01:31:17AM +0300, Antony Pavlov wrote:
> Antony Pavlov (3):
> clocksource: timer-riscv: adapt riscv_timer_get_count_rdcycle() for
> RV32
> RISC-V: erizo.dtsi: set timebase-frequency = <24000000>
> RISC-V: drop old timer handling code
>
Applied, thanks
Sascha
> arch/riscv/dts/erizo.dtsi | 2 +
> arch/riscv/lib/Makefile | 2 +-
> arch/riscv/lib/riscv_timer.c | 63 -------------------------------
> drivers/clocksource/timer-riscv.c | 13 +++++--
> 4 files changed, 13 insertions(+), 67 deletions(-)
> delete mode 100644 arch/riscv/lib/riscv_timer.c
>
> --
> 2.30.1
>
>
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Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
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2021-03-29 22:31 [PATCH 0/3] RISC-V cycle timer fixes Antony Pavlov
2021-03-29 22:31 ` [PATCH 1/3] clocksource: timer-riscv: adapt riscv_timer_get_count_rdcycle() for RV32 Antony Pavlov
2021-03-29 22:31 ` [PATCH 2/3] RISC-V: erizo.dtsi: set timebase-frequency = <24000000> Antony Pavlov
2021-03-29 22:31 ` [PATCH 3/3] RISC-V: drop old timer handling code Antony Pavlov
2021-03-30 5:36 ` [PATCH 0/3] RISC-V cycle timer fixes Sascha Hauer
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