From: Sascha Hauer <sha@pengutronix.de>
To: Ahmad Fatoum <a.fatoum@pengutronix.de>
Cc: barebox@lists.infradead.org, rcz@pengutronix.de
Subject: Re: [PATCH 11/12] net: macb: add SiFive support
Date: Mon, 17 May 2021 08:39:24 +0200 [thread overview]
Message-ID: <20210517063924.GE31738@pengutronix.de> (raw)
In-Reply-To: <20210427202309.32077-11-a.fatoum@pengutronix.de>
On Tue, Apr 27, 2021 at 10:23:08PM +0200, Ahmad Fatoum wrote:
> The Ethernet controller on the SiFive SoCs needs some special TX clock
> setup. Port the relevant Linux v5.12 bits to enable it.
>
> Tested on qemu-system-riscv64 -M sifive_u with dhcp.
>
> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> ---
> drivers/net/macb.c | 113 +++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 113 insertions(+)
>
> diff --git a/drivers/net/macb.c b/drivers/net/macb.c
> index 14a0b45322bf..9c4fdbd5bc4f 100644
> --- a/drivers/net/macb.c
> +++ b/drivers/net/macb.c
> @@ -52,6 +52,17 @@
> #define TX_RING_BYTES (sizeof(struct macb_dma_desc) * TX_RING_SIZE)
> #define GEM_Q1_DESC_BYTES (sizeof(struct macb_dma_desc) * GEM_Q1_DESCS)
>
> +/* This structure is only used for MACB on SiFive FU540 devices */
> +struct sifive_fu540_macb_mgmt {
> + void __iomem *reg;
> + unsigned long rate;
> + struct clk clk;
> +};
> +
> +struct macb_config {
> + int (*txclk_init)(struct device_d *dev, struct clk **tx_clk);
> +};
> +
> struct macb_device {
> void __iomem *regs;
>
> @@ -666,12 +677,101 @@ static void macb_init_rx_buffer_size(struct macb_device *bp, size_t size)
> size, bp->rx_buffer_size);
> }
>
> +static struct sifive_fu540_macb_mgmt *mgmt;
> +
> +static unsigned long fu540_macb_tx_recalc_rate(struct clk *clk,
> + unsigned long parent_rate)
> +{
> + return mgmt->rate;
> +}
Unfortunately I had to drop this one. The macb driver is used by some of
the old at91 configs which have their own clk implementation. Among
other things there is no recalc_rate hook.
Can we place the clk code inside a #ifdef CONFIG_COMMON_CLK?
Sascha
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next prev parent reply other threads:[~2021-05-17 6:41 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-27 20:22 [PATCH 01/12] clk: add SiFive PRCI clock controller support Ahmad Fatoum
2021-04-27 20:22 ` [PATCH 02/12] serial: implement SiFive UART support Ahmad Fatoum
2021-04-27 20:23 ` [PATCH 03/12] debug_ll: support <asm/debug_ll.h> to get rid of mach directories Ahmad Fatoum
2021-04-27 20:23 ` [PATCH 04/12] RISC-V: support multi-image for all machines Ahmad Fatoum
2021-05-03 11:33 ` Sascha Hauer
2021-05-03 11:39 ` Ahmad Fatoum
2021-05-03 12:00 ` Sascha Hauer
2021-04-27 20:23 ` [PATCH 05/12] RISC-V: erizo: restrict to RV32I Ahmad Fatoum
2021-04-27 20:23 ` [PATCH 06/12] RISC-V: erizo: drop mach-erizo directory Ahmad Fatoum
2021-05-05 10:18 ` Antony Pavlov
2021-05-05 10:21 ` Ahmad Fatoum
2021-05-07 11:27 ` Antony Pavlov
2021-04-27 20:23 ` [PATCH 07/12] RISC-V: add SBI based cpuinfo Ahmad Fatoum
2021-04-27 20:23 ` [PATCH 08/12] gpio: gpio-generic-platform: remove unused non-DT support Ahmad Fatoum
2021-04-27 20:23 ` [PATCH 09/12] gpio: generic: sync with upstream Linux gpio-mmio driver Ahmad Fatoum
2021-05-06 23:45 ` Antony Pavlov
2021-04-27 20:23 ` [PATCH 10/12] gpio: add SiFive GPIO controller support Ahmad Fatoum
2021-04-27 20:23 ` [PATCH 11/12] net: macb: add SiFive support Ahmad Fatoum
2021-05-17 6:39 ` Sascha Hauer [this message]
2021-04-27 20:23 ` [PATCH 12/12] RISC-V: sifive: add HiFive board support Ahmad Fatoum
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