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From: Ahmad Fatoum <a.fatoum@pengutronix.de>
To: barebox@lists.infradead.org
Cc: Ahmad Fatoum <a.fatoum@pengutronix.de>
Subject: [PATCH 06/20] RISC-V: dma: support multiple dma_alloc_coherent backends
Date: Mon, 31 May 2021 09:38:07 +0200
Message-ID: <20210531073821.15257-7-a.fatoum@pengutronix.de> (raw)
In-Reply-To: <20210531073821.15257-1-a.fatoum@pengutronix.de>

StarFive JH7100 has uncached DDR region at 64G, but Designware MAC v3.70
has 32-bit DMA mask. There's internal RAM in first 4G that's uncached,
which we could use as backing store for dma_alloc_coherent.

Rework code, so SoC specific code can define own implementation.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 arch/riscv/cpu/Makefile        |  2 +
 arch/riscv/cpu/cache.c         | 22 +++++++++++
 arch/riscv/cpu/dma.c           | 69 ++++++++++++++++++++++++++++++++++
 arch/riscv/include/asm/cache.h | 17 +++++++++
 arch/riscv/include/asm/dma.h   | 42 +++++----------------
 5 files changed, 119 insertions(+), 33 deletions(-)
 create mode 100644 arch/riscv/cpu/cache.c
 create mode 100644 arch/riscv/cpu/dma.c
 create mode 100644 arch/riscv/include/asm/cache.h

diff --git a/arch/riscv/cpu/Makefile b/arch/riscv/cpu/Makefile
index f1312be699a1..e521ca4bfd47 100644
--- a/arch/riscv/cpu/Makefile
+++ b/arch/riscv/cpu/Makefile
@@ -1,3 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0
 
 obj-y += core.o time.o
+obj-$(CONFIG_HAS_CACHE) += cache.o
+obj-$(CONFIG_HAS_DMA) += dma.o
diff --git a/arch/riscv/cpu/cache.c b/arch/riscv/cpu/cache.c
new file mode 100644
index 000000000000..d5aad7e4038b
--- /dev/null
+++ b/arch/riscv/cpu/cache.c
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#include <asm/cache.h>
+
+static struct cache_ops *cache_ops;
+
+void __dma_flush_range(dma_addr_t start, dma_addr_t end)
+{
+	if (cache_ops)
+		cache_ops->dma_flush_range(start, end);
+}
+
+void __dma_inv_range(dma_addr_t start, dma_addr_t end)
+{
+	if (cache_ops)
+		cache_ops->dma_inv_range(start, end);
+}
+
+void riscv_cache_set_ops(struct cache_ops *ops)
+{
+	cache_ops = ops;
+}
diff --git a/arch/riscv/cpu/dma.c b/arch/riscv/cpu/dma.c
new file mode 100644
index 000000000000..d7dc642f5830
--- /dev/null
+++ b/arch/riscv/cpu/dma.c
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#include <common.h>
+#include <xfuncs.h>
+#include <asm/dma.h>
+#include <asm/cache.h>
+#include <malloc.h>
+
+static void *__dma_alloc_coherent(size_t size, dma_addr_t *dma_handle)
+{
+	void *ret;
+
+	ret = xmemalign(PAGE_SIZE, size);
+
+	memset(ret, 0, size);
+
+	if (dma_handle)
+		*dma_handle = (dma_addr_t)ret;
+
+	return ret;
+}
+
+static void __dma_free_coherent(void *vaddr, dma_addr_t dma_handle, size_t size)
+{
+	free(vaddr);
+}
+
+static const struct dma_coherent_ops nommu_ops = {
+	.alloc = __dma_alloc_coherent,
+	.free = __dma_free_coherent,
+};
+
+static const struct dma_coherent_ops *dma_coherent_ops = &nommu_ops;
+
+void *dma_alloc_coherent(size_t size, dma_addr_t *dma_handle)
+{
+	return dma_coherent_ops->alloc(size, dma_handle);
+}
+
+void dma_free_coherent(void *vaddr, dma_addr_t dma_handle, size_t size)
+{
+	dma_coherent_ops->free(vaddr, dma_handle, size);
+}
+
+void dma_set_coherent_ops(const struct dma_coherent_ops *ops)
+{
+	dma_coherent_ops = ops;
+}
+
+void dma_sync_single_for_cpu(dma_addr_t address, size_t size, enum dma_data_direction dir)
+{
+        /*
+         * FIXME: This function needs a device argument to support non 1:1 mappings
+         */
+        if (dir != DMA_TO_DEVICE)
+                __dma_inv_range(address, address + size);
+}
+
+void dma_sync_single_for_device(dma_addr_t address, size_t size, enum dma_data_direction dir)
+{
+        /*
+         * FIXME: This function needs a device argument to support non 1:1 mappings
+         */
+
+        if (dir == DMA_FROM_DEVICE)
+                __dma_inv_range(address, address + size);
+        else
+                __dma_flush_range(address, address + size);
+}
diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h
new file mode 100644
index 000000000000..a1cdd6b13b62
--- /dev/null
+++ b/arch/riscv/include/asm/cache.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_CACHE_H
+#define __ASM_CACHE_H
+
+#include <linux/types.h>
+
+struct cache_ops {
+	void (*dma_flush_range)(dma_addr_t start, dma_addr_t end);
+	void (*dma_inv_range)(dma_addr_t start, dma_addr_t end);
+};
+
+void __dma_flush_range(dma_addr_t start, dma_addr_t end);
+void __dma_inv_range(dma_addr_t start, dma_addr_t end);
+
+void riscv_cache_set_ops(struct cache_ops *ops);
+
+#endif
diff --git a/arch/riscv/include/asm/dma.h b/arch/riscv/include/asm/dma.h
index 4204653984a3..b880e49732e0 100644
--- a/arch/riscv/include/asm/dma.h
+++ b/arch/riscv/include/asm/dma.h
@@ -2,43 +2,19 @@
 #ifndef _ASM_DMA_MAPPING_H
 #define _ASM_DMA_MAPPING_H
 
-#include <common.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
 #include <xfuncs.h>
-#include <linux/build_bug.h>
-#include <malloc.h>
 
-#ifdef CONFIG_MMU
-#error DMA stubs need be replaced when using MMU and caches
-#endif
+struct dma_coherent_ops {
+	void *(*alloc)(size_t size, dma_addr_t *dma_handle);
 
-static inline void *dma_alloc_coherent(size_t size, dma_addr_t *dma_handle)
-{
-	void *ret;
+	void (*free)(void *vaddr, dma_addr_t dma_handle, size_t size);
+};
 
-	ret = xmemalign(PAGE_SIZE, size);
+void dma_set_coherent_ops(const struct dma_coherent_ops *ops);
+#define DMA_ALIGNMENT 64
 
-	memset(ret, 0, size);
-
-	if (dma_handle)
-		*dma_handle = (dma_addr_t)ret;
-
-	return ret;
-}
-
-static inline void dma_free_coherent(void *vaddr, dma_addr_t dma_handle,
-				     size_t size)
-{
-	free(vaddr);
-}
-
-static inline void dma_sync_single_for_cpu(dma_addr_t address, size_t size,
-					   enum dma_data_direction dir)
-{
-}
-
-static inline void dma_sync_single_for_device(dma_addr_t address, size_t size,
-					      enum dma_data_direction dir)
-{
-}
+#include <dma.h>
 
 #endif /* _ASM_DMA_MAPPING_H */
-- 
2.29.2


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  parent reply	other threads:[~2021-05-31  7:40 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-31  7:38 [PATCH 00/20] RISC-V: prepare for BeagleV pre-production board support Ahmad Fatoum
2021-05-31  7:38 ` [PATCH 01/20] RISC-V: socs: add Kconfig entry for StarFive JH7100 Ahmad Fatoum
2021-05-31  7:38 ` [PATCH 02/20] net: designware: add support for IP integrated into StarFive SoC Ahmad Fatoum
2021-05-31  7:38 ` [PATCH 03/20] mfd: add TI TPS65086 PMIC restart driver Ahmad Fatoum
2021-06-07  6:44   ` Sascha Hauer
2021-05-31  7:38 ` [PATCH 04/20] mtd: spi-nor: cadence: fix 64-bit issues Ahmad Fatoum
2021-06-07  6:51   ` Sascha Hauer
2021-05-31  7:38 ` [PATCH 05/20] nvmem: add StarFive OTP support Ahmad Fatoum
2021-05-31  7:38 ` Ahmad Fatoum [this message]
2021-05-31  7:38 ` [PATCH 07/20] RISC-V: support incoherent I-Cache Ahmad Fatoum
2021-05-31  7:40   ` Ahmad Fatoum
2021-06-07  7:33     ` Ahmad Fatoum
2021-05-31  7:38 ` [PATCH 08/20] soc: add support for StarFive JH7100 incoherent interconnect Ahmad Fatoum
2021-05-31  7:38 ` [PATCH 09/20] soc: sifive: l2_cache: enable maximum available cache ways Ahmad Fatoum
2021-05-31  7:38 ` [PATCH 10/20] net: designware: fix 64-bit incompatibilities Ahmad Fatoum
2021-05-31  7:38 ` [PATCH 11/20] dma: support marking SRAM for coherent DMA use Ahmad Fatoum
2021-06-07  7:34   ` Sascha Hauer
2021-06-07  7:40     ` Ahmad Fatoum
2021-06-07  7:39   ` Sascha Hauer
2021-05-31  7:38 ` [PATCH 12/20] mci: allocate DMA-able memory Ahmad Fatoum
2021-05-31  7:38 ` [PATCH 13/20] mci: allocate sector_buf on demand Ahmad Fatoum
2021-05-31  7:38 ` [PATCH 14/20] dma: allocate 32-byte aligned buffers by default Ahmad Fatoum
2021-05-31  7:38 ` [PATCH 15/20] mci: dw_mmc: enable use on 64-bit CPUs Ahmad Fatoum
2021-05-31  7:38 ` [PATCH 16/20] mci: dw_mmc: match against generic "snps, dw-mshc" compatible Ahmad Fatoum
2021-05-31  7:38 ` [PATCH 17/20] clk: add initial StarFive clock support Ahmad Fatoum
2021-05-31  8:41   ` Ahmad Fatoum
2021-05-31  7:38 ` [PATCH 18/20] reset: add StarFive reset controller driver Ahmad Fatoum
2021-06-07  8:00   ` Sascha Hauer
2021-05-31  7:38 ` [PATCH 19/20] watchdog: add StarFive watchdog driver Ahmad Fatoum
2021-05-31  7:38 ` [PATCH 20/20] hw_random: add driver for RNG on StarFive SoC Ahmad Fatoum

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