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From: Sascha Hauer <sha@pengutronix.de>
To: Ahmad Fatoum <a.fatoum@pengutronix.de>
Cc: barebox@lists.infradead.org
Subject: Re: [PATCH 11/20] dma: support marking SRAM for coherent DMA use
Date: Mon, 7 Jun 2021 09:39:25 +0200
Message-ID: <20210607073925.GF26174@pengutronix.de> (raw)
In-Reply-To: <20210531073821.15257-12-a.fatoum@pengutronix.de>

On Mon, May 31, 2021 at 09:38:12AM +0200, Ahmad Fatoum wrote:
> The RISC-V architecture allows overriding the dma_alloc_coherent and
> dma_free_coherent. Allow this to be controlled by device tree.
> 
> Cache-coherent SoCs won't need this, but incoherent ones that have
> uncached regions can register them here.
> 
> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> ---
>  common/Kconfig              |   4 ++
>  common/Makefile             |   3 +-
>  drivers/dma/Kconfig         |   6 ++
>  drivers/dma/Makefile        |   1 +
>  drivers/dma/coherent-pool.c | 120 ++++++++++++++++++++++++++++++++++++
>  5 files changed, 133 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/dma/coherent-pool.c
> 
> diff --git a/common/Kconfig b/common/Kconfig
> index ce349d4ebbf6..dbbcbb946fff 100644
> --- a/common/Kconfig
> +++ b/common/Kconfig
> @@ -303,6 +303,9 @@ config EXPERIMENTAL
>  	bool
>  	prompt "Prompt for experimental code"
>  
> +config TLSF
> +	bool
> +
>  choice
>  	prompt "malloc implementation"
>  
> @@ -311,6 +314,7 @@ config MALLOC_DLMALLOC
>  
>  config MALLOC_TLSF
>  	bool "tlsf"
> +	select TLSF
>  
>  config MALLOC_DUMMY
>  	bool "dummy malloc"
> diff --git a/common/Makefile b/common/Makefile
> index 382a4f661f67..0777d2030c99 100644
> --- a/common/Makefile
> +++ b/common/Makefile
> @@ -40,7 +40,8 @@ obj-$(CONFIG_GLOBALVAR)		+= globalvar.o
>  obj-$(CONFIG_GREGORIAN_CALENDER) += date.o
>  obj-$(CONFIG_KALLSYMS)		+= kallsyms.o
>  obj-$(CONFIG_MALLOC_DLMALLOC)	+= dlmalloc.o
> -obj-$(CONFIG_MALLOC_TLSF)	+= tlsf_malloc.o tlsf.o calloc.o
> +obj-$(CONFIG_TLSF)		+= tlsf.o
> +obj-$(CONFIG_MALLOC_TLSF)	+= tlsf_malloc.o calloc.o
>  KASAN_SANITIZE_tlsf.o := n
>  obj-$(CONFIG_MALLOC_DUMMY)	+= dummy_malloc.o calloc.o
>  obj-$(CONFIG_MEMINFO)		+= meminfo.o
> diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
> index c75fc8b9811f..6bc915585fbe 100644
> --- a/drivers/dma/Kconfig
> +++ b/drivers/dma/Kconfig
> @@ -1,5 +1,11 @@
>  menu "DMA support"
>  
> +config DMA_COHERENT_POOLS
> +	bool
> +	depends on RISCV
> +	select TLSF
> +	imply SRAM

This symbol is invisible and selected when needed. We shouldn't need
this "depends on RISCV"

Sascha

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  parent reply	other threads:[~2021-06-07  7:41 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-31  7:38 [PATCH 00/20] RISC-V: prepare for BeagleV pre-production board support Ahmad Fatoum
2021-05-31  7:38 ` [PATCH 01/20] RISC-V: socs: add Kconfig entry for StarFive JH7100 Ahmad Fatoum
2021-05-31  7:38 ` [PATCH 02/20] net: designware: add support for IP integrated into StarFive SoC Ahmad Fatoum
2021-05-31  7:38 ` [PATCH 03/20] mfd: add TI TPS65086 PMIC restart driver Ahmad Fatoum
2021-06-07  6:44   ` Sascha Hauer
2021-05-31  7:38 ` [PATCH 04/20] mtd: spi-nor: cadence: fix 64-bit issues Ahmad Fatoum
2021-06-07  6:51   ` Sascha Hauer
2021-05-31  7:38 ` [PATCH 05/20] nvmem: add StarFive OTP support Ahmad Fatoum
2021-05-31  7:38 ` [PATCH 06/20] RISC-V: dma: support multiple dma_alloc_coherent backends Ahmad Fatoum
2021-05-31  7:38 ` [PATCH 07/20] RISC-V: support incoherent I-Cache Ahmad Fatoum
2021-05-31  7:40   ` Ahmad Fatoum
2021-06-07  7:33     ` Ahmad Fatoum
2021-05-31  7:38 ` [PATCH 08/20] soc: add support for StarFive JH7100 incoherent interconnect Ahmad Fatoum
2021-05-31  7:38 ` [PATCH 09/20] soc: sifive: l2_cache: enable maximum available cache ways Ahmad Fatoum
2021-05-31  7:38 ` [PATCH 10/20] net: designware: fix 64-bit incompatibilities Ahmad Fatoum
2021-05-31  7:38 ` [PATCH 11/20] dma: support marking SRAM for coherent DMA use Ahmad Fatoum
2021-06-07  7:34   ` Sascha Hauer
2021-06-07  7:40     ` Ahmad Fatoum
2021-06-07  7:39   ` Sascha Hauer [this message]
2021-05-31  7:38 ` [PATCH 12/20] mci: allocate DMA-able memory Ahmad Fatoum
2021-05-31  7:38 ` [PATCH 13/20] mci: allocate sector_buf on demand Ahmad Fatoum
2021-05-31  7:38 ` [PATCH 14/20] dma: allocate 32-byte aligned buffers by default Ahmad Fatoum
2021-05-31  7:38 ` [PATCH 15/20] mci: dw_mmc: enable use on 64-bit CPUs Ahmad Fatoum
2021-05-31  7:38 ` [PATCH 16/20] mci: dw_mmc: match against generic "snps, dw-mshc" compatible Ahmad Fatoum
2021-05-31  7:38 ` [PATCH 17/20] clk: add initial StarFive clock support Ahmad Fatoum
2021-05-31  8:41   ` Ahmad Fatoum
2021-05-31  7:38 ` [PATCH 18/20] reset: add StarFive reset controller driver Ahmad Fatoum
2021-06-07  8:00   ` Sascha Hauer
2021-05-31  7:38 ` [PATCH 19/20] watchdog: add StarFive watchdog driver Ahmad Fatoum
2021-05-31  7:38 ` [PATCH 20/20] hw_random: add driver for RNG on StarFive SoC Ahmad Fatoum

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