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* [PATCH 1/5] net: drop Calxeda Highbank xgmac driver support
@ 2021-08-12 12:19 Ahmad Fatoum
  2021-08-12 12:19 ` [PATCH 2/5] net: make ARC MAC driver 32-bit only Ahmad Fatoum
                   ` (5 more replies)
  0 siblings, 6 replies; 7+ messages in thread
From: Ahmad Fatoum @ 2021-08-12 12:19 UTC (permalink / raw)
  To: barebox; +Cc: Ahmad Fatoum

Support for MACH_HIGHBANK was removed in f0f96c3322d5
("ARM: remove Calxeda Highbank support"). There are no device trees
either barebox or upstream using this network controller, so remove
the driver as well.

Fixes: f0f96c3322d5 ("ARM: remove Calxeda Highbank support")
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 drivers/net/Kconfig  |   4 -
 drivers/net/Makefile |   1 -
 drivers/net/xgmac.c  | 734 -------------------------------------------
 3 files changed, 739 deletions(-)
 delete mode 100644 drivers/net/xgmac.c

diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 802169a86e8c..4a290bebbd75 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -39,10 +39,6 @@ config DRIVER_NET_AT91_ETHER
 	depends on HAS_AT91_ETHER
 	select PHYLIB
 
-config DRIVER_NET_CALXEDA_XGMAC
-	bool "Calxeda xgmac"
-	depends on HAS_DMA
-
 config DRIVER_NET_CS8900
 	bool "cs8900 ethernet driver"
 	depends on HAS_CS8900 || COMPILE_TEST
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index fb3e3bdee46a..e5eede634e63 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -4,7 +4,6 @@ obj-$(CONFIG_NET_USB)			+= usb/
 obj-$(CONFIG_DRIVER_NET_AR231X)		+= ar231x.o
 obj-$(CONFIG_DRIVER_NET_ARC_EMAC)	+= arc_emac.o
 obj-$(CONFIG_DRIVER_NET_AT91_ETHER)	+= at91_ether.o
-obj-$(CONFIG_DRIVER_NET_CALXEDA_XGMAC)	+= xgmac.o
 obj-$(CONFIG_DRIVER_NET_CS8900)		+= cs8900.o
 obj-$(CONFIG_DRIVER_NET_CPSW)		+= cpsw.o
 obj-$(CONFIG_DRIVER_NET_DAVINCI_EMAC)	+= davinci_emac.o
diff --git a/drivers/net/xgmac.c b/drivers/net/xgmac.c
deleted file mode 100644
index 136d78804349..000000000000
--- a/drivers/net/xgmac.c
+++ /dev/null
@@ -1,734 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright 2010-2011 Calxeda, Inc.
- */
-
-#include <common.h>
-#include <dma.h>
-#include <net.h>
-#include <clock.h>
-#include <malloc.h>
-#include <xfuncs.h>
-#include <init.h>
-#include <errno.h>
-#include <io.h>
-#include <linux/err.h>
-
-#define TX_NUM_DESC			1
-#define RX_NUM_DESC			32
-
-#define ETH_BUF_SZ			2048
-#define TX_BUF_SZ			(ETH_BUF_SZ * TX_NUM_DESC)
-#define RX_BUF_SZ			(ETH_BUF_SZ * RX_NUM_DESC)
-
-/* XGMAC Register definitions */
-#define XGMAC_CONTROL		0x00000000	/* MAC Configuration */
-#define XGMAC_FRAME_FILTER	0x00000004	/* MAC Frame Filter */
-#define XGMAC_FLOW_CTRL		0x00000018	/* MAC Flow Control */
-#define XGMAC_VLAN_TAG		0x0000001C	/* VLAN Tags */
-#define XGMAC_VERSION		0x00000020	/* Version */
-#define XGMAC_VLAN_INCL		0x00000024	/* VLAN tag for tx frames */
-#define XGMAC_LPI_CTRL		0x00000028	/* LPI Control and Status */
-#define XGMAC_LPI_TIMER		0x0000002C	/* LPI Timers Control */
-#define XGMAC_TX_PACE		0x00000030	/* Transmit Pace and Stretch */
-#define XGMAC_VLAN_HASH		0x00000034	/* VLAN Hash Table */
-#define XGMAC_DEBUG		0x00000038	/* Debug */
-#define XGMAC_INT_STAT		0x0000003C	/* Interrupt and Control */
-#define XGMAC_ADDR_HIGH(reg)	(0x00000040 + ((reg) * 8))
-#define XGMAC_ADDR_LOW(reg)	(0x00000044 + ((reg) * 8))
-#define XGMAC_HASH(n)		(0x00000300 + (n) * 4) /* HASH table regs */
-#define XGMAC_NUM_HASH		16
-#define XGMAC_OMR		0x00000400
-#define XGMAC_REMOTE_WAKE	0x00000700	/* Remote Wake-Up Frm Filter */
-#define XGMAC_PMT		0x00000704	/* PMT Control and Status */
-#define XGMAC_MMC_CTRL		0x00000800	/* XGMAC MMC Control */
-#define XGMAC_MMC_INTR_RX	0x00000804	/* Recieve Interrupt */
-#define XGMAC_MMC_INTR_TX	0x00000808	/* Transmit Interrupt */
-#define XGMAC_MMC_INTR_MASK_RX	0x0000080c	/* Recieve Interrupt Mask */
-#define XGMAC_MMC_INTR_MASK_TX	0x00000810	/* Transmit Interrupt Mask */
-
-
-/* Hardware TX Statistics Counters */
-#define XGMAC_MMC_TXOCTET_GB_LO	0x00000814
-#define XGMAC_MMC_TXOCTET_GB_HI	0x00000818
-#define XGMAC_MMC_TXFRAME_GB_LO	0x0000081C
-#define XGMAC_MMC_TXFRAME_GB_HI	0x00000820
-#define XGMAC_MMC_TXBCFRAME_G	0x00000824
-#define XGMAC_MMC_TXMCFRAME_G	0x0000082C
-#define XGMAC_MMC_TXUCFRAME_GB	0x00000864
-#define XGMAC_MMC_TXMCFRAME_GB	0x0000086C
-#define XGMAC_MMC_TXBCFRAME_GB	0x00000874
-#define XGMAC_MMC_TXUNDERFLOW	0x0000087C
-#define XGMAC_MMC_TXOCTET_G_LO	0x00000884
-#define XGMAC_MMC_TXOCTET_G_HI	0x00000888
-#define XGMAC_MMC_TXFRAME_G_LO	0x0000088C
-#define XGMAC_MMC_TXFRAME_G_HI	0x00000890
-#define XGMAC_MMC_TXPAUSEFRAME	0x00000894
-#define XGMAC_MMC_TXVLANFRAME	0x0000089C
-
-/* Hardware RX Statistics Counters */
-#define XGMAC_MMC_RXFRAME_GB_LO	0x00000900
-#define XGMAC_MMC_RXFRAME_GB_HI	0x00000904
-#define XGMAC_MMC_RXOCTET_GB_LO	0x00000908
-#define XGMAC_MMC_RXOCTET_GB_HI	0x0000090C
-#define XGMAC_MMC_RXOCTET_G_LO	0x00000910
-#define XGMAC_MMC_RXOCTET_G_HI	0x00000914
-#define XGMAC_MMC_RXBCFRAME_G	0x00000918
-#define XGMAC_MMC_RXMCFRAME_G	0x00000920
-#define XGMAC_MMC_RXCRCERR	0x00000928
-#define XGMAC_MMC_RXRUNT	0x00000930
-#define XGMAC_MMC_RXJABBER	0x00000934
-#define XGMAC_MMC_RXUCFRAME_G	0x00000970
-#define XGMAC_MMC_RXLENGTHERR	0x00000978
-#define XGMAC_MMC_RXPAUSEFRAME	0x00000988
-#define XGMAC_MMC_RXOVERFLOW	0x00000990
-#define XGMAC_MMC_RXVLANFRAME	0x00000998
-#define XGMAC_MMC_RXWATCHDOG	0x000009a0
-
-/* DMA Control and Status Registers */
-#define XGMAC_DMA_BUS_MODE	0x00000f00	/* Bus Mode */
-#define XGMAC_DMA_TX_POLL	0x00000f04	/* Transmit Poll Demand */
-#define XGMAC_DMA_RX_POLL	0x00000f08	/* Received Poll Demand */
-#define XGMAC_DMA_RX_BASE_ADDR	0x00000f0c	/* Receive List Base */
-#define XGMAC_DMA_TX_BASE_ADDR	0x00000f10	/* Transmit List Base */
-#define XGMAC_DMA_STATUS	0x00000f14	/* Status Register */
-#define XGMAC_DMA_CONTROL	0x00000f18	/* Ctrl (Operational Mode) */
-#define XGMAC_DMA_INTR_ENA	0x00000f1c	/* Interrupt Enable */
-#define XGMAC_DMA_MISS_FRAME_CTR 0x00000f20	/* Missed Frame Counter */
-#define XGMAC_DMA_RI_WDOG_TIMER	0x00000f24	/* RX Intr Watchdog Timer */
-#define XGMAC_DMA_AXI_BUS	0x00000f28	/* AXI Bus Mode */
-#define XGMAC_DMA_AXI_STATUS	0x00000f2C	/* AXI Status */
-#define XGMAC_DMA_HW_FEATURE	0x00000f58	/* Enabled Hardware Features */
-
-#define XGMAC_ADDR_AE		0x80000000
-#define XGMAC_MAX_FILTER_ADDR	31
-
-/* PMT Control and Status */
-#define XGMAC_PMT_POINTER_RESET	0x80000000
-#define XGMAC_PMT_GLBL_UNICAST	0x00000200
-#define XGMAC_PMT_WAKEUP_RX_FRM	0x00000040
-#define XGMAC_PMT_MAGIC_PKT	0x00000020
-#define XGMAC_PMT_WAKEUP_FRM_EN	0x00000004
-#define XGMAC_PMT_MAGIC_PKT_EN	0x00000002
-#define XGMAC_PMT_POWERDOWN	0x00000001
-
-#define XGMAC_CONTROL_SPD	0x40000000	/* Speed control */
-#define XGMAC_CONTROL_SPD_MASK	0x60000000
-#define XGMAC_CONTROL_SPD_1G	0x60000000
-#define XGMAC_CONTROL_SPD_2_5G	0x40000000
-#define XGMAC_CONTROL_SPD_10G	0x00000000
-#define XGMAC_CONTROL_SARC	0x10000000	/* Source Addr Insert/Replace */
-#define XGMAC_CONTROL_SARK_MASK	0x18000000
-#define XGMAC_CONTROL_CAR	0x04000000	/* CRC Addition/Replacement */
-#define XGMAC_CONTROL_CAR_MASK	0x06000000
-#define XGMAC_CONTROL_DP	0x01000000	/* Disable Padding */
-#define XGMAC_CONTROL_WD	0x00800000	/* Disable Watchdog on rx */
-#define XGMAC_CONTROL_JD	0x00400000	/* Jabber disable */
-#define XGMAC_CONTROL_JE	0x00100000	/* Jumbo frame */
-#define XGMAC_CONTROL_LM	0x00001000	/* Loop-back mode */
-#define XGMAC_CONTROL_IPC	0x00000400	/* Checksum Offload */
-#define XGMAC_CONTROL_ACS	0x00000080	/* Automatic Pad/FCS Strip */
-#define XGMAC_CONTROL_DDIC	0x00000010	/* Disable Deficit Idle Count */
-#define XGMAC_CONTROL_TE	0x00000008	/* Transmitter Enable */
-#define XGMAC_CONTROL_RE	0x00000004	/* Receiver Enable */
-
-/* XGMAC Frame Filter defines */
-#define XGMAC_FRAME_FILTER_PR	0x00000001	/* Promiscuous Mode */
-#define XGMAC_FRAME_FILTER_HUC	0x00000002	/* Hash Unicast */
-#define XGMAC_FRAME_FILTER_HMC	0x00000004	/* Hash Multicast */
-#define XGMAC_FRAME_FILTER_DAIF	0x00000008	/* DA Inverse Filtering */
-#define XGMAC_FRAME_FILTER_PM	0x00000010	/* Pass all multicast */
-#define XGMAC_FRAME_FILTER_DBF	0x00000020	/* Disable Broadcast frames */
-#define XGMAC_FRAME_FILTER_SAIF	0x00000100	/* Inverse Filtering */
-#define XGMAC_FRAME_FILTER_SAF	0x00000200	/* Source Address Filter */
-#define XGMAC_FRAME_FILTER_HPF	0x00000400	/* Hash or perfect Filter */
-#define XGMAC_FRAME_FILTER_VHF	0x00000800	/* VLAN Hash Filter */
-#define XGMAC_FRAME_FILTER_VPF	0x00001000	/* VLAN Perfect Filter */
-#define XGMAC_FRAME_FILTER_RA	0x80000000	/* Receive all mode */
-
-#define FIFO_MINUS_1K			0x0
-#define FIFO_MINUS_2K			0x1
-#define FIFO_MINUS_3K			0x2
-#define FIFO_MINUS_4K			0x3
-#define FIFO_MINUS_6K			0x4
-#define FIFO_MINUS_8K			0x5
-#define FIFO_MINUS_12K			0x6
-#define FIFO_MINUS_16K			0x7
-
-/* XGMAC FLOW CTRL defines */
-#define XGMAC_FLOW_CTRL_PT_MASK	0xffff0000	/* Pause Time Mask */
-#define XGMAC_FLOW_CTRL_PT_SHIFT	16
-#define XGMAC_FLOW_CTRL_DZQP	0x00000080	/* Disable Zero-Quanta Phase */
-#define XGMAC_FLOW_CTRL_PLT	0x00000020	/* Pause Low Threshhold */
-#define XGMAC_FLOW_CTRL_PLT_SHIFT	4
-#define XGMAC_FLOW_CTRL_PLT_MASK 0x00000030	/* PLT MASK */
-#define XGMAC_FLOW_CTRL_UP	0x00000008	/* Unicast Pause Frame Detect */
-#define XGMAC_FLOW_CTRL_RFE	0x00000004	/* Rx Flow Control Enable */
-#define XGMAC_FLOW_CTRL_TFE	0x00000002	/* Tx Flow Control Enable */
-#define XGMAC_FLOW_CTRL_FCB_BPA	0x00000001	/* Flow Control Busy ... */
-
-/* XGMAC_INT_STAT reg */
-#define XGMAC_INT_STAT_PMT	0x0080		/* PMT Interrupt Status */
-#define XGMAC_INT_STAT_LPI	0x0040		/* LPI Interrupt Status */
-
-/* DMA Bus Mode register defines */
-#define DMA_BUS_MODE_SFT_RESET	0x00000001	/* Software Reset */
-#define DMA_BUS_MODE_DSL_MASK	0x0000007c	/* Descriptor Skip Length */
-#define DMA_BUS_MODE_DSL_SHIFT	2		/* (in DWORDS) */
-#define DMA_BUS_MODE_ATDS	0x00000080	/* Alternate Descriptor Size */
-
-/* Programmable burst length */
-#define DMA_BUS_MODE_PBL_MASK	0x00003f00	/* Programmable Burst Len */
-#define DMA_BUS_MODE_PBL_SHIFT	8
-#define DMA_BUS_MODE_FB		0x00010000	/* Fixed burst */
-#define DMA_BUS_MODE_RPBL_MASK	0x003e0000	/* Rx-Programmable Burst Len */
-#define DMA_BUS_MODE_RPBL_SHIFT	17
-#define DMA_BUS_MODE_USP	0x00800000
-#define DMA_BUS_MODE_8PBL	0x01000000
-#define DMA_BUS_MODE_AAL	0x02000000
-
-#define DMA_AXIMODE_ENLPI	0x80000000
-#define DMA_AXIMODE_MGK		0x40000000
-#define DMA_AXIMODE_WROSR	0x00100000
-#define DMA_AXIMODE_WROSR_MASK	0x00F00000
-#define DMA_AXIMODE_WROSR_SHIFT	20
-#define DMA_AXIMODE_RDOSR	0x00010000
-#define DMA_AXIMODE_RDOSR_MASK	0x000F0000
-#define DMA_AXIMODE_RDOSR_SHIFT	16
-#define DMA_AXIMODE_AAL		0x00001000
-#define DMA_AXIMODE_BLEN256	0x00000080
-#define DMA_AXIMODE_BLEN128	0x00000040
-#define DMA_AXIMODE_BLEN64	0x00000020
-#define DMA_AXIMODE_BLEN32	0x00000010
-#define DMA_AXIMODE_BLEN16	0x00000008
-#define DMA_AXIMODE_BLEN8	0x00000004
-#define DMA_AXIMODE_BLEN4	0x00000002
-#define DMA_AXIMODE_UNDEF	0x00000001
-
-/* DMA Bus Mode register defines */
-#define DMA_BUS_PR_RATIO_MASK	0x0000c000	/* Rx/Tx priority ratio */
-#define DMA_BUS_PR_RATIO_SHIFT	14
-#define DMA_BUS_FB		0x00010000	/* Fixed Burst */
-
-/* DMA Control register defines */
-#define DMA_CONTROL_ST		0x00002000	/* Start/Stop Transmission */
-#define DMA_CONTROL_SR		0x00000002	/* Start/Stop Receive */
-#define DMA_CONTROL_DFF		0x01000000	/* Disable flush of rx frames */
-
-/* DMA Normal interrupt */
-#define DMA_INTR_ENA_NIE	0x00010000	/* Normal Summary */
-#define DMA_INTR_ENA_AIE	0x00008000	/* Abnormal Summary */
-#define DMA_INTR_ENA_ERE	0x00004000	/* Early Receive */
-#define DMA_INTR_ENA_FBE	0x00002000	/* Fatal Bus Error */
-#define DMA_INTR_ENA_ETE	0x00000400	/* Early Transmit */
-#define DMA_INTR_ENA_RWE	0x00000200	/* Receive Watchdog */
-#define DMA_INTR_ENA_RSE	0x00000100	/* Receive Stopped */
-#define DMA_INTR_ENA_RUE	0x00000080	/* Receive Buffer Unavailable */
-#define DMA_INTR_ENA_RIE	0x00000040	/* Receive Interrupt */
-#define DMA_INTR_ENA_UNE	0x00000020	/* Tx Underflow */
-#define DMA_INTR_ENA_OVE	0x00000010	/* Receive Overflow */
-#define DMA_INTR_ENA_TJE	0x00000008	/* Transmit Jabber */
-#define DMA_INTR_ENA_TUE	0x00000004	/* Transmit Buffer Unavail */
-#define DMA_INTR_ENA_TSE	0x00000002	/* Transmit Stopped */
-#define DMA_INTR_ENA_TIE	0x00000001	/* Transmit Interrupt */
-
-#define DMA_INTR_NORMAL		(DMA_INTR_ENA_NIE | DMA_INTR_ENA_RIE | \
-				 DMA_INTR_ENA_TUE)
-
-#define DMA_INTR_ABNORMAL	(DMA_INTR_ENA_AIE | DMA_INTR_ENA_FBE | \
-				 DMA_INTR_ENA_RWE | DMA_INTR_ENA_RSE | \
-				 DMA_INTR_ENA_RUE | DMA_INTR_ENA_UNE | \
-				 DMA_INTR_ENA_OVE | DMA_INTR_ENA_TJE | \
-				 DMA_INTR_ENA_TSE)
-
-/* DMA default interrupt mask */
-#define DMA_INTR_DEFAULT_MASK	(DMA_INTR_NORMAL | DMA_INTR_ABNORMAL)
-
-/* DMA Status register defines */
-#define DMA_STATUS_GMI		0x08000000	/* MMC interrupt */
-#define DMA_STATUS_GLI		0x04000000	/* GMAC Line interface int */
-#define DMA_STATUS_EB_MASK	0x00380000	/* Error Bits Mask */
-#define DMA_STATUS_EB_TX_ABORT	0x00080000	/* Error Bits - TX Abort */
-#define DMA_STATUS_EB_RX_ABORT	0x00100000	/* Error Bits - RX Abort */
-#define DMA_STATUS_TS_MASK	0x00700000	/* Transmit Process State */
-#define DMA_STATUS_TS_SHIFT	20
-#define DMA_STATUS_RS_MASK	0x000e0000	/* Receive Process State */
-#define DMA_STATUS_RS_SHIFT	17
-#define DMA_STATUS_NIS		0x00010000	/* Normal Interrupt Summary */
-#define DMA_STATUS_AIS		0x00008000	/* Abnormal Interrupt Summary */
-#define DMA_STATUS_ERI		0x00004000	/* Early Receive Interrupt */
-#define DMA_STATUS_FBI		0x00002000	/* Fatal Bus Error Interrupt */
-#define DMA_STATUS_ETI		0x00000400	/* Early Transmit Interrupt */
-#define DMA_STATUS_RWT		0x00000200	/* Receive Watchdog Timeout */
-#define DMA_STATUS_RPS		0x00000100	/* Receive Process Stopped */
-#define DMA_STATUS_RU		0x00000080	/* Receive Buffer Unavailable */
-#define DMA_STATUS_RI		0x00000040	/* Receive Interrupt */
-#define DMA_STATUS_UNF		0x00000020	/* Transmit Underflow */
-#define DMA_STATUS_OVF		0x00000010	/* Receive Overflow */
-#define DMA_STATUS_TJT		0x00000008	/* Transmit Jabber Timeout */
-#define DMA_STATUS_TU		0x00000004	/* Transmit Buffer Unavail */
-#define DMA_STATUS_TPS		0x00000002	/* Transmit Process Stopped */
-#define DMA_STATUS_TI		0x00000001	/* Transmit Interrupt */
-
-/* Common MAC defines */
-#define MAC_ENABLE_TX		0x00000008	/* Transmitter Enable */
-#define MAC_ENABLE_RX		0x00000004	/* Receiver Enable */
-
-/* XGMAC Operation Mode Register */
-#define XGMAC_OMR_TSF		0x00200000	/* TX FIFO Store and Forward */
-#define XGMAC_OMR_FTF		0x00100000	/* Flush Transmit FIFO */
-#define XGMAC_OMR_TTC		0x00020000	/* Transmit Threshhold Ctrl */
-#define XGMAC_OMR_TTC_SHIFT	16
-#define XGMAC_OMR_TTC_MASK	0x00030000
-#define XGMAC_OMR_RFD		0x00006000	/* FC Deactivation Threshhold */
-#define XGMAC_OMR_RFD_SHIFT	12
-#define XGMAC_OMR_RFD_MASK	0x00007000	/* FC Deact Threshhold MASK */
-#define XGMAC_OMR_RFA		0x00000600	/* FC Activation Threshhold */
-#define XGMAC_OMR_RFA_SHIFT	9
-#define XGMAC_OMR_RFA_MASK	0x00000E00	/* FC Act Threshhold MASK */
-#define XGMAC_OMR_EFC		0x00000100	/* Enable Hardware FC */
-#define XGMAC_OMR_FEF		0x00000080	/* Forward Error Frames */
-#define XGMAC_OMR_DT		0x00000040	/* Drop TCP/IP csum Errors */
-#define XGMAC_OMR_RSF		0x00000020	/* RX FIFO Store and Forward */
-#define XGMAC_OMR_RTC_256	0x00000018	/* RX Threshhold Ctrl */
-#define XGMAC_OMR_RTC_MASK	0x00000018	/* RX Threshhold Ctrl MASK */
-
-/* XGMAC HW Features Register */
-#define DMA_HW_FEAT_TXCOESEL	0x00010000	/* TX Checksum offload */
-
-#define XGMAC_MMC_CTRL_CNT_FRZ	0x00000008
-
-/* XGMAC Descriptor Defines */
-#define MAX_DESC_BUF_SZ		(0x2000 - 8)
-
-#define RXDESC_EXT_STATUS	0x00000001
-#define RXDESC_CRC_ERR		0x00000002
-#define RXDESC_RX_ERR		0x00000008
-#define RXDESC_RX_WDOG		0x00000010
-#define RXDESC_FRAME_TYPE	0x00000020
-#define RXDESC_GIANT_FRAME	0x00000080
-#define RXDESC_LAST_SEG		0x00000100
-#define RXDESC_FIRST_SEG	0x00000200
-#define RXDESC_VLAN_FRAME	0x00000400
-#define RXDESC_OVERFLOW_ERR	0x00000800
-#define RXDESC_LENGTH_ERR	0x00001000
-#define RXDESC_SA_FILTER_FAIL	0x00002000
-#define RXDESC_DESCRIPTOR_ERR	0x00004000
-#define RXDESC_ERROR_SUMMARY	0x00008000
-#define RXDESC_FRAME_LEN_OFFSET	16
-#define RXDESC_FRAME_LEN_MASK	0x3fff0000
-#define RXDESC_DA_FILTER_FAIL	0x40000000
-
-#define RXDESC1_END_RING	0x00008000
-
-#define RXDESC_IP_PAYLOAD_MASK	0x00000003
-#define RXDESC_IP_PAYLOAD_UDP	0x00000001
-#define RXDESC_IP_PAYLOAD_TCP	0x00000002
-#define RXDESC_IP_PAYLOAD_ICMP	0x00000003
-#define RXDESC_IP_HEADER_ERR	0x00000008
-#define RXDESC_IP_PAYLOAD_ERR	0x00000010
-#define RXDESC_IPV4_PACKET	0x00000040
-#define RXDESC_IPV6_PACKET	0x00000080
-#define TXDESC_UNDERFLOW_ERR	0x00000001
-#define TXDESC_JABBER_TIMEOUT	0x00000002
-#define TXDESC_LOCAL_FAULT	0x00000004
-#define TXDESC_REMOTE_FAULT	0x00000008
-#define TXDESC_VLAN_FRAME	0x00000010
-#define TXDESC_FRAME_FLUSHED	0x00000020
-#define TXDESC_IP_HEADER_ERR	0x00000040
-#define TXDESC_PAYLOAD_CSUM_ERR	0x00000080
-#define TXDESC_ERROR_SUMMARY	0x00008000
-#define TXDESC_SA_CTRL_INSERT	0x00040000
-#define TXDESC_SA_CTRL_REPLACE	0x00080000
-#define TXDESC_2ND_ADDR_CHAINED	0x00100000
-#define TXDESC_END_RING		0x00200000
-#define TXDESC_CSUM_IP		0x00400000
-#define TXDESC_CSUM_IP_PAYLD	0x00800000
-#define TXDESC_CSUM_ALL		0x00C00000
-#define TXDESC_CRC_EN_REPLACE	0x01000000
-#define TXDESC_CRC_EN_APPEND	0x02000000
-#define TXDESC_DISABLE_PAD	0x04000000
-#define TXDESC_FIRST_SEG	0x10000000
-#define TXDESC_LAST_SEG		0x20000000
-#define TXDESC_INTERRUPT	0x40000000
-
-#define DESC_OWN		0x80000000
-#define DESC_BUFFER1_SZ_MASK	0x00001fff
-#define DESC_BUFFER2_SZ_MASK	0x1fff0000
-#define DESC_BUFFER2_SZ_OFFSET	16
-
-struct xgmac_dma_desc {
-	__le32 flags;
-	__le32 buf_size;
-	__le32 buf1_addr;		/* Buffer 1 Address Pointer */
-	__le32 buf2_addr;		/* Buffer 2 Address Pointer */
-	__le32 ext_status;
-	__le32 res[3];
-};
-
-struct xgmac_priv {
-	struct xgmac_dma_desc *rx_chain;
-	struct xgmac_dma_desc *tx_chain;
-	char *rxbuffer;
-
-	u32 tx_currdesc;
-	u32 rx_currdesc;
-
-	void __iomem *base;
-
-	struct eth_device edev;
-	struct device_d *dev;
-};
-
-/* XGMAC Descriptor Access Helpers */
-static inline void desc_set_buf_len(struct xgmac_dma_desc *p, u32 buf_sz)
-{
-	if (buf_sz > MAX_DESC_BUF_SZ)
-		p->buf_size = cpu_to_le32(MAX_DESC_BUF_SZ |
-			(buf_sz - MAX_DESC_BUF_SZ) << DESC_BUFFER2_SZ_OFFSET);
-	else
-		p->buf_size = cpu_to_le32(buf_sz);
-}
-
-static inline int desc_get_buf_len(struct xgmac_dma_desc *p)
-{
-	u32 len = le32_to_cpu(p->buf_size);
-	return (len & DESC_BUFFER1_SZ_MASK) +
-		((len & DESC_BUFFER2_SZ_MASK) >> DESC_BUFFER2_SZ_OFFSET);
-}
-
-static inline void desc_init_rx_desc(struct xgmac_dma_desc *p, int ring_size,
-				     int buf_sz)
-{
-	struct xgmac_dma_desc *end = p + ring_size - 1;
-
-	memset(p, 0, sizeof(*p) * ring_size);
-
-	for (; p <= end; p++)
-		desc_set_buf_len(p, buf_sz);
-
-	end->buf_size |= cpu_to_le32(RXDESC1_END_RING);
-}
-
-static inline void desc_init_tx_desc(struct xgmac_dma_desc *p, u32 ring_size)
-{
-	memset(p, 0, sizeof(*p) * ring_size);
-	p[ring_size - 1].flags = cpu_to_le32(TXDESC_END_RING);
-}
-
-static inline int desc_get_owner(struct xgmac_dma_desc *p)
-{
-	return le32_to_cpu(p->flags) & DESC_OWN;
-}
-
-static inline void desc_set_rx_owner(struct xgmac_dma_desc *p)
-{
-	/* Clear all fields and set the owner */
-	p->flags = cpu_to_le32(DESC_OWN);
-}
-
-static inline void desc_set_tx_owner(struct xgmac_dma_desc *p, u32 flags)
-{
-	u32 tmpflags = le32_to_cpu(p->flags);
-	tmpflags &= TXDESC_END_RING;
-	tmpflags |= flags | DESC_OWN;
-	p->flags = cpu_to_le32(tmpflags);
-}
-
-static inline void *desc_get_buf_addr(struct xgmac_dma_desc *p)
-{
-	return (void *)le32_to_cpu(p->buf1_addr);
-}
-
-static inline void desc_set_buf_addr(struct xgmac_dma_desc *p,
-				     void *paddr, int len)
-{
-	p->buf1_addr = cpu_to_le32(paddr);
-	if (len > MAX_DESC_BUF_SZ)
-		p->buf2_addr = cpu_to_le32(paddr + MAX_DESC_BUF_SZ);
-}
-
-static inline void desc_set_buf_addr_and_size(struct xgmac_dma_desc *p,
-					      void *paddr, int len)
-{
-	desc_set_buf_len(p, len);
-	desc_set_buf_addr(p, paddr, len);
-}
-
-static inline int desc_get_rx_frame_len(struct xgmac_dma_desc *p)
-{
-	u32 data = le32_to_cpu(p->flags);
-	u32 len = (data & RXDESC_FRAME_LEN_MASK) >> RXDESC_FRAME_LEN_OFFSET;
-	if (data & RXDESC_FRAME_TYPE)
-		len -= 4;
-
-	return len;
-}
-
-/*
- * Initialize a descriptor ring.  Calxeda XGMAC is configured to use
- * advanced descriptors.
- */
-
-static void init_rx_desc(struct xgmac_priv *priv)
-{
-	struct xgmac_dma_desc *rxdesc = priv->rx_chain;
-	void *rxbuffer = priv->rxbuffer;
-	int i;
-
-	desc_init_rx_desc(rxdesc, RX_NUM_DESC, ETH_BUF_SZ);
-	writel((ulong)rxdesc, priv->base + XGMAC_DMA_RX_BASE_ADDR);
-
-	for (i = 0; i < RX_NUM_DESC; i++) {
-		desc_set_buf_addr(rxdesc + i, rxbuffer + (i * ETH_BUF_SZ),
-				  ETH_BUF_SZ);
-		desc_set_rx_owner(rxdesc + i);
-	}
-}
-
-static void init_tx_desc(struct xgmac_priv *priv)
-{
-	desc_init_tx_desc(priv->tx_chain, TX_NUM_DESC);
-	writel((ulong)priv->tx_chain, priv->base + XGMAC_DMA_TX_BASE_ADDR);
-}
-
-static int xgmac_reset(struct eth_device *dev)
-{
-	struct xgmac_priv *priv = dev->priv;
-	int ret;
-	u32 value;
-
-	value = readl(priv->base + XGMAC_CONTROL) & XGMAC_CONTROL_SPD_MASK;
-
-	writel(DMA_BUS_MODE_SFT_RESET, priv->base + XGMAC_DMA_BUS_MODE);
-
-	ret = wait_on_timeout(100 * MSECOND,
-		!(readl(priv->base + XGMAC_DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET));
-
-	writel(value, priv->base + XGMAC_CONTROL);
-
-	return ret;
-}
-
-static int xgmac_open(struct eth_device *edev)
-{
-	struct xgmac_priv *priv = edev->priv;
-	int value;
-	int ret;
-
-	ret = xgmac_reset(edev);
-	if (ret)
-		return ret;
-
-	/* set the AXI bus modes */
-	value = DMA_BUS_MODE_ATDS |
-		(16 << DMA_BUS_MODE_PBL_SHIFT) |
-		DMA_BUS_MODE_FB | DMA_BUS_MODE_AAL;
-	writel(value, priv->base + XGMAC_DMA_BUS_MODE);
-
-	value = DMA_AXIMODE_AAL | DMA_AXIMODE_BLEN16 |
-		DMA_AXIMODE_BLEN8 | DMA_AXIMODE_BLEN4;
-	writel(value, priv->base + XGMAC_DMA_AXI_BUS);
-
-	/* set flow control parameters and store and forward mode */
-	value = (FIFO_MINUS_12K << XGMAC_OMR_RFD_SHIFT) |
-		(FIFO_MINUS_4K << XGMAC_OMR_RFA_SHIFT) |
-		XGMAC_OMR_EFC | XGMAC_OMR_TSF | XGMAC_OMR_RSF;
-	writel(value, priv->base + XGMAC_OMR);
-
-	/* enable pause frames */
-	value = (1024 << XGMAC_FLOW_CTRL_PT_SHIFT) |
-		(1 << XGMAC_FLOW_CTRL_PLT_SHIFT) |
-		XGMAC_FLOW_CTRL_UP | XGMAC_FLOW_CTRL_RFE | XGMAC_FLOW_CTRL_TFE;
-	writel(value, priv->base + XGMAC_FLOW_CTRL);
-
-	/* Initialize the descriptor chains */
-	init_rx_desc(priv);
-	init_tx_desc(priv);
-
-	/* must set to 0, or when started up will cause issues */
-	priv->tx_currdesc = 0;
-	priv->rx_currdesc = 0;
-
-	/* set default core values */
-	value = readl(priv->base + XGMAC_CONTROL);
-	value &= XGMAC_CONTROL_SPD_MASK;
-	value |= XGMAC_CONTROL_DDIC | XGMAC_CONTROL_ACS |
-		XGMAC_CONTROL_IPC | XGMAC_CONTROL_CAR;
-
-	/* Everything is ready enable both mac and DMA */
-	value |= XGMAC_CONTROL_RE | XGMAC_CONTROL_TE;
-	writel(value, priv->base + XGMAC_CONTROL);
-
-	value = readl(priv->base + XGMAC_DMA_CONTROL);
-	value |= DMA_CONTROL_SR | DMA_CONTROL_ST;
-	writel(value, priv->base + XGMAC_DMA_CONTROL);
-
-	return 0;
-}
-
-static int xgmac_send(struct eth_device *edev, void *packet, int length)
-{
-	struct xgmac_priv *priv = edev->priv;
-	u32 currdesc = priv->tx_currdesc;
-	struct xgmac_dma_desc *txdesc = &priv->tx_chain[currdesc];
-	int ret;
-
-	dma_sync_single_for_device((unsigned long)packet, length, DMA_TO_DEVICE);
-	desc_set_buf_addr_and_size(txdesc, packet, length);
-	desc_set_tx_owner(txdesc, TXDESC_FIRST_SEG |
-		TXDESC_LAST_SEG | TXDESC_CRC_EN_APPEND);
-
-	/* write poll demand */
-	writel(1, priv->base + XGMAC_DMA_TX_POLL);
-
-	ret = wait_on_timeout(1 * SECOND, !desc_get_owner(txdesc));
-	dma_sync_single_for_cpu((unsigned long)packet, length, DMA_TO_DEVICE);
-	if (ret) {
-		dev_err(priv->dev, "TX timeout\n");
-		return ret;
-	}
-
-	priv->tx_currdesc = (currdesc + 1) & (TX_NUM_DESC - 1);
-	return 0;
-}
-
-static int xgmac_recv(struct eth_device *edev)
-{
-	struct xgmac_priv *priv = edev->priv;
-	u32 currdesc = priv->rx_currdesc;
-	struct xgmac_dma_desc *rxdesc = &priv->rx_chain[currdesc];
-	int length = 0;
-	void *buf_addr;
-
-	/* check if the host has the desc */
-	if (desc_get_owner(rxdesc))
-		return -1; /* something bad happened */
-
-	length = desc_get_rx_frame_len(rxdesc);
-	buf_addr = desc_get_buf_addr(rxdesc);
-
-	dma_sync_single_for_cpu((unsigned long)buf_addr, length, DMA_FROM_DEVICE);
-	net_receive(edev, buf_addr, length);
-	dma_sync_single_for_device((unsigned long)buf_addr, length,
-				   DMA_FROM_DEVICE);
-
-	/* set descriptor back to owned by XGMAC */
-	desc_set_rx_owner(rxdesc);
-	writel(1, priv->base + XGMAC_DMA_RX_POLL);
-
-	priv->rx_currdesc = (currdesc + 1) & (RX_NUM_DESC - 1);
-
-	return length;
-}
-
-static void xgmac_halt(struct eth_device *edev)
-{
-	struct xgmac_priv *priv = edev->priv;
-	int value;
-
-	/* Disable TX/RX */
-	value = readl(priv->base + XGMAC_CONTROL);
-	value &= ~(XGMAC_CONTROL_RE | XGMAC_CONTROL_TE);
-	writel(value, priv->base + XGMAC_CONTROL);
-
-	/* Disable DMA */
-	value = readl(priv->base + XGMAC_DMA_CONTROL);
-	value &= ~(DMA_CONTROL_SR | DMA_CONTROL_ST);
-	writel(value, priv->base + XGMAC_DMA_CONTROL);
-
-	/* must set to 0, or when started up will cause issues */
-	priv->tx_currdesc = 0;
-	priv->rx_currdesc = 0;
-}
-
-static int xgmac_get_ethaddr(struct eth_device *edev, unsigned char *addr)
-{
-	struct xgmac_priv *priv = edev->priv;
-	u32 hi_addr, lo_addr;
-
-	/* Read the MAC address from the hardware */
-	hi_addr = readl(priv->base + XGMAC_ADDR_HIGH(0));
-	lo_addr = readl(priv->base + XGMAC_ADDR_LOW(0));
-
-	/* Extract the MAC address from the high and low words */
-	addr[0] = lo_addr & 0xff;
-	addr[1] = (lo_addr >> 8) & 0xff;
-	addr[2] = (lo_addr >> 16) & 0xff;
-	addr[3] = (lo_addr >> 24) & 0xff;
-	addr[4] = hi_addr & 0xff;
-	addr[5] = (hi_addr >> 8) & 0xff;
-
-	return 0;
-}
-
-static int xgmac_set_ethaddr(struct eth_device *dev, const unsigned char *addr)
-{
-	struct xgmac_priv *priv = dev->priv;
-	u32 data;
-
-	data = (addr[5] << 8) | addr[4];
-	writel(data, priv->base + XGMAC_ADDR_HIGH(0));
-	data = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
-	writel(data, priv->base + XGMAC_ADDR_LOW(0));
-
-	return 0;
-}
-
-static int hb_xgmac_probe(struct device_d *dev)
-{
-	struct resource *iores;
-	struct eth_device *edev;
-	struct xgmac_priv *priv;
-	void __iomem *base;
-
-	iores = dev_request_mem_resource(dev, 0);
-	if (IS_ERR(iores))
-		return PTR_ERR(iores);
-	base = IOMEM(iores->start);
-
-	/* check hardware version */
-	if (readl(base + XGMAC_VERSION) != 0x1012)
-		return -EINVAL;
-
-	priv = xzalloc(sizeof(*priv));
-
-	priv->dev = dev;
-	priv->base = base;
-
-	priv->rxbuffer = dma_alloc_coherent(RX_BUF_SZ, DMA_ADDRESS_BROKEN);
-	priv->rx_chain = dma_alloc_coherent(RX_NUM_DESC * sizeof(struct xgmac_dma_desc),
-					    DMA_ADDRESS_BROKEN);
-	priv->tx_chain = dma_alloc_coherent(TX_NUM_DESC * sizeof(struct xgmac_dma_desc),
-					    DMA_ADDRESS_BROKEN);
-
-	edev = &priv->edev;
-	edev->priv = priv;
-
-	edev->open = xgmac_open;
-	edev->send = xgmac_send;
-	edev->recv = xgmac_recv;
-	edev->halt = xgmac_halt;
-	edev->get_ethaddr = xgmac_get_ethaddr;
-	edev->set_ethaddr = xgmac_set_ethaddr;
-	edev->parent = dev;
-
-	eth_register(edev);
-
-	return 0;
-}
-
-static __maybe_unused struct of_device_id xgmac_dt_ids[] = {
-	{
-		.compatible = "calxeda,hb-xgmac",
-	}, {
-		/* sentinel */
-	}
-};
-
-static struct driver_d hb_xgmac_driver = {
-	.name  = "hb-xgmac",
-	.probe = hb_xgmac_probe,
-	.of_compatible = DRV_OF_COMPAT(xgmac_dt_ids),
-};
-device_platform_driver(hb_xgmac_driver);
-- 
2.30.2


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^ permalink raw reply	[flat|nested] 7+ messages in thread

* [PATCH 2/5] net: make ARC MAC driver 32-bit only
  2021-08-12 12:19 [PATCH 1/5] net: drop Calxeda Highbank xgmac driver support Ahmad Fatoum
@ 2021-08-12 12:19 ` Ahmad Fatoum
  2021-08-12 12:19 ` [PATCH 3/5] asm-generic: include bitio.h from io.h Ahmad Fatoum
                   ` (4 subsequent siblings)
  5 siblings, 0 replies; 7+ messages in thread
From: Ahmad Fatoum @ 2021-08-12 12:19 UTC (permalink / raw)
  To: barebox; +Cc: Ahmad Fatoum

The driver assumes 32-bit pointers and only matches against 32-bit
rockchip device trees. Make this official in the kconfig, so it's
not selectable on 64 bit, where it would issue build warnings and
probably not work anyway.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 drivers/net/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 4a290bebbd75..397164f3f175 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -28,7 +28,7 @@ config DRIVER_NET_AR231X
 
 config DRIVER_NET_ARC_EMAC
 	bool "ARC Ethernet MAC driver"
-	depends on HAS_DMA
+	depends on HAS_DMA && 32BIT
 	select PHYLIB
 	help
 	  This option enables support for the ARC EMAC ethernet
-- 
2.30.2


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^ permalink raw reply	[flat|nested] 7+ messages in thread

* [PATCH 3/5] asm-generic: include bitio.h from io.h
  2021-08-12 12:19 [PATCH 1/5] net: drop Calxeda Highbank xgmac driver support Ahmad Fatoum
  2021-08-12 12:19 ` [PATCH 2/5] net: make ARC MAC driver 32-bit only Ahmad Fatoum
@ 2021-08-12 12:19 ` Ahmad Fatoum
  2021-08-12 12:19 ` [PATCH 4/5] x86: define phys_to_virt and virt_to_phys Ahmad Fatoum
                   ` (3 subsequent siblings)
  5 siblings, 0 replies; 7+ messages in thread
From: Ahmad Fatoum @ 2021-08-12 12:19 UTC (permalink / raw)
  To: barebox; +Cc: Ahmad Fatoum

This is currently used on ARM and sandbox, but it's relevant for
other platforms like x86 as well if driver code wants to make use
of the functions defined within.

MIPS and PowerPC already defines the symbols, but that's ok because
<bitio.h> doesn't override existing macros. This works for MIPS, but
not PowerPC, where those aren't macros. Fix that up.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 arch/arm/include/asm/io.h     |  1 -
 arch/powerpc/include/asm/io.h | 10 ++++++++++
 arch/sandbox/include/asm/io.h |  1 -
 include/asm-generic/io.h      |  2 ++
 4 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index b442a37b9c1d..0507db1a9cf8 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -8,7 +8,6 @@
 #define memset_io memset_io
 
 #include <asm-generic/io.h>
-#include <asm-generic/bitio.h>
 
 /*
  * String version of IO memory access ops:
diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h
index 8488c36f6558..30d098702380 100644
--- a/arch/powerpc/include/asm/io.h
+++ b/arch/powerpc/include/asm/io.h
@@ -132,6 +132,7 @@ static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
 /*
  * 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
  */
+#define in_8 in_8
 static inline u8 in_8(const volatile u8 __iomem *addr)
 {
 	u8 ret;
@@ -141,11 +142,13 @@ static inline u8 in_8(const volatile u8 __iomem *addr)
 	return ret;
 }
 
+#define out_8 out_8
 static inline void out_8(volatile u8 __iomem *addr, u8 val)
 {
 	__asm__ __volatile__("sync;stb%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
 }
 
+#define in_le16 in_le16
 static inline u16 in_le16(const volatile u16 __iomem *addr)
 {
 	u16 ret;
@@ -155,6 +158,7 @@ static inline u16 in_le16(const volatile u16 __iomem *addr)
 	return ret;
 }
 
+#define in_be16 in_be16
 static inline u16 in_be16(const volatile u16 __iomem *addr)
 {
 	u16 ret;
@@ -164,17 +168,20 @@ static inline u16 in_be16(const volatile u16 __iomem *addr)
 	return ret;
 }
 
+#define out_le16 out_le16
 static inline void out_le16(volatile u16 __iomem *addr, u16 val)
 {
 	__asm__ __volatile__("sync; sthbrx %1,0,%2"
 			: "=m" (*addr) : "r" (val), "r" (addr));
 }
 
+#define out_be16 out_be16
 static inline void out_be16(volatile u16 __iomem *addr, u16 val)
 {
 	__asm__ __volatile__("sync;sth%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
 }
 
+#define in_le32 in_le32
 static inline u32 in_le32(const volatile u32 __iomem *addr)
 {
 	u32 ret;
@@ -184,6 +191,7 @@ static inline u32 in_le32(const volatile u32 __iomem *addr)
 	return ret;
 }
 
+#define in_be32 in_be32
 static inline u32 in_be32(const volatile u32 __iomem *addr)
 {
 	u32 ret;
@@ -193,12 +201,14 @@ static inline u32 in_be32(const volatile u32 __iomem *addr)
 	return ret;
 }
 
+#define out_le32 out_le32
 static inline void out_le32(volatile u32 __iomem *addr, u32 val)
 {
 	__asm__ __volatile__("sync; stwbrx %1,0,%2"
 			: "=m" (*addr) : "r" (val), "r" (addr));
 }
 
+#define out_be32 out_be32
 static inline void out_be32(volatile u32 __iomem *addr, u32 val)
 {
 	__asm__ __volatile__("sync;stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
diff --git a/arch/sandbox/include/asm/io.h b/arch/sandbox/include/asm/io.h
index 9f9cd3a42ab1..3e5c0580bc5a 100644
--- a/arch/sandbox/include/asm/io.h
+++ b/arch/sandbox/include/asm/io.h
@@ -8,7 +8,6 @@
 extern unsigned char __pci_iobase[IO_SPACE_LIMIT];
 
 #include <asm-generic/io.h>
-#include <asm-generic/bitio.h>
 
 static inline void *phys_to_virt(unsigned long phys)
 {
diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h
index a4b0dc4b4337..47f8c3ec1be6 100644
--- a/include/asm-generic/io.h
+++ b/include/asm-generic/io.h
@@ -479,4 +479,6 @@ static inline void memcpy_toio(volatile void __iomem *addr, const void *buffer,
 }
 #endif
 
+#include <asm-generic/bitio.h>
+
 #endif /* __ASM_GENERIC_IO_H */
-- 
2.30.2


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^ permalink raw reply	[flat|nested] 7+ messages in thread

* [PATCH 4/5] x86: define phys_to_virt and virt_to_phys
  2021-08-12 12:19 [PATCH 1/5] net: drop Calxeda Highbank xgmac driver support Ahmad Fatoum
  2021-08-12 12:19 ` [PATCH 2/5] net: make ARC MAC driver 32-bit only Ahmad Fatoum
  2021-08-12 12:19 ` [PATCH 3/5] asm-generic: include bitio.h from io.h Ahmad Fatoum
@ 2021-08-12 12:19 ` Ahmad Fatoum
  2021-08-12 12:19 ` [PATCH 5/5] net: e1000: split EEPROM and barebox MTD wrapper into separate files Ahmad Fatoum
                   ` (2 subsequent siblings)
  5 siblings, 0 replies; 7+ messages in thread
From: Ahmad Fatoum @ 2021-08-12 12:19 UTC (permalink / raw)
  To: barebox; +Cc: Ahmad Fatoum

Some PCI drivers use those, so provide 1:1 implementations.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 arch/x86/include/asm/io.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h
index 5d19679b5064..0971727bc63d 100644
--- a/arch/x86/include/asm/io.h
+++ b/arch/x86/include/asm/io.h
@@ -82,6 +82,16 @@ static inline void io_delay(void)
 	inb(0x80);
 }
 
+static inline void *phys_to_virt(unsigned long phys)
+{
+	return (void *)phys;
+}
+
+static inline unsigned long virt_to_phys(volatile void *mem)
+{
+	return (unsigned long)mem;
+}
+
 #include <asm-generic/io.h>
 
 #endif	/* __ASM_X86_IO_H */
-- 
2.30.2


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^ permalink raw reply	[flat|nested] 7+ messages in thread

* [PATCH 5/5] net: e1000: split EEPROM and barebox MTD wrapper into separate files
  2021-08-12 12:19 [PATCH 1/5] net: drop Calxeda Highbank xgmac driver support Ahmad Fatoum
                   ` (2 preceding siblings ...)
  2021-08-12 12:19 ` [PATCH 4/5] x86: define phys_to_virt and virt_to_phys Ahmad Fatoum
@ 2021-08-12 12:19 ` Ahmad Fatoum
  2021-08-12 13:03 ` [PATCH 1/5] net: drop Calxeda Highbank xgmac driver support Ahmad Fatoum
  2021-08-18  4:46 ` Sascha Hauer
  5 siblings, 0 replies; 7+ messages in thread
From: Ahmad Fatoum @ 2021-08-12 12:19 UTC (permalink / raw)
  To: barebox; +Cc: Ahmad Fatoum

With the addition of the EFI PCI bus driver, e1000 can now be built for
x86 as well. This only works when CONFIG_MTD=y, because otherwise
add_mtd_device is not defined leading to a link error.

This doesn't happen with other platforms, because linker garbage
collection, which is not used for the EFI platform.

Fix this issue by separating the generic EEPROM parts from the
barebox-specific MTD parts and compiling the MTD parts conditionally.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 drivers/net/Makefile       |   2 +-
 drivers/net/e1000/Makefile |   3 +
 drivers/net/e1000/eeprom.c | 814 ------------------------------------
 drivers/net/e1000/mtd.c    | 835 +++++++++++++++++++++++++++++++++++++
 4 files changed, 839 insertions(+), 815 deletions(-)
 create mode 100644 drivers/net/e1000/Makefile
 create mode 100644 drivers/net/e1000/mtd.c

diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index e5eede634e63..b1aa9571fc72 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -16,7 +16,7 @@ obj-$(CONFIG_DRIVER_NET_DESIGNWARE_STM32) += designware_stm32.o
 obj-$(CONFIG_DRIVER_NET_DESIGNWARE_TEGRA186) += designware_tegra186.o
 obj-$(CONFIG_DRIVER_NET_DESIGNWARE_ROCKCHIP) += designware_rockchip.o
 obj-$(CONFIG_DRIVER_NET_DM9K)		+= dm9k.o
-obj-$(CONFIG_DRIVER_NET_E1000)		+= e1000/regio.o e1000/main.o e1000/eeprom.o
+obj-$(CONFIG_DRIVER_NET_E1000)		+= e1000/
 obj-$(CONFIG_DRIVER_NET_ENC28J60)	+= enc28j60.o
 obj-$(CONFIG_DRIVER_NET_EP93XX)		+= ep93xx.o
 obj-$(CONFIG_DRIVER_NET_ETHOC)		+= ethoc.o
diff --git a/drivers/net/e1000/Makefile b/drivers/net/e1000/Makefile
new file mode 100644
index 000000000000..91ef11cbe356
--- /dev/null
+++ b/drivers/net/e1000/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-y			+= regio.o main.o eeprom.o
+obj-$(CONFIG_MTD)	+= mtd.o
diff --git a/drivers/net/e1000/eeprom.c b/drivers/net/e1000/eeprom.c
index 5a7d8675cecd..6bdf9db5532e 100644
--- a/drivers/net/e1000/eeprom.c
+++ b/drivers/net/e1000/eeprom.c
@@ -731,250 +731,6 @@ static int32_t e1000_spi_eeprom_ready(struct e1000_hw *hw)
 	return E1000_SUCCESS;
 }
 
-static int e1000_flash_mode_wait_for_idle(struct e1000_hw *hw)
-{
-	const int ret = e1000_poll_reg(hw, E1000_FLSWCTL, E1000_FLSWCTL_DONE,
-				       E1000_FLSWCTL_DONE, SECOND);
-	if (ret < 0)
-		dev_err(hw->dev,
-			"Timeout waiting for FLSWCTL.DONE to be set (wait)\n");
-	return ret;
-}
-
-static int e1000_flash_mode_check_command_valid(struct e1000_hw *hw)
-{
-	const uint32_t flswctl = e1000_read_reg(hw, E1000_FLSWCTL);
-	if (!(flswctl & E1000_FLSWCTL_CMDV)) {
-		dev_err(hw->dev, "FLSWCTL.CMDV was cleared\n");
-		return -EIO;
-	}
-
-	return E1000_SUCCESS;
-}
-
-static void e1000_flash_cmd(struct e1000_hw *hw,
-			    uint32_t cmd, uint32_t offset)
-{
-	uint32_t flswctl = e1000_read_reg(hw, E1000_FLSWCTL);
-	flswctl &= ~E1000_FLSWCTL_CMD_ADDR_MASK;
-	flswctl |= E1000_FLSWCTL_CMD(cmd) | E1000_FLSWCTL_ADDR(offset);
-	e1000_write_reg(hw, E1000_FLSWCTL, flswctl);
-}
-
-static int e1000_flash_mode_read_chunk(struct e1000_hw *hw, loff_t offset,
-				       size_t size, void *data)
-{
-	int ret;
-	size_t chunk, residue = size;
-	uint32_t flswdata;
-
-	DEBUGFUNC();
-
-	if (size > SZ_4K ||
-	    E1000_FLSWCTL_ADDR(offset) != offset)
-		return -EINVAL;
-
-	ret = e1000_flash_mode_wait_for_idle(hw);
-	if (ret < 0)
-		return ret;
-
-	e1000_write_reg(hw, E1000_FLSWCNT, size);
-	e1000_flash_cmd(hw, E1000_FLSWCTL_CMD_READ, offset);
-
-	do {
-		ret = e1000_flash_mode_check_command_valid(hw);
-		if (ret < 0)
-			return -EIO;
-
-		chunk = min(sizeof(flswdata), residue);
-
-		ret = e1000_poll_reg(hw, E1000_FLSWCTL,
-				     E1000_FLSWCTL_DONE, E1000_FLSWCTL_DONE,
-				     SECOND);
-		if (ret < 0) {
-			dev_err(hw->dev,
-				"Timeout waiting for FLSWCTL.DONE to be set (read)\n");
-			return ret;
-		}
-
-		flswdata = e1000_read_reg(hw, E1000_FLSWDATA);
-		/*
-		 * Readl does le32_to_cpu, so we need to undo that
-		 */
-		flswdata = cpu_to_le32(flswdata);
-		memcpy(data, &flswdata, chunk);
-
-		data += chunk;
-		residue -= chunk;
-	} while (residue);
-
-	return E1000_SUCCESS;
-}
-
-static int e1000_flash_mode_write_chunk(struct e1000_hw *hw, loff_t offset,
-					size_t size, const void *data)
-{
-	int ret;
-	size_t chunk, residue = size;
-	uint32_t flswdata;
-
-	if (size > 256 ||
-	    E1000_FLSWCTL_ADDR(offset) != offset)
-		return -EINVAL;
-
-	ret = e1000_flash_mode_wait_for_idle(hw);
-	if (ret < 0)
-		return ret;
-
-
-	e1000_write_reg(hw, E1000_FLSWCNT, size);
-	e1000_flash_cmd(hw, E1000_FLSWCTL_CMD_WRITE, offset);
-
-	do {
-		chunk = min(sizeof(flswdata), residue);
-		memcpy(&flswdata, data, chunk);
-		/*
-		 * writel does cpu_to_le32, so we do the inverse in
-		 * order to account for that
-		 */
-		flswdata = le32_to_cpu(flswdata);
-		e1000_write_reg(hw, E1000_FLSWDATA, flswdata);
-
-		ret = e1000_flash_mode_check_command_valid(hw);
-		if (ret < 0)
-			return -EIO;
-
-		ret = e1000_poll_reg(hw, E1000_FLSWCTL,
-				     E1000_FLSWCTL_DONE, E1000_FLSWCTL_DONE,
-				     SECOND);
-		if (ret < 0) {
-			dev_err(hw->dev,
-				"Timeout waiting for FLSWCTL.DONE to be set (write)\n");
-			return ret;
-		}
-
-		data += chunk;
-		residue -= chunk;
-
-	} while (residue);
-
-	return E1000_SUCCESS;
-}
-
-
-static int e1000_flash_mode_erase_chunk(struct e1000_hw *hw, loff_t offset,
-					size_t size)
-{
-	int ret;
-
-	ret = e1000_flash_mode_wait_for_idle(hw);
-	if (ret < 0)
-		return ret;
-
-	if (!size && !offset)
-		e1000_flash_cmd(hw, E1000_FLSWCTL_CMD_ERASE_DEVICE, 0);
-	else
-		e1000_flash_cmd(hw, E1000_FLSWCTL_CMD_ERASE_SECTOR, offset);
-
-	ret = e1000_flash_mode_check_command_valid(hw);
-	if (ret < 0)
-		return -EIO;
-
-	ret = e1000_poll_reg(hw, E1000_FLSWCTL,
-			     E1000_FLSWCTL_DONE | E1000_FLSWCTL_FLBUSY,
-			     E1000_FLSWCTL_DONE,
-			     40 * SECOND);
-	if (ret < 0) {
-		dev_err(hw->dev,
-			"Timeout waiting for FLSWCTL.DONE to be set (erase)\n");
-		return ret;
-	}
-
-	return E1000_SUCCESS;
-}
-
-enum {
-	E1000_FLASH_MODE_OP_READ = 0,
-	E1000_FLASH_MODE_OP_WRITE = 1,
-	E1000_FLASH_MODE_OP_ERASE = 2,
-};
-
-
-static int e1000_flash_mode_io(struct e1000_hw *hw, int op, size_t granularity,
-			       loff_t offset, size_t size, void *data)
-{
-	int ret;
-	size_t residue = size;
-
-	do {
-		const size_t chunk = min(granularity, residue);
-
-		switch (op) {
-		case E1000_FLASH_MODE_OP_READ:
-			ret = e1000_flash_mode_read_chunk(hw, offset,
-							  chunk, data);
-			break;
-		case E1000_FLASH_MODE_OP_WRITE:
-			ret = e1000_flash_mode_write_chunk(hw, offset,
-							   chunk, data);
-			break;
-		case E1000_FLASH_MODE_OP_ERASE:
-			ret = e1000_flash_mode_erase_chunk(hw, offset,
-							   chunk);
-			break;
-		default:
-			return -ENOTSUPP;
-		}
-
-		if (ret < 0)
-			return ret;
-
-		offset += chunk;
-		residue -= chunk;
-		data += chunk;
-	} while (residue);
-
-	return E1000_SUCCESS;
-}
-
-
-static int e1000_flash_mode_read(struct e1000_hw *hw, loff_t offset,
-				 size_t size, void *data)
-{
-	return e1000_flash_mode_io(hw,
-				   E1000_FLASH_MODE_OP_READ, SZ_4K,
-				   offset, size, data);
-}
-
-static int e1000_flash_mode_write(struct e1000_hw *hw, loff_t offset,
-				  size_t size, const void *data)
-{
-	int ret;
-
-	ret = e1000_flash_mode_io(hw,
-				  E1000_FLASH_MODE_OP_WRITE, 256,
-				  offset, size, (void *)data);
-	if (ret < 0)
-		return ret;
-
-	ret = e1000_poll_reg(hw, E1000_FLSWCTL,
-			     E1000_FLSWCTL_FLBUSY,
-			     0,  SECOND);
-	if (ret < 0)
-		dev_err(hw->dev, "Timout while waiting for FLSWCTL.FLBUSY\n");
-
-	return ret;
-}
-
-static int e1000_flash_mode_erase(struct e1000_hw *hw, loff_t offset,
-				  size_t size)
-{
-	return e1000_flash_mode_io(hw,
-				   E1000_FLASH_MODE_OP_ERASE, SZ_4K,
-				   offset, size, NULL);
-}
-
-
 /******************************************************************************
  * Reads a 16 bit word from the EEPROM.
  *
@@ -1066,484 +822,6 @@ int e1000_validate_eeprom_checksum(struct e1000_hw *hw)
 	return -E1000_ERR_EEPROM;
 }
 
-static ssize_t e1000_invm_cdev_read(struct cdev *cdev, void *buf,
-				    size_t count, loff_t offset, unsigned long flags)
-{
-	uint8_t n, bnr;
-	uint32_t line;
-	size_t chunk, residue = count;
-	struct e1000_hw *hw = container_of(cdev, struct e1000_hw, invm.cdev);
-
-	n = offset / sizeof(line);
-	if (n > E1000_INVM_DATA_MAX_N)
-		return -EINVAL;
-
-	bnr = offset % sizeof(line);
-	if (bnr) {
-		/*
-		 * if bnr in not zero it means we have a non 4-byte
-		 * aligned start and need to do a partial read
-		 */
-		const uint8_t *bptr;
-
-		bptr  = (uint8_t *)&line + bnr;
-		chunk = min(bnr - sizeof(line), count);
-		line  = e1000_read_reg(hw, E1000_INVM_DATA(n));
-		line  = cpu_to_le32(line); /* to account for readl */
-		memcpy(buf, bptr, chunk);
-
-		goto start_adjusted;
-	}
-
-	do {
-		if (n > E1000_INVM_DATA_MAX_N)
-			return -EINVAL;
-
-		chunk = min(sizeof(line), residue);
-		line = e1000_read_reg(hw, E1000_INVM_DATA(n));
-		line = cpu_to_le32(line); /* to account for readl */
-
-		/*
-		 * by using memcpy in conjunction with min should get
-		 * dangling tail reads as well as aligned reads
-		 */
-		memcpy(buf, &line, chunk);
-
-	start_adjusted:
-		residue -= chunk;
-		buf += chunk;
-		n++;
-	} while (residue);
-
-	return count;
-}
-
-static int e1000_invm_program(struct e1000_hw *hw, u32 offset, u32 value,
-			      unsigned int delay)
-{
-	int retries = 400;
-	do {
-		if ((e1000_read_reg(hw, offset) & value) == value)
-			return E1000_SUCCESS;
-
-		e1000_write_reg(hw, offset, value);
-
-		if (delay) {
-			udelay(delay);
-		} else {
-			int ret;
-
-			if (e1000_read_reg(hw, E1000_INVM_PROTECT) &
-			    E1000_INVM_PROTECT_WRITE_ERROR) {
-				dev_err(hw->dev, "Error while writing to %x\n", offset);
-				return -EIO;
-			}
-
-			ret = e1000_poll_reg(hw, E1000_INVM_PROTECT,
-					     E1000_INVM_PROTECT_BUSY,
-					     0,  SECOND);
-			if (ret < 0) {
-				dev_err(hw->dev,
-					"Timeout while waiting for INVM_PROTECT.BUSY\n");
-				return ret;
-			}
-		}
-	} while (retries--);
-
-	return -ETIMEDOUT;
-}
-
-static int e1000_invm_set_lock(struct param_d *param, void *priv)
-{
-	struct e1000_hw *hw = priv;
-
-	if (hw->invm.line > 31)
-		return -EINVAL;
-
-	return e1000_invm_program(hw,
-				  E1000_INVM_LOCK(hw->invm.line),
-				  E1000_INVM_LOCK_BIT,
-				  10);
-}
-
-static int e1000_invm_unlock(struct e1000_hw *hw)
-{
-	e1000_write_reg(hw, E1000_INVM_PROTECT, E1000_INVM_PROTECT_CODE);
-	/*
-	 * If we were successful at unlocking iNVM for programming we
-	 * should see ALLOW_WRITE bit toggle to 1
-	 */
-	if (!(e1000_read_reg(hw, E1000_INVM_PROTECT) &
-	      E1000_INVM_PROTECT_ALLOW_WRITE))
-		return -EIO;
-	else
-		return E1000_SUCCESS;
-}
-
-static void e1000_invm_lock(struct e1000_hw *hw)
-{
-	e1000_write_reg(hw, E1000_INVM_PROTECT, 0);
-}
-
-static int e1000_invm_write_prepare(struct e1000_hw *hw)
-{
-	int ret;
-	/*
-	 * This needs to be done accorging to the datasheet p. 541 and
-	 * p. 79
-	*/
-	e1000_write_reg(hw, E1000_PCIEMISC,
-			E1000_PCIEMISC_RESERVED_PATTERN1 |
-			E1000_PCIEMISC_DMA_IDLE          |
-			E1000_PCIEMISC_RESERVED_PATTERN2);
-
-	/*
-	 * Needed for programming iNVM on devices with Flash with valid
-	 * contents attached
-	 */
-	ret = e1000_poll_reg(hw, E1000_EEMNGCTL,
-			     E1000_EEMNGCTL_CFG_DONE,
-			     E1000_EEMNGCTL_CFG_DONE, SECOND);
-	if (ret < 0) {
-		dev_err(hw->dev,
-			"Timeout while waiting for EEMNGCTL.CFG_DONE\n");
-		return ret;
-	}
-
-	udelay(15);
-
-	return E1000_SUCCESS;
-}
-
-static ssize_t e1000_invm_cdev_write(struct cdev *cdev, const void *buf,
-				     size_t count, loff_t offset, unsigned long flags)
-{
-	int ret;
-	uint8_t n, bnr;
-	uint32_t line;
-	size_t chunk, residue = count;
-	struct e1000_hw *hw = container_of(cdev, struct e1000_hw, invm.cdev);
-
-	ret = e1000_invm_write_prepare(hw);
-	if (ret < 0)
-		return ret;
-
-	ret = e1000_invm_unlock(hw);
-	if (ret < 0)
-		goto exit;
-
-	n = offset / sizeof(line);
-	if (n > E1000_INVM_DATA_MAX_N) {
-		ret = -EINVAL;
-		goto exit;
-	}
-
-	bnr = offset % sizeof(line);
-	if (bnr) {
-		uint8_t *bptr;
-		/*
-		 * if bnr in not zero it means we have a non 4-byte
-		 * aligned start and need to do a read-modify-write
-		 * sequence
-		 */
-
-		/* Read */
-		line = e1000_read_reg(hw, E1000_INVM_DATA(n));
-
-		/* Modify */
-		/*
-		 * We need to ensure that line is LE32 in order for
-		 * memcpy to copy byte from least significant to most
-		 * significant, since that's how i210 will write the
-		 * 32-bit word out to OTP
-		 */
-		line = cpu_to_le32(line);
-		bptr  = (uint8_t *)&line + bnr;
-		chunk = min(sizeof(line) - bnr, count);
-		memcpy(bptr, buf, chunk);
-		line = le32_to_cpu(line);
-
-		/* Jumping inside of the loop to take care of the
-		 * Write */
-		goto start_adjusted;
-	}
-
-	do {
-		if (n > E1000_INVM_DATA_MAX_N) {
-			ret = -EINVAL;
-			goto exit;
-		}
-
-		chunk = min(sizeof(line), residue);
-		if (chunk != sizeof(line)) {
-			/*
-			 * If chunk is smaller that sizeof(line), which
-			 * should be 4 bytes, we have a "dangling"
-			 * chunk and we should read the unchanged
-			 * portion of the 4-byte word from iNVM and do
-			 * a read-modify-write sequence
-			 */
-			line = e1000_read_reg(hw, E1000_INVM_DATA(n));
-		}
-
-		line = cpu_to_le32(line);
-		memcpy(&line, buf, chunk);
-		line = le32_to_cpu(line);
-
-	start_adjusted:
-		/*
-		 * iNVM is organized in 32 64-bit lines and each of
-		 * those lines can be locked to prevent any further
-		 * modification, so for every i-th 32-bit word we need
-		 * to check INVM_LINE[i/2] register to see if that word
-		 * can be modified
-		 */
-		if (e1000_read_reg(hw, E1000_INVM_LOCK(n / 2)) &
-		    E1000_INVM_LOCK_BIT) {
-			dev_err(hw->dev, "line %d is locked\n", n / 2);
-			ret = -EIO;
-			goto exit;
-		}
-
-		ret = e1000_invm_program(hw,
-					 E1000_INVM_DATA(n),
-					 line,
-					 0);
-		if (ret < 0)
-			goto exit;
-
-		residue -= chunk;
-		buf += chunk;
-		n++;
-	} while (residue);
-
-	ret = E1000_SUCCESS;
-exit:
-	e1000_invm_lock(hw);
-	return ret;
-}
-
-static struct cdev_operations e1000_invm_ops = {
-	.read	= e1000_invm_cdev_read,
-	.write	= e1000_invm_cdev_write,
-};
-
-static ssize_t e1000_eeprom_cdev_read(struct cdev *cdev, void *buf,
-				      size_t count, loff_t offset, unsigned long flags)
-{
-	struct e1000_hw *hw = container_of(cdev, struct e1000_hw, eepromcdev);
-	int32_t ret;
-
-	/*
-	 * The eeprom interface works on 16 bit words which gives a nice excuse
-	 * for being lazy and not implementing unaligned reads.
-	 */
-	if (offset & 1 || count == 1)
-		return -EIO;
-
-	ret = e1000_read_eeprom(hw, offset / 2, count / 2, buf);
-	if (ret)
-		return -EIO;
-	else
-		return (count / 2) * 2;
-};
-
-static struct cdev_operations e1000_eeprom_ops = {
-	.read = e1000_eeprom_cdev_read,
-};
-
-static int e1000_mtd_read_or_write(bool read,
-				   struct mtd_info *mtd, loff_t off, size_t len,
-				   size_t *retlen, u_char *buf)
-{
-	int ret;
-	struct e1000_hw *hw = container_of(mtd, struct e1000_hw, mtd);
-
-	DEBUGFUNC();
-
-	if (e1000_acquire_eeprom(hw) == E1000_SUCCESS) {
-		if (read)
-			ret = e1000_flash_mode_read(hw, off,
-						    len, buf);
-		else
-			ret = e1000_flash_mode_write(hw, off,
-						     len, buf);
-		if (ret == E1000_SUCCESS)
-			*retlen = len;
-
-		e1000_release_eeprom(hw);
-	} else {
-		ret = -E1000_ERR_EEPROM;
-	}
-
-	return ret;
-
-}
-
-static int e1000_mtd_read(struct mtd_info *mtd, loff_t from, size_t len,
-				 size_t *retlen, u_char *buf)
-{
-	return e1000_mtd_read_or_write(true,
-				       mtd, from, len, retlen, buf);
-}
-
-static int e1000_mtd_write(struct mtd_info *mtd, loff_t to, size_t len,
-			   size_t *retlen, const u_char *buf)
-{
-	return e1000_mtd_read_or_write(false,
-				       mtd, to, len, retlen, (u_char *)buf);
-}
-
-static int e1000_mtd_erase(struct mtd_info *mtd, struct erase_info *instr)
-{
-	uint32_t rem;
-	struct e1000_hw *hw = container_of(mtd, struct e1000_hw, mtd);
-	int ret;
-
-	div_u64_rem(instr->len, mtd->erasesize, &rem);
-	if (rem)
-		return -EINVAL;
-
-	ret = e1000_acquire_eeprom(hw);
-	if (ret != E1000_SUCCESS)
-		goto fail;
-
-	/*
-	 * If mtd->size is 4096 it means we are dealing with
-	 * unprogrammed flash and we don't really know its size to
-	 * make an informed decision wheither to erase the whole chip or
-	 * just a number of its sectors
-	 */
-	if (mtd->size > SZ_4K &&
-	    instr->len == mtd->size)
-		ret = e1000_flash_mode_erase(hw, 0, 0);
-	else
-		ret = e1000_flash_mode_erase(hw,
-					     instr->addr, instr->len);
-
-	e1000_release_eeprom(hw);
-
-	if (ret < 0)
-		goto fail;
-
-	return 0;
-
-fail:
-	return ret;
-}
-
-static int e1000_mtd_sr_rmw(struct mtd_info *mtd, u8 mask, u8 val)
-{
-	struct e1000_hw *hw = container_of(mtd, struct e1000_hw, mtd);
-	uint32_t flswdata;
-	int ret;
-
-	ret = e1000_flash_mode_wait_for_idle(hw);
-	if (ret < 0)
-		return ret;
-
-	e1000_write_reg(hw, E1000_FLSWCNT, 1);
-	e1000_flash_cmd(hw, E1000_FLSWCTL_CMD_RDSR, 0);
-
-	ret = e1000_flash_mode_check_command_valid(hw);
-	if (ret < 0)
-		return -EIO;
-
-	ret = e1000_poll_reg(hw, E1000_FLSWCTL,
-			     E1000_FLSWCTL_DONE, E1000_FLSWCTL_DONE,
-			     SECOND);
-	if (ret < 0) {
-		dev_err(hw->dev,
-			"Timeout waiting for FLSWCTL.DONE to be set (RDSR)\n");
-		return ret;
-	}
-
-	flswdata = e1000_read_reg(hw, E1000_FLSWDATA);
-
-	flswdata = (flswdata & ~mask) | val;
-
-	e1000_write_reg(hw, E1000_FLSWCNT, 1);
-	e1000_flash_cmd(hw, E1000_FLSWCTL_CMD_WRSR, 0);
-
-	ret = e1000_flash_mode_check_command_valid(hw);
-	if (ret < 0)
-		return -EIO;
-
-	e1000_write_reg(hw, E1000_FLSWDATA, flswdata);
-
-	ret = e1000_poll_reg(hw, E1000_FLSWCTL,
-			     E1000_FLSWCTL_DONE, E1000_FLSWCTL_DONE,
-			     SECOND);
-	if (ret < 0) {
-		dev_err(hw->dev,
-			"Timeout waiting for FLSWCTL.DONE to be set (WRSR)\n");
-	}
-
-	return ret;
-}
-
-/*
- * The available spi nor devices are very different in how the block protection
- * bits affect which sectors to be protected. So take the simple approach and
- * only use BP[012] = b000 (unprotected) and BP[012] = b111 (protected).
- */
-#define SR_BPALL (SR_BP0 | SR_BP1 | SR_BP2)
-
-static int e1000_mtd_lock(struct mtd_info *mtd, loff_t ofs, size_t len)
-{
-	return e1000_mtd_sr_rmw(mtd, SR_BPALL, SR_BPALL);
-}
-
-static int e1000_mtd_unlock(struct mtd_info *mtd, loff_t ofs, size_t len)
-{
-	return e1000_mtd_sr_rmw(mtd, SR_BPALL, 0x0);
-}
-
-static int e1000_register_invm(struct e1000_hw *hw)
-{
-	int ret;
-	u16 word;
-	struct param_d *p;
-
-	if (e1000_eeprom_valid(hw)) {
-		ret = e1000_read_eeprom(hw, 0x0a, 1, &word);
-		if (ret < 0)
-			return ret;
-
-		if (word & (1 << 15))
-			dev_warn(hw->dev, "iNVM lockout mechanism is active\n");
-	}
-
-	hw->invm.cdev.dev = hw->dev;
-	hw->invm.cdev.ops = &e1000_invm_ops;
-	hw->invm.cdev.priv = hw;
-	hw->invm.cdev.name = xasprintf("e1000-invm%d", hw->dev->id);
-	hw->invm.cdev.size = 4 * (E1000_INVM_DATA_MAX_N + 1);
-
-	ret = devfs_create(&hw->invm.cdev);
-	if (ret < 0)
-		return ret;
-
-	dev_set_name(&hw->invm.dev, "invm");
-	hw->invm.dev.id = hw->dev->id;
-	hw->invm.dev.parent = hw->dev;
-	ret = register_device(&hw->invm.dev);
-	if (ret < 0) {
-		devfs_remove(&hw->invm.cdev);
-		return ret;
-	}
-
-	p = dev_add_param_int(&hw->invm.dev, "lock", e1000_invm_set_lock,
-			      NULL, &hw->invm.line, "%u", hw);
-	if (IS_ERR(p)) {
-		unregister_device(&hw->invm.dev);
-		devfs_remove(&hw->invm.cdev);
-		ret = PTR_ERR(p);
-	}
-
-	return ret;
-}
-
 int e1000_eeprom_valid(struct e1000_hw *hw)
 {
 	uint32_t valid_mask = E1000_EECD_FLASH_IN_USE |
@@ -1562,95 +840,3 @@ int e1000_eeprom_valid(struct e1000_hw *hw)
 
 	return 1;
 }
-
-/*
- * This function has a wrong name for historic reasons, it doesn't add an
- * eeprom, but the flash (if available) that is used to simulate the eeprom.
- * Also a device that represents the invm is registered here (if available).
- */
-int e1000_register_eeprom(struct e1000_hw *hw)
-{
-	struct e1000_eeprom_info *eeprom = &hw->eeprom;
-	uint32_t eecd;
-	int ret;
-
-	if (hw->mac_type != e1000_igb)
-		return E1000_SUCCESS;
-
-	eecd = e1000_read_reg(hw, E1000_EECD);
-
-	if (eecd & E1000_EECD_AUTO_RD) {
-		if (eecd & E1000_EECD_EE_PRES) {
-			if (eecd & E1000_EECD_FLASH_IN_USE) {
-				uint32_t fla = e1000_read_reg(hw, E1000_FLA);
-				dev_info(hw->dev,
-					 "Hardware programmed from flash (%ssecure)\n",
-					 fla & E1000_FLA_LOCKED ? "" : "un");
-			} else {
-				dev_info(hw->dev, "Hardware programmed from iNVM\n");
-			}
-		} else {
-			dev_warn(hw->dev, "Shadow RAM invalid\n");
-		}
-	} else {
-		/*
-		 * I never saw this case in practise and I'm unsure how
-		 * to handle that. Maybe just wait until the hardware is
-		 * up enough that this bit is set?
-		 */
-		dev_err(hw->dev, "Flash Auto-Read not done\n");
-	}
-
-	if (e1000_eeprom_valid(hw)) {
-		hw->eepromcdev.dev = hw->dev;
-		hw->eepromcdev.ops = &e1000_eeprom_ops;
-		hw->eepromcdev.name = xasprintf("e1000-eeprom%d",
-						hw->dev->id);
-		hw->eepromcdev.size = 0x1000;
-
-		ret = devfs_create(&hw->eepromcdev);
-		if (ret < 0)
-			return ret;
-	}
-
-	if (eecd & E1000_EECD_I210_FLASH_DETECTED) {
-		hw->mtd.dev.parent = hw->dev;
-		hw->mtd._read = e1000_mtd_read;
-		hw->mtd._write = e1000_mtd_write;
-		hw->mtd._erase = e1000_mtd_erase;
-		hw->mtd._lock = e1000_mtd_lock;
-		hw->mtd._unlock = e1000_mtd_unlock;
-		hw->mtd.size = eeprom->word_size * 2;
-		hw->mtd.writesize = 1;
-		hw->mtd.subpage_sft = 0;
-
-		hw->mtd.eraseregions = xzalloc(sizeof(struct mtd_erase_region_info));
-		hw->mtd.erasesize = SZ_4K;
-		hw->mtd.eraseregions[0].erasesize = SZ_4K;
-		hw->mtd.eraseregions[0].numblocks = hw->mtd.size / SZ_4K;
-		hw->mtd.numeraseregions = 1;
-
-		hw->mtd.flags = MTD_CAP_NORFLASH;
-		hw->mtd.type = MTD_NORFLASH;
-
-		ret = add_mtd_device(&hw->mtd, "e1000-nor",
-				     DEVICE_ID_DYNAMIC);
-		if (ret)
-			goto out_eeprom;
-	}
-
-	ret = e1000_register_invm(hw);
-	if (ret < 0)
-		goto out_mtd;
-
-	return E1000_SUCCESS;
-
-out_mtd:
-	if (eecd & E1000_EECD_I210_FLASH_DETECTED)
-		del_mtd_device(&hw->mtd);
-out_eeprom:
-	if (e1000_eeprom_valid(hw))
-		devfs_remove(&hw->eepromcdev);
-
-	return ret;
-}
diff --git a/drivers/net/e1000/mtd.c b/drivers/net/e1000/mtd.c
new file mode 100644
index 000000000000..93595cc88d24
--- /dev/null
+++ b/drivers/net/e1000/mtd.c
@@ -0,0 +1,835 @@
+#include <common.h>
+#include <init.h>
+#include <malloc.h>
+#include <linux/math64.h>
+#include <linux/sizes.h>
+#include <of_device.h>
+#include <linux/pci.h>
+#include <linux/mtd/spi-nor.h>
+
+#include "e1000.h"
+
+static int32_t e1000_acquire_eeprom(struct e1000_hw *hw)
+{
+	if (hw->eeprom.acquire)
+		return hw->eeprom.acquire(hw);
+	else
+		return E1000_SUCCESS;
+}
+
+static void e1000_release_eeprom(struct e1000_hw *hw)
+{
+	if (hw->eeprom.release)
+		hw->eeprom.release(hw);
+}
+
+static int e1000_flash_mode_wait_for_idle(struct e1000_hw *hw)
+{
+	const int ret = e1000_poll_reg(hw, E1000_FLSWCTL, E1000_FLSWCTL_DONE,
+				       E1000_FLSWCTL_DONE, SECOND);
+	if (ret < 0)
+		dev_err(hw->dev,
+			"Timeout waiting for FLSWCTL.DONE to be set (wait)\n");
+	return ret;
+}
+
+static int e1000_flash_mode_check_command_valid(struct e1000_hw *hw)
+{
+	const uint32_t flswctl = e1000_read_reg(hw, E1000_FLSWCTL);
+	if (!(flswctl & E1000_FLSWCTL_CMDV)) {
+		dev_err(hw->dev, "FLSWCTL.CMDV was cleared\n");
+		return -EIO;
+	}
+
+	return E1000_SUCCESS;
+}
+
+static void e1000_flash_cmd(struct e1000_hw *hw,
+			    uint32_t cmd, uint32_t offset)
+{
+	uint32_t flswctl = e1000_read_reg(hw, E1000_FLSWCTL);
+	flswctl &= ~E1000_FLSWCTL_CMD_ADDR_MASK;
+	flswctl |= E1000_FLSWCTL_CMD(cmd) | E1000_FLSWCTL_ADDR(offset);
+	e1000_write_reg(hw, E1000_FLSWCTL, flswctl);
+}
+
+static int e1000_flash_mode_read_chunk(struct e1000_hw *hw, loff_t offset,
+				       size_t size, void *data)
+{
+	int ret;
+	size_t chunk, residue = size;
+	uint32_t flswdata;
+
+	DEBUGFUNC();
+
+	if (size > SZ_4K ||
+	    E1000_FLSWCTL_ADDR(offset) != offset)
+		return -EINVAL;
+
+	ret = e1000_flash_mode_wait_for_idle(hw);
+	if (ret < 0)
+		return ret;
+
+	e1000_write_reg(hw, E1000_FLSWCNT, size);
+	e1000_flash_cmd(hw, E1000_FLSWCTL_CMD_READ, offset);
+
+	do {
+		ret = e1000_flash_mode_check_command_valid(hw);
+		if (ret < 0)
+			return -EIO;
+
+		chunk = min(sizeof(flswdata), residue);
+
+		ret = e1000_poll_reg(hw, E1000_FLSWCTL,
+				     E1000_FLSWCTL_DONE, E1000_FLSWCTL_DONE,
+				     SECOND);
+		if (ret < 0) {
+			dev_err(hw->dev,
+				"Timeout waiting for FLSWCTL.DONE to be set (read)\n");
+			return ret;
+		}
+
+		flswdata = e1000_read_reg(hw, E1000_FLSWDATA);
+		/*
+		 * Readl does le32_to_cpu, so we need to undo that
+		 */
+		flswdata = cpu_to_le32(flswdata);
+		memcpy(data, &flswdata, chunk);
+
+		data += chunk;
+		residue -= chunk;
+	} while (residue);
+
+	return E1000_SUCCESS;
+}
+
+static int e1000_flash_mode_write_chunk(struct e1000_hw *hw, loff_t offset,
+					size_t size, const void *data)
+{
+	int ret;
+	size_t chunk, residue = size;
+	uint32_t flswdata;
+
+	if (size > 256 ||
+	    E1000_FLSWCTL_ADDR(offset) != offset)
+		return -EINVAL;
+
+	ret = e1000_flash_mode_wait_for_idle(hw);
+	if (ret < 0)
+		return ret;
+
+
+	e1000_write_reg(hw, E1000_FLSWCNT, size);
+	e1000_flash_cmd(hw, E1000_FLSWCTL_CMD_WRITE, offset);
+
+	do {
+		chunk = min(sizeof(flswdata), residue);
+		memcpy(&flswdata, data, chunk);
+		/*
+		 * writel does cpu_to_le32, so we do the inverse in
+		 * order to account for that
+		 */
+		flswdata = le32_to_cpu(flswdata);
+		e1000_write_reg(hw, E1000_FLSWDATA, flswdata);
+
+		ret = e1000_flash_mode_check_command_valid(hw);
+		if (ret < 0)
+			return -EIO;
+
+		ret = e1000_poll_reg(hw, E1000_FLSWCTL,
+				     E1000_FLSWCTL_DONE, E1000_FLSWCTL_DONE,
+				     SECOND);
+		if (ret < 0) {
+			dev_err(hw->dev,
+				"Timeout waiting for FLSWCTL.DONE to be set (write)\n");
+			return ret;
+		}
+
+		data += chunk;
+		residue -= chunk;
+
+	} while (residue);
+
+	return E1000_SUCCESS;
+}
+
+static int e1000_flash_mode_erase_chunk(struct e1000_hw *hw, loff_t offset,
+					size_t size)
+{
+	int ret;
+
+	ret = e1000_flash_mode_wait_for_idle(hw);
+	if (ret < 0)
+		return ret;
+
+	if (!size && !offset)
+		e1000_flash_cmd(hw, E1000_FLSWCTL_CMD_ERASE_DEVICE, 0);
+	else
+		e1000_flash_cmd(hw, E1000_FLSWCTL_CMD_ERASE_SECTOR, offset);
+
+	ret = e1000_flash_mode_check_command_valid(hw);
+	if (ret < 0)
+		return -EIO;
+
+	ret = e1000_poll_reg(hw, E1000_FLSWCTL,
+			     E1000_FLSWCTL_DONE | E1000_FLSWCTL_FLBUSY,
+			     E1000_FLSWCTL_DONE,
+			     40 * SECOND);
+	if (ret < 0) {
+		dev_err(hw->dev,
+			"Timeout waiting for FLSWCTL.DONE to be set (erase)\n");
+		return ret;
+	}
+
+	return E1000_SUCCESS;
+}
+
+enum {
+	E1000_FLASH_MODE_OP_READ = 0,
+	E1000_FLASH_MODE_OP_WRITE = 1,
+	E1000_FLASH_MODE_OP_ERASE = 2,
+};
+
+
+static int e1000_flash_mode_io(struct e1000_hw *hw, int op, size_t granularity,
+			       loff_t offset, size_t size, void *data)
+{
+	int ret;
+	size_t residue = size;
+
+	do {
+		const size_t chunk = min(granularity, residue);
+
+		switch (op) {
+		case E1000_FLASH_MODE_OP_READ:
+			ret = e1000_flash_mode_read_chunk(hw, offset,
+							  chunk, data);
+			break;
+		case E1000_FLASH_MODE_OP_WRITE:
+			ret = e1000_flash_mode_write_chunk(hw, offset,
+							   chunk, data);
+			break;
+		case E1000_FLASH_MODE_OP_ERASE:
+			ret = e1000_flash_mode_erase_chunk(hw, offset,
+							   chunk);
+			break;
+		default:
+			return -ENOTSUPP;
+		}
+
+		if (ret < 0)
+			return ret;
+
+		offset += chunk;
+		residue -= chunk;
+		data += chunk;
+	} while (residue);
+
+	return E1000_SUCCESS;
+}
+
+static int e1000_flash_mode_read(struct e1000_hw *hw, loff_t offset,
+				 size_t size, void *data)
+{
+	return e1000_flash_mode_io(hw,
+				   E1000_FLASH_MODE_OP_READ, SZ_4K,
+				   offset, size, data);
+}
+
+static int e1000_flash_mode_write(struct e1000_hw *hw, loff_t offset,
+				  size_t size, const void *data)
+{
+	int ret;
+
+	ret = e1000_flash_mode_io(hw,
+				  E1000_FLASH_MODE_OP_WRITE, 256,
+				  offset, size, (void *)data);
+	if (ret < 0)
+		return ret;
+
+	ret = e1000_poll_reg(hw, E1000_FLSWCTL,
+			     E1000_FLSWCTL_FLBUSY,
+			     0,  SECOND);
+	if (ret < 0)
+		dev_err(hw->dev, "Timout while waiting for FLSWCTL.FLBUSY\n");
+
+	return ret;
+}
+
+static int e1000_flash_mode_erase(struct e1000_hw *hw, loff_t offset,
+				  size_t size)
+{
+	return e1000_flash_mode_io(hw,
+				   E1000_FLASH_MODE_OP_ERASE, SZ_4K,
+				   offset, size, NULL);
+}
+
+static ssize_t e1000_invm_cdev_read(struct cdev *cdev, void *buf,
+				    size_t count, loff_t offset, unsigned long flags)
+{
+	uint8_t n, bnr;
+	uint32_t line;
+	size_t chunk, residue = count;
+	struct e1000_hw *hw = container_of(cdev, struct e1000_hw, invm.cdev);
+
+	n = offset / sizeof(line);
+	if (n > E1000_INVM_DATA_MAX_N)
+		return -EINVAL;
+
+	bnr = offset % sizeof(line);
+	if (bnr) {
+		/*
+		 * if bnr in not zero it means we have a non 4-byte
+		 * aligned start and need to do a partial read
+		 */
+		const uint8_t *bptr;
+
+		bptr  = (uint8_t *)&line + bnr;
+		chunk = min(bnr - sizeof(line), count);
+		line  = e1000_read_reg(hw, E1000_INVM_DATA(n));
+		line  = cpu_to_le32(line); /* to account for readl */
+		memcpy(buf, bptr, chunk);
+
+		goto start_adjusted;
+	}
+
+	do {
+		if (n > E1000_INVM_DATA_MAX_N)
+			return -EINVAL;
+
+		chunk = min(sizeof(line), residue);
+		line = e1000_read_reg(hw, E1000_INVM_DATA(n));
+		line = cpu_to_le32(line); /* to account for readl */
+
+		/*
+		 * by using memcpy in conjunction with min should get
+		 * dangling tail reads as well as aligned reads
+		 */
+		memcpy(buf, &line, chunk);
+
+	start_adjusted:
+		residue -= chunk;
+		buf += chunk;
+		n++;
+	} while (residue);
+
+	return count;
+}
+
+static int e1000_invm_program(struct e1000_hw *hw, u32 offset, u32 value,
+			      unsigned int delay)
+{
+	int retries = 400;
+	do {
+		if ((e1000_read_reg(hw, offset) & value) == value)
+			return E1000_SUCCESS;
+
+		e1000_write_reg(hw, offset, value);
+
+		if (delay) {
+			udelay(delay);
+		} else {
+			int ret;
+
+			if (e1000_read_reg(hw, E1000_INVM_PROTECT) &
+			    E1000_INVM_PROTECT_WRITE_ERROR) {
+				dev_err(hw->dev, "Error while writing to %x\n", offset);
+				return -EIO;
+			}
+
+			ret = e1000_poll_reg(hw, E1000_INVM_PROTECT,
+					     E1000_INVM_PROTECT_BUSY,
+					     0,  SECOND);
+			if (ret < 0) {
+				dev_err(hw->dev,
+					"Timeout while waiting for INVM_PROTECT.BUSY\n");
+				return ret;
+			}
+		}
+	} while (retries--);
+
+	return -ETIMEDOUT;
+}
+
+static int e1000_invm_set_lock(struct param_d *param, void *priv)
+{
+	struct e1000_hw *hw = priv;
+
+	if (hw->invm.line > 31)
+		return -EINVAL;
+
+	return e1000_invm_program(hw,
+				  E1000_INVM_LOCK(hw->invm.line),
+				  E1000_INVM_LOCK_BIT,
+				  10);
+}
+
+static int e1000_invm_unlock(struct e1000_hw *hw)
+{
+	e1000_write_reg(hw, E1000_INVM_PROTECT, E1000_INVM_PROTECT_CODE);
+	/*
+	 * If we were successful at unlocking iNVM for programming we
+	 * should see ALLOW_WRITE bit toggle to 1
+	 */
+	if (!(e1000_read_reg(hw, E1000_INVM_PROTECT) &
+	      E1000_INVM_PROTECT_ALLOW_WRITE))
+		return -EIO;
+	else
+		return E1000_SUCCESS;
+}
+
+static void e1000_invm_lock(struct e1000_hw *hw)
+{
+	e1000_write_reg(hw, E1000_INVM_PROTECT, 0);
+}
+
+static int e1000_invm_write_prepare(struct e1000_hw *hw)
+{
+	int ret;
+	/*
+	 * This needs to be done accorging to the datasheet p. 541 and
+	 * p. 79
+	*/
+	e1000_write_reg(hw, E1000_PCIEMISC,
+			E1000_PCIEMISC_RESERVED_PATTERN1 |
+			E1000_PCIEMISC_DMA_IDLE          |
+			E1000_PCIEMISC_RESERVED_PATTERN2);
+
+	/*
+	 * Needed for programming iNVM on devices with Flash with valid
+	 * contents attached
+	 */
+	ret = e1000_poll_reg(hw, E1000_EEMNGCTL,
+			     E1000_EEMNGCTL_CFG_DONE,
+			     E1000_EEMNGCTL_CFG_DONE, SECOND);
+	if (ret < 0) {
+		dev_err(hw->dev,
+			"Timeout while waiting for EEMNGCTL.CFG_DONE\n");
+		return ret;
+	}
+
+	udelay(15);
+
+	return E1000_SUCCESS;
+}
+
+static ssize_t e1000_invm_cdev_write(struct cdev *cdev, const void *buf,
+				     size_t count, loff_t offset, unsigned long flags)
+{
+	int ret;
+	uint8_t n, bnr;
+	uint32_t line;
+	size_t chunk, residue = count;
+	struct e1000_hw *hw = container_of(cdev, struct e1000_hw, invm.cdev);
+
+	ret = e1000_invm_write_prepare(hw);
+	if (ret < 0)
+		return ret;
+
+	ret = e1000_invm_unlock(hw);
+	if (ret < 0)
+		goto exit;
+
+	n = offset / sizeof(line);
+	if (n > E1000_INVM_DATA_MAX_N) {
+		ret = -EINVAL;
+		goto exit;
+	}
+
+	bnr = offset % sizeof(line);
+	if (bnr) {
+		uint8_t *bptr;
+		/*
+		 * if bnr in not zero it means we have a non 4-byte
+		 * aligned start and need to do a read-modify-write
+		 * sequence
+		 */
+
+		/* Read */
+		line = e1000_read_reg(hw, E1000_INVM_DATA(n));
+
+		/* Modify */
+		/*
+		 * We need to ensure that line is LE32 in order for
+		 * memcpy to copy byte from least significant to most
+		 * significant, since that's how i210 will write the
+		 * 32-bit word out to OTP
+		 */
+		line = cpu_to_le32(line);
+		bptr  = (uint8_t *)&line + bnr;
+		chunk = min(sizeof(line) - bnr, count);
+		memcpy(bptr, buf, chunk);
+		line = le32_to_cpu(line);
+
+		/* Jumping inside of the loop to take care of the
+		 * Write */
+		goto start_adjusted;
+	}
+
+	do {
+		if (n > E1000_INVM_DATA_MAX_N) {
+			ret = -EINVAL;
+			goto exit;
+		}
+
+		chunk = min(sizeof(line), residue);
+		if (chunk != sizeof(line)) {
+			/*
+			 * If chunk is smaller that sizeof(line), which
+			 * should be 4 bytes, we have a "dangling"
+			 * chunk and we should read the unchanged
+			 * portion of the 4-byte word from iNVM and do
+			 * a read-modify-write sequence
+			 */
+			line = e1000_read_reg(hw, E1000_INVM_DATA(n));
+		}
+
+		line = cpu_to_le32(line);
+		memcpy(&line, buf, chunk);
+		line = le32_to_cpu(line);
+
+	start_adjusted:
+		/*
+		 * iNVM is organized in 32 64-bit lines and each of
+		 * those lines can be locked to prevent any further
+		 * modification, so for every i-th 32-bit word we need
+		 * to check INVM_LINE[i/2] register to see if that word
+		 * can be modified
+		 */
+		if (e1000_read_reg(hw, E1000_INVM_LOCK(n / 2)) &
+		    E1000_INVM_LOCK_BIT) {
+			dev_err(hw->dev, "line %d is locked\n", n / 2);
+			ret = -EIO;
+			goto exit;
+		}
+
+		ret = e1000_invm_program(hw,
+					 E1000_INVM_DATA(n),
+					 line,
+					 0);
+		if (ret < 0)
+			goto exit;
+
+		residue -= chunk;
+		buf += chunk;
+		n++;
+	} while (residue);
+
+	ret = E1000_SUCCESS;
+exit:
+	e1000_invm_lock(hw);
+	return ret;
+}
+
+static struct cdev_operations e1000_invm_ops = {
+	.read	= e1000_invm_cdev_read,
+	.write	= e1000_invm_cdev_write,
+};
+
+static ssize_t e1000_eeprom_cdev_read(struct cdev *cdev, void *buf,
+				      size_t count, loff_t offset, unsigned long flags)
+{
+	struct e1000_hw *hw = container_of(cdev, struct e1000_hw, eepromcdev);
+	int32_t ret;
+
+	/*
+	 * The eeprom interface works on 16 bit words which gives a nice excuse
+	 * for being lazy and not implementing unaligned reads.
+	 */
+	if (offset & 1 || count == 1)
+		return -EIO;
+
+	ret = e1000_read_eeprom(hw, offset / 2, count / 2, buf);
+	if (ret)
+		return -EIO;
+	else
+		return (count / 2) * 2;
+};
+
+static struct cdev_operations e1000_eeprom_ops = {
+	.read = e1000_eeprom_cdev_read,
+};
+
+static int e1000_mtd_read_or_write(bool read,
+				   struct mtd_info *mtd, loff_t off, size_t len,
+				   size_t *retlen, u_char *buf)
+{
+	int ret;
+	struct e1000_hw *hw = container_of(mtd, struct e1000_hw, mtd);
+
+	DEBUGFUNC();
+
+	if (e1000_acquire_eeprom(hw) == E1000_SUCCESS) {
+		if (read)
+			ret = e1000_flash_mode_read(hw, off,
+						    len, buf);
+		else
+			ret = e1000_flash_mode_write(hw, off,
+						     len, buf);
+		if (ret == E1000_SUCCESS)
+			*retlen = len;
+
+		e1000_release_eeprom(hw);
+	} else {
+		ret = -E1000_ERR_EEPROM;
+	}
+
+	return ret;
+
+}
+
+static int e1000_mtd_read(struct mtd_info *mtd, loff_t from, size_t len,
+				 size_t *retlen, u_char *buf)
+{
+	return e1000_mtd_read_or_write(true,
+				       mtd, from, len, retlen, buf);
+}
+
+static int e1000_mtd_write(struct mtd_info *mtd, loff_t to, size_t len,
+			   size_t *retlen, const u_char *buf)
+{
+	return e1000_mtd_read_or_write(false,
+				       mtd, to, len, retlen, (u_char *)buf);
+}
+
+static int e1000_mtd_erase(struct mtd_info *mtd, struct erase_info *instr)
+{
+	uint32_t rem;
+	struct e1000_hw *hw = container_of(mtd, struct e1000_hw, mtd);
+	int ret;
+
+	div_u64_rem(instr->len, mtd->erasesize, &rem);
+	if (rem)
+		return -EINVAL;
+
+	ret = e1000_acquire_eeprom(hw);
+	if (ret != E1000_SUCCESS)
+		goto fail;
+
+	/*
+	 * If mtd->size is 4096 it means we are dealing with
+	 * unprogrammed flash and we don't really know its size to
+	 * make an informed decision wheither to erase the whole chip or
+	 * just a number of its sectors
+	 */
+	if (mtd->size > SZ_4K &&
+	    instr->len == mtd->size)
+		ret = e1000_flash_mode_erase(hw, 0, 0);
+	else
+		ret = e1000_flash_mode_erase(hw,
+					     instr->addr, instr->len);
+
+	e1000_release_eeprom(hw);
+
+	if (ret < 0)
+		goto fail;
+
+	return 0;
+
+fail:
+	return ret;
+}
+
+static int e1000_mtd_sr_rmw(struct mtd_info *mtd, u8 mask, u8 val)
+{
+	struct e1000_hw *hw = container_of(mtd, struct e1000_hw, mtd);
+	uint32_t flswdata;
+	int ret;
+
+	ret = e1000_flash_mode_wait_for_idle(hw);
+	if (ret < 0)
+		return ret;
+
+	e1000_write_reg(hw, E1000_FLSWCNT, 1);
+	e1000_flash_cmd(hw, E1000_FLSWCTL_CMD_RDSR, 0);
+
+	ret = e1000_flash_mode_check_command_valid(hw);
+	if (ret < 0)
+		return -EIO;
+
+	ret = e1000_poll_reg(hw, E1000_FLSWCTL,
+			     E1000_FLSWCTL_DONE, E1000_FLSWCTL_DONE,
+			     SECOND);
+	if (ret < 0) {
+		dev_err(hw->dev,
+			"Timeout waiting for FLSWCTL.DONE to be set (RDSR)\n");
+		return ret;
+	}
+
+	flswdata = e1000_read_reg(hw, E1000_FLSWDATA);
+
+	flswdata = (flswdata & ~mask) | val;
+
+	e1000_write_reg(hw, E1000_FLSWCNT, 1);
+	e1000_flash_cmd(hw, E1000_FLSWCTL_CMD_WRSR, 0);
+
+	ret = e1000_flash_mode_check_command_valid(hw);
+	if (ret < 0)
+		return -EIO;
+
+	e1000_write_reg(hw, E1000_FLSWDATA, flswdata);
+
+	ret = e1000_poll_reg(hw, E1000_FLSWCTL,
+			     E1000_FLSWCTL_DONE, E1000_FLSWCTL_DONE,
+			     SECOND);
+	if (ret < 0) {
+		dev_err(hw->dev,
+			"Timeout waiting for FLSWCTL.DONE to be set (WRSR)\n");
+	}
+
+	return ret;
+}
+
+/*
+ * The available spi nor devices are very different in how the block protection
+ * bits affect which sectors to be protected. So take the simple approach and
+ * only use BP[012] = b000 (unprotected) and BP[012] = b111 (protected).
+ */
+#define SR_BPALL (SR_BP0 | SR_BP1 | SR_BP2)
+
+static int e1000_mtd_lock(struct mtd_info *mtd, loff_t ofs, size_t len)
+{
+	return e1000_mtd_sr_rmw(mtd, SR_BPALL, SR_BPALL);
+}
+
+static int e1000_mtd_unlock(struct mtd_info *mtd, loff_t ofs, size_t len)
+{
+	return e1000_mtd_sr_rmw(mtd, SR_BPALL, 0x0);
+}
+
+static int e1000_register_invm(struct e1000_hw *hw)
+{
+	int ret;
+	u16 word;
+	struct param_d *p;
+
+	if (e1000_eeprom_valid(hw)) {
+		ret = e1000_read_eeprom(hw, 0x0a, 1, &word);
+		if (ret < 0)
+			return ret;
+
+		if (word & (1 << 15))
+			dev_warn(hw->dev, "iNVM lockout mechanism is active\n");
+	}
+
+	hw->invm.cdev.dev = hw->dev;
+	hw->invm.cdev.ops = &e1000_invm_ops;
+	hw->invm.cdev.priv = hw;
+	hw->invm.cdev.name = xasprintf("e1000-invm%d", hw->dev->id);
+	hw->invm.cdev.size = 4 * (E1000_INVM_DATA_MAX_N + 1);
+
+	ret = devfs_create(&hw->invm.cdev);
+	if (ret < 0)
+		return ret;
+
+	dev_set_name(&hw->invm.dev, "invm");
+	hw->invm.dev.id = hw->dev->id;
+	hw->invm.dev.parent = hw->dev;
+	ret = register_device(&hw->invm.dev);
+	if (ret < 0) {
+		devfs_remove(&hw->invm.cdev);
+		return ret;
+	}
+
+	p = dev_add_param_int(&hw->invm.dev, "lock", e1000_invm_set_lock,
+			      NULL, &hw->invm.line, "%u", hw);
+	if (IS_ERR(p)) {
+		unregister_device(&hw->invm.dev);
+		devfs_remove(&hw->invm.cdev);
+		ret = PTR_ERR(p);
+	}
+
+	return ret;
+}
+
+/*
+ * This function has a wrong name for historic reasons, it doesn't add an
+ * eeprom, but the flash (if available) that is used to simulate the eeprom.
+ * Also a device that represents the invm is registered here (if available).
+ */
+int e1000_register_eeprom(struct e1000_hw *hw)
+{
+	struct e1000_eeprom_info *eeprom = &hw->eeprom;
+	uint32_t eecd;
+	int ret;
+
+	if (hw->mac_type != e1000_igb)
+		return E1000_SUCCESS;
+
+	eecd = e1000_read_reg(hw, E1000_EECD);
+
+	if (eecd & E1000_EECD_AUTO_RD) {
+		if (eecd & E1000_EECD_EE_PRES) {
+			if (eecd & E1000_EECD_FLASH_IN_USE) {
+				uint32_t fla = e1000_read_reg(hw, E1000_FLA);
+				dev_info(hw->dev,
+					 "Hardware programmed from flash (%ssecure)\n",
+					 fla & E1000_FLA_LOCKED ? "" : "un");
+			} else {
+				dev_info(hw->dev, "Hardware programmed from iNVM\n");
+			}
+		} else {
+			dev_warn(hw->dev, "Shadow RAM invalid\n");
+		}
+	} else {
+		/*
+		 * I never saw this case in practise and I'm unsure how
+		 * to handle that. Maybe just wait until the hardware is
+		 * up enough that this bit is set?
+		 */
+		dev_err(hw->dev, "Flash Auto-Read not done\n");
+	}
+
+	if (e1000_eeprom_valid(hw)) {
+		hw->eepromcdev.dev = hw->dev;
+		hw->eepromcdev.ops = &e1000_eeprom_ops;
+		hw->eepromcdev.name = xasprintf("e1000-eeprom%d",
+						hw->dev->id);
+		hw->eepromcdev.size = 0x1000;
+
+		ret = devfs_create(&hw->eepromcdev);
+		if (ret < 0)
+			return ret;
+	}
+
+	if (eecd & E1000_EECD_I210_FLASH_DETECTED) {
+		hw->mtd.dev.parent = hw->dev;
+		hw->mtd._read = e1000_mtd_read;
+		hw->mtd._write = e1000_mtd_write;
+		hw->mtd._erase = e1000_mtd_erase;
+		hw->mtd._lock = e1000_mtd_lock;
+		hw->mtd._unlock = e1000_mtd_unlock;
+		hw->mtd.size = eeprom->word_size * 2;
+		hw->mtd.writesize = 1;
+		hw->mtd.subpage_sft = 0;
+
+		hw->mtd.eraseregions = xzalloc(sizeof(struct mtd_erase_region_info));
+		hw->mtd.erasesize = SZ_4K;
+		hw->mtd.eraseregions[0].erasesize = SZ_4K;
+		hw->mtd.eraseregions[0].numblocks = hw->mtd.size / SZ_4K;
+		hw->mtd.numeraseregions = 1;
+
+		hw->mtd.flags = MTD_CAP_NORFLASH;
+		hw->mtd.type = MTD_NORFLASH;
+
+		ret = add_mtd_device(&hw->mtd, "e1000-nor",
+				     DEVICE_ID_DYNAMIC);
+		if (ret)
+			goto out_eeprom;
+	}
+
+	ret = e1000_register_invm(hw);
+	if (ret < 0)
+		goto out_mtd;
+
+	return E1000_SUCCESS;
+
+out_mtd:
+	if (eecd & E1000_EECD_I210_FLASH_DETECTED)
+		del_mtd_device(&hw->mtd);
+out_eeprom:
+	if (e1000_eeprom_valid(hw))
+		devfs_remove(&hw->eepromcdev);
+
+	return ret;
+}
-- 
2.30.2


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^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH 1/5] net: drop Calxeda Highbank xgmac driver support
  2021-08-12 12:19 [PATCH 1/5] net: drop Calxeda Highbank xgmac driver support Ahmad Fatoum
                   ` (3 preceding siblings ...)
  2021-08-12 12:19 ` [PATCH 5/5] net: e1000: split EEPROM and barebox MTD wrapper into separate files Ahmad Fatoum
@ 2021-08-12 13:03 ` Ahmad Fatoum
  2021-08-18  4:46 ` Sascha Hauer
  5 siblings, 0 replies; 7+ messages in thread
From: Ahmad Fatoum @ 2021-08-12 13:03 UTC (permalink / raw)
  To: barebox

On 12.08.21 14:19, Ahmad Fatoum wrote:
> Support for MACH_HIGHBANK was removed in f0f96c3322d5
> ("ARM: remove Calxeda Highbank support"). There are no device trees
> either barebox or upstream using this network controller, so remove
> the driver as well.
> 
> Fixes: f0f96c3322d5 ("ARM: remove Calxeda Highbank support")
> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>

Should've added a cover letter. With the recent virtio/dma and PCI
additions for x86, many network drivers can now be newly enabled
on x86, yielding different warnings/errors.

This series fixes that up.

> ---
>  drivers/net/Kconfig  |   4 -
>  drivers/net/Makefile |   1 -
>  drivers/net/xgmac.c  | 734 -------------------------------------------
>  3 files changed, 739 deletions(-)
>  delete mode 100644 drivers/net/xgmac.c
> 
> diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
> index 802169a86e8c..4a290bebbd75 100644
> --- a/drivers/net/Kconfig
> +++ b/drivers/net/Kconfig
> @@ -39,10 +39,6 @@ config DRIVER_NET_AT91_ETHER
>  	depends on HAS_AT91_ETHER
>  	select PHYLIB
>  
> -config DRIVER_NET_CALXEDA_XGMAC
> -	bool "Calxeda xgmac"
> -	depends on HAS_DMA
> -
>  config DRIVER_NET_CS8900
>  	bool "cs8900 ethernet driver"
>  	depends on HAS_CS8900 || COMPILE_TEST
> diff --git a/drivers/net/Makefile b/drivers/net/Makefile
> index fb3e3bdee46a..e5eede634e63 100644
> --- a/drivers/net/Makefile
> +++ b/drivers/net/Makefile
> @@ -4,7 +4,6 @@ obj-$(CONFIG_NET_USB)			+= usb/
>  obj-$(CONFIG_DRIVER_NET_AR231X)		+= ar231x.o
>  obj-$(CONFIG_DRIVER_NET_ARC_EMAC)	+= arc_emac.o
>  obj-$(CONFIG_DRIVER_NET_AT91_ETHER)	+= at91_ether.o
> -obj-$(CONFIG_DRIVER_NET_CALXEDA_XGMAC)	+= xgmac.o
>  obj-$(CONFIG_DRIVER_NET_CS8900)		+= cs8900.o
>  obj-$(CONFIG_DRIVER_NET_CPSW)		+= cpsw.o
>  obj-$(CONFIG_DRIVER_NET_DAVINCI_EMAC)	+= davinci_emac.o
> diff --git a/drivers/net/xgmac.c b/drivers/net/xgmac.c
> deleted file mode 100644
> index 136d78804349..000000000000
> --- a/drivers/net/xgmac.c
> +++ /dev/null
> @@ -1,734 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-or-later
> -/*
> - * Copyright 2010-2011 Calxeda, Inc.
> - */
> -
> -#include <common.h>
> -#include <dma.h>
> -#include <net.h>
> -#include <clock.h>
> -#include <malloc.h>
> -#include <xfuncs.h>
> -#include <init.h>
> -#include <errno.h>
> -#include <io.h>
> -#include <linux/err.h>
> -
> -#define TX_NUM_DESC			1
> -#define RX_NUM_DESC			32
> -
> -#define ETH_BUF_SZ			2048
> -#define TX_BUF_SZ			(ETH_BUF_SZ * TX_NUM_DESC)
> -#define RX_BUF_SZ			(ETH_BUF_SZ * RX_NUM_DESC)
> -
> -/* XGMAC Register definitions */
> -#define XGMAC_CONTROL		0x00000000	/* MAC Configuration */
> -#define XGMAC_FRAME_FILTER	0x00000004	/* MAC Frame Filter */
> -#define XGMAC_FLOW_CTRL		0x00000018	/* MAC Flow Control */
> -#define XGMAC_VLAN_TAG		0x0000001C	/* VLAN Tags */
> -#define XGMAC_VERSION		0x00000020	/* Version */
> -#define XGMAC_VLAN_INCL		0x00000024	/* VLAN tag for tx frames */
> -#define XGMAC_LPI_CTRL		0x00000028	/* LPI Control and Status */
> -#define XGMAC_LPI_TIMER		0x0000002C	/* LPI Timers Control */
> -#define XGMAC_TX_PACE		0x00000030	/* Transmit Pace and Stretch */
> -#define XGMAC_VLAN_HASH		0x00000034	/* VLAN Hash Table */
> -#define XGMAC_DEBUG		0x00000038	/* Debug */
> -#define XGMAC_INT_STAT		0x0000003C	/* Interrupt and Control */
> -#define XGMAC_ADDR_HIGH(reg)	(0x00000040 + ((reg) * 8))
> -#define XGMAC_ADDR_LOW(reg)	(0x00000044 + ((reg) * 8))
> -#define XGMAC_HASH(n)		(0x00000300 + (n) * 4) /* HASH table regs */
> -#define XGMAC_NUM_HASH		16
> -#define XGMAC_OMR		0x00000400
> -#define XGMAC_REMOTE_WAKE	0x00000700	/* Remote Wake-Up Frm Filter */
> -#define XGMAC_PMT		0x00000704	/* PMT Control and Status */
> -#define XGMAC_MMC_CTRL		0x00000800	/* XGMAC MMC Control */
> -#define XGMAC_MMC_INTR_RX	0x00000804	/* Recieve Interrupt */
> -#define XGMAC_MMC_INTR_TX	0x00000808	/* Transmit Interrupt */
> -#define XGMAC_MMC_INTR_MASK_RX	0x0000080c	/* Recieve Interrupt Mask */
> -#define XGMAC_MMC_INTR_MASK_TX	0x00000810	/* Transmit Interrupt Mask */
> -
> -
> -/* Hardware TX Statistics Counters */
> -#define XGMAC_MMC_TXOCTET_GB_LO	0x00000814
> -#define XGMAC_MMC_TXOCTET_GB_HI	0x00000818
> -#define XGMAC_MMC_TXFRAME_GB_LO	0x0000081C
> -#define XGMAC_MMC_TXFRAME_GB_HI	0x00000820
> -#define XGMAC_MMC_TXBCFRAME_G	0x00000824
> -#define XGMAC_MMC_TXMCFRAME_G	0x0000082C
> -#define XGMAC_MMC_TXUCFRAME_GB	0x00000864
> -#define XGMAC_MMC_TXMCFRAME_GB	0x0000086C
> -#define XGMAC_MMC_TXBCFRAME_GB	0x00000874
> -#define XGMAC_MMC_TXUNDERFLOW	0x0000087C
> -#define XGMAC_MMC_TXOCTET_G_LO	0x00000884
> -#define XGMAC_MMC_TXOCTET_G_HI	0x00000888
> -#define XGMAC_MMC_TXFRAME_G_LO	0x0000088C
> -#define XGMAC_MMC_TXFRAME_G_HI	0x00000890
> -#define XGMAC_MMC_TXPAUSEFRAME	0x00000894
> -#define XGMAC_MMC_TXVLANFRAME	0x0000089C
> -
> -/* Hardware RX Statistics Counters */
> -#define XGMAC_MMC_RXFRAME_GB_LO	0x00000900
> -#define XGMAC_MMC_RXFRAME_GB_HI	0x00000904
> -#define XGMAC_MMC_RXOCTET_GB_LO	0x00000908
> -#define XGMAC_MMC_RXOCTET_GB_HI	0x0000090C
> -#define XGMAC_MMC_RXOCTET_G_LO	0x00000910
> -#define XGMAC_MMC_RXOCTET_G_HI	0x00000914
> -#define XGMAC_MMC_RXBCFRAME_G	0x00000918
> -#define XGMAC_MMC_RXMCFRAME_G	0x00000920
> -#define XGMAC_MMC_RXCRCERR	0x00000928
> -#define XGMAC_MMC_RXRUNT	0x00000930
> -#define XGMAC_MMC_RXJABBER	0x00000934
> -#define XGMAC_MMC_RXUCFRAME_G	0x00000970
> -#define XGMAC_MMC_RXLENGTHERR	0x00000978
> -#define XGMAC_MMC_RXPAUSEFRAME	0x00000988
> -#define XGMAC_MMC_RXOVERFLOW	0x00000990
> -#define XGMAC_MMC_RXVLANFRAME	0x00000998
> -#define XGMAC_MMC_RXWATCHDOG	0x000009a0
> -
> -/* DMA Control and Status Registers */
> -#define XGMAC_DMA_BUS_MODE	0x00000f00	/* Bus Mode */
> -#define XGMAC_DMA_TX_POLL	0x00000f04	/* Transmit Poll Demand */
> -#define XGMAC_DMA_RX_POLL	0x00000f08	/* Received Poll Demand */
> -#define XGMAC_DMA_RX_BASE_ADDR	0x00000f0c	/* Receive List Base */
> -#define XGMAC_DMA_TX_BASE_ADDR	0x00000f10	/* Transmit List Base */
> -#define XGMAC_DMA_STATUS	0x00000f14	/* Status Register */
> -#define XGMAC_DMA_CONTROL	0x00000f18	/* Ctrl (Operational Mode) */
> -#define XGMAC_DMA_INTR_ENA	0x00000f1c	/* Interrupt Enable */
> -#define XGMAC_DMA_MISS_FRAME_CTR 0x00000f20	/* Missed Frame Counter */
> -#define XGMAC_DMA_RI_WDOG_TIMER	0x00000f24	/* RX Intr Watchdog Timer */
> -#define XGMAC_DMA_AXI_BUS	0x00000f28	/* AXI Bus Mode */
> -#define XGMAC_DMA_AXI_STATUS	0x00000f2C	/* AXI Status */
> -#define XGMAC_DMA_HW_FEATURE	0x00000f58	/* Enabled Hardware Features */
> -
> -#define XGMAC_ADDR_AE		0x80000000
> -#define XGMAC_MAX_FILTER_ADDR	31
> -
> -/* PMT Control and Status */
> -#define XGMAC_PMT_POINTER_RESET	0x80000000
> -#define XGMAC_PMT_GLBL_UNICAST	0x00000200
> -#define XGMAC_PMT_WAKEUP_RX_FRM	0x00000040
> -#define XGMAC_PMT_MAGIC_PKT	0x00000020
> -#define XGMAC_PMT_WAKEUP_FRM_EN	0x00000004
> -#define XGMAC_PMT_MAGIC_PKT_EN	0x00000002
> -#define XGMAC_PMT_POWERDOWN	0x00000001
> -
> -#define XGMAC_CONTROL_SPD	0x40000000	/* Speed control */
> -#define XGMAC_CONTROL_SPD_MASK	0x60000000
> -#define XGMAC_CONTROL_SPD_1G	0x60000000
> -#define XGMAC_CONTROL_SPD_2_5G	0x40000000
> -#define XGMAC_CONTROL_SPD_10G	0x00000000
> -#define XGMAC_CONTROL_SARC	0x10000000	/* Source Addr Insert/Replace */
> -#define XGMAC_CONTROL_SARK_MASK	0x18000000
> -#define XGMAC_CONTROL_CAR	0x04000000	/* CRC Addition/Replacement */
> -#define XGMAC_CONTROL_CAR_MASK	0x06000000
> -#define XGMAC_CONTROL_DP	0x01000000	/* Disable Padding */
> -#define XGMAC_CONTROL_WD	0x00800000	/* Disable Watchdog on rx */
> -#define XGMAC_CONTROL_JD	0x00400000	/* Jabber disable */
> -#define XGMAC_CONTROL_JE	0x00100000	/* Jumbo frame */
> -#define XGMAC_CONTROL_LM	0x00001000	/* Loop-back mode */
> -#define XGMAC_CONTROL_IPC	0x00000400	/* Checksum Offload */
> -#define XGMAC_CONTROL_ACS	0x00000080	/* Automatic Pad/FCS Strip */
> -#define XGMAC_CONTROL_DDIC	0x00000010	/* Disable Deficit Idle Count */
> -#define XGMAC_CONTROL_TE	0x00000008	/* Transmitter Enable */
> -#define XGMAC_CONTROL_RE	0x00000004	/* Receiver Enable */
> -
> -/* XGMAC Frame Filter defines */
> -#define XGMAC_FRAME_FILTER_PR	0x00000001	/* Promiscuous Mode */
> -#define XGMAC_FRAME_FILTER_HUC	0x00000002	/* Hash Unicast */
> -#define XGMAC_FRAME_FILTER_HMC	0x00000004	/* Hash Multicast */
> -#define XGMAC_FRAME_FILTER_DAIF	0x00000008	/* DA Inverse Filtering */
> -#define XGMAC_FRAME_FILTER_PM	0x00000010	/* Pass all multicast */
> -#define XGMAC_FRAME_FILTER_DBF	0x00000020	/* Disable Broadcast frames */
> -#define XGMAC_FRAME_FILTER_SAIF	0x00000100	/* Inverse Filtering */
> -#define XGMAC_FRAME_FILTER_SAF	0x00000200	/* Source Address Filter */
> -#define XGMAC_FRAME_FILTER_HPF	0x00000400	/* Hash or perfect Filter */
> -#define XGMAC_FRAME_FILTER_VHF	0x00000800	/* VLAN Hash Filter */
> -#define XGMAC_FRAME_FILTER_VPF	0x00001000	/* VLAN Perfect Filter */
> -#define XGMAC_FRAME_FILTER_RA	0x80000000	/* Receive all mode */
> -
> -#define FIFO_MINUS_1K			0x0
> -#define FIFO_MINUS_2K			0x1
> -#define FIFO_MINUS_3K			0x2
> -#define FIFO_MINUS_4K			0x3
> -#define FIFO_MINUS_6K			0x4
> -#define FIFO_MINUS_8K			0x5
> -#define FIFO_MINUS_12K			0x6
> -#define FIFO_MINUS_16K			0x7
> -
> -/* XGMAC FLOW CTRL defines */
> -#define XGMAC_FLOW_CTRL_PT_MASK	0xffff0000	/* Pause Time Mask */
> -#define XGMAC_FLOW_CTRL_PT_SHIFT	16
> -#define XGMAC_FLOW_CTRL_DZQP	0x00000080	/* Disable Zero-Quanta Phase */
> -#define XGMAC_FLOW_CTRL_PLT	0x00000020	/* Pause Low Threshhold */
> -#define XGMAC_FLOW_CTRL_PLT_SHIFT	4
> -#define XGMAC_FLOW_CTRL_PLT_MASK 0x00000030	/* PLT MASK */
> -#define XGMAC_FLOW_CTRL_UP	0x00000008	/* Unicast Pause Frame Detect */
> -#define XGMAC_FLOW_CTRL_RFE	0x00000004	/* Rx Flow Control Enable */
> -#define XGMAC_FLOW_CTRL_TFE	0x00000002	/* Tx Flow Control Enable */
> -#define XGMAC_FLOW_CTRL_FCB_BPA	0x00000001	/* Flow Control Busy ... */
> -
> -/* XGMAC_INT_STAT reg */
> -#define XGMAC_INT_STAT_PMT	0x0080		/* PMT Interrupt Status */
> -#define XGMAC_INT_STAT_LPI	0x0040		/* LPI Interrupt Status */
> -
> -/* DMA Bus Mode register defines */
> -#define DMA_BUS_MODE_SFT_RESET	0x00000001	/* Software Reset */
> -#define DMA_BUS_MODE_DSL_MASK	0x0000007c	/* Descriptor Skip Length */
> -#define DMA_BUS_MODE_DSL_SHIFT	2		/* (in DWORDS) */
> -#define DMA_BUS_MODE_ATDS	0x00000080	/* Alternate Descriptor Size */
> -
> -/* Programmable burst length */
> -#define DMA_BUS_MODE_PBL_MASK	0x00003f00	/* Programmable Burst Len */
> -#define DMA_BUS_MODE_PBL_SHIFT	8
> -#define DMA_BUS_MODE_FB		0x00010000	/* Fixed burst */
> -#define DMA_BUS_MODE_RPBL_MASK	0x003e0000	/* Rx-Programmable Burst Len */
> -#define DMA_BUS_MODE_RPBL_SHIFT	17
> -#define DMA_BUS_MODE_USP	0x00800000
> -#define DMA_BUS_MODE_8PBL	0x01000000
> -#define DMA_BUS_MODE_AAL	0x02000000
> -
> -#define DMA_AXIMODE_ENLPI	0x80000000
> -#define DMA_AXIMODE_MGK		0x40000000
> -#define DMA_AXIMODE_WROSR	0x00100000
> -#define DMA_AXIMODE_WROSR_MASK	0x00F00000
> -#define DMA_AXIMODE_WROSR_SHIFT	20
> -#define DMA_AXIMODE_RDOSR	0x00010000
> -#define DMA_AXIMODE_RDOSR_MASK	0x000F0000
> -#define DMA_AXIMODE_RDOSR_SHIFT	16
> -#define DMA_AXIMODE_AAL		0x00001000
> -#define DMA_AXIMODE_BLEN256	0x00000080
> -#define DMA_AXIMODE_BLEN128	0x00000040
> -#define DMA_AXIMODE_BLEN64	0x00000020
> -#define DMA_AXIMODE_BLEN32	0x00000010
> -#define DMA_AXIMODE_BLEN16	0x00000008
> -#define DMA_AXIMODE_BLEN8	0x00000004
> -#define DMA_AXIMODE_BLEN4	0x00000002
> -#define DMA_AXIMODE_UNDEF	0x00000001
> -
> -/* DMA Bus Mode register defines */
> -#define DMA_BUS_PR_RATIO_MASK	0x0000c000	/* Rx/Tx priority ratio */
> -#define DMA_BUS_PR_RATIO_SHIFT	14
> -#define DMA_BUS_FB		0x00010000	/* Fixed Burst */
> -
> -/* DMA Control register defines */
> -#define DMA_CONTROL_ST		0x00002000	/* Start/Stop Transmission */
> -#define DMA_CONTROL_SR		0x00000002	/* Start/Stop Receive */
> -#define DMA_CONTROL_DFF		0x01000000	/* Disable flush of rx frames */
> -
> -/* DMA Normal interrupt */
> -#define DMA_INTR_ENA_NIE	0x00010000	/* Normal Summary */
> -#define DMA_INTR_ENA_AIE	0x00008000	/* Abnormal Summary */
> -#define DMA_INTR_ENA_ERE	0x00004000	/* Early Receive */
> -#define DMA_INTR_ENA_FBE	0x00002000	/* Fatal Bus Error */
> -#define DMA_INTR_ENA_ETE	0x00000400	/* Early Transmit */
> -#define DMA_INTR_ENA_RWE	0x00000200	/* Receive Watchdog */
> -#define DMA_INTR_ENA_RSE	0x00000100	/* Receive Stopped */
> -#define DMA_INTR_ENA_RUE	0x00000080	/* Receive Buffer Unavailable */
> -#define DMA_INTR_ENA_RIE	0x00000040	/* Receive Interrupt */
> -#define DMA_INTR_ENA_UNE	0x00000020	/* Tx Underflow */
> -#define DMA_INTR_ENA_OVE	0x00000010	/* Receive Overflow */
> -#define DMA_INTR_ENA_TJE	0x00000008	/* Transmit Jabber */
> -#define DMA_INTR_ENA_TUE	0x00000004	/* Transmit Buffer Unavail */
> -#define DMA_INTR_ENA_TSE	0x00000002	/* Transmit Stopped */
> -#define DMA_INTR_ENA_TIE	0x00000001	/* Transmit Interrupt */
> -
> -#define DMA_INTR_NORMAL		(DMA_INTR_ENA_NIE | DMA_INTR_ENA_RIE | \
> -				 DMA_INTR_ENA_TUE)
> -
> -#define DMA_INTR_ABNORMAL	(DMA_INTR_ENA_AIE | DMA_INTR_ENA_FBE | \
> -				 DMA_INTR_ENA_RWE | DMA_INTR_ENA_RSE | \
> -				 DMA_INTR_ENA_RUE | DMA_INTR_ENA_UNE | \
> -				 DMA_INTR_ENA_OVE | DMA_INTR_ENA_TJE | \
> -				 DMA_INTR_ENA_TSE)
> -
> -/* DMA default interrupt mask */
> -#define DMA_INTR_DEFAULT_MASK	(DMA_INTR_NORMAL | DMA_INTR_ABNORMAL)
> -
> -/* DMA Status register defines */
> -#define DMA_STATUS_GMI		0x08000000	/* MMC interrupt */
> -#define DMA_STATUS_GLI		0x04000000	/* GMAC Line interface int */
> -#define DMA_STATUS_EB_MASK	0x00380000	/* Error Bits Mask */
> -#define DMA_STATUS_EB_TX_ABORT	0x00080000	/* Error Bits - TX Abort */
> -#define DMA_STATUS_EB_RX_ABORT	0x00100000	/* Error Bits - RX Abort */
> -#define DMA_STATUS_TS_MASK	0x00700000	/* Transmit Process State */
> -#define DMA_STATUS_TS_SHIFT	20
> -#define DMA_STATUS_RS_MASK	0x000e0000	/* Receive Process State */
> -#define DMA_STATUS_RS_SHIFT	17
> -#define DMA_STATUS_NIS		0x00010000	/* Normal Interrupt Summary */
> -#define DMA_STATUS_AIS		0x00008000	/* Abnormal Interrupt Summary */
> -#define DMA_STATUS_ERI		0x00004000	/* Early Receive Interrupt */
> -#define DMA_STATUS_FBI		0x00002000	/* Fatal Bus Error Interrupt */
> -#define DMA_STATUS_ETI		0x00000400	/* Early Transmit Interrupt */
> -#define DMA_STATUS_RWT		0x00000200	/* Receive Watchdog Timeout */
> -#define DMA_STATUS_RPS		0x00000100	/* Receive Process Stopped */
> -#define DMA_STATUS_RU		0x00000080	/* Receive Buffer Unavailable */
> -#define DMA_STATUS_RI		0x00000040	/* Receive Interrupt */
> -#define DMA_STATUS_UNF		0x00000020	/* Transmit Underflow */
> -#define DMA_STATUS_OVF		0x00000010	/* Receive Overflow */
> -#define DMA_STATUS_TJT		0x00000008	/* Transmit Jabber Timeout */
> -#define DMA_STATUS_TU		0x00000004	/* Transmit Buffer Unavail */
> -#define DMA_STATUS_TPS		0x00000002	/* Transmit Process Stopped */
> -#define DMA_STATUS_TI		0x00000001	/* Transmit Interrupt */
> -
> -/* Common MAC defines */
> -#define MAC_ENABLE_TX		0x00000008	/* Transmitter Enable */
> -#define MAC_ENABLE_RX		0x00000004	/* Receiver Enable */
> -
> -/* XGMAC Operation Mode Register */
> -#define XGMAC_OMR_TSF		0x00200000	/* TX FIFO Store and Forward */
> -#define XGMAC_OMR_FTF		0x00100000	/* Flush Transmit FIFO */
> -#define XGMAC_OMR_TTC		0x00020000	/* Transmit Threshhold Ctrl */
> -#define XGMAC_OMR_TTC_SHIFT	16
> -#define XGMAC_OMR_TTC_MASK	0x00030000
> -#define XGMAC_OMR_RFD		0x00006000	/* FC Deactivation Threshhold */
> -#define XGMAC_OMR_RFD_SHIFT	12
> -#define XGMAC_OMR_RFD_MASK	0x00007000	/* FC Deact Threshhold MASK */
> -#define XGMAC_OMR_RFA		0x00000600	/* FC Activation Threshhold */
> -#define XGMAC_OMR_RFA_SHIFT	9
> -#define XGMAC_OMR_RFA_MASK	0x00000E00	/* FC Act Threshhold MASK */
> -#define XGMAC_OMR_EFC		0x00000100	/* Enable Hardware FC */
> -#define XGMAC_OMR_FEF		0x00000080	/* Forward Error Frames */
> -#define XGMAC_OMR_DT		0x00000040	/* Drop TCP/IP csum Errors */
> -#define XGMAC_OMR_RSF		0x00000020	/* RX FIFO Store and Forward */
> -#define XGMAC_OMR_RTC_256	0x00000018	/* RX Threshhold Ctrl */
> -#define XGMAC_OMR_RTC_MASK	0x00000018	/* RX Threshhold Ctrl MASK */
> -
> -/* XGMAC HW Features Register */
> -#define DMA_HW_FEAT_TXCOESEL	0x00010000	/* TX Checksum offload */
> -
> -#define XGMAC_MMC_CTRL_CNT_FRZ	0x00000008
> -
> -/* XGMAC Descriptor Defines */
> -#define MAX_DESC_BUF_SZ		(0x2000 - 8)
> -
> -#define RXDESC_EXT_STATUS	0x00000001
> -#define RXDESC_CRC_ERR		0x00000002
> -#define RXDESC_RX_ERR		0x00000008
> -#define RXDESC_RX_WDOG		0x00000010
> -#define RXDESC_FRAME_TYPE	0x00000020
> -#define RXDESC_GIANT_FRAME	0x00000080
> -#define RXDESC_LAST_SEG		0x00000100
> -#define RXDESC_FIRST_SEG	0x00000200
> -#define RXDESC_VLAN_FRAME	0x00000400
> -#define RXDESC_OVERFLOW_ERR	0x00000800
> -#define RXDESC_LENGTH_ERR	0x00001000
> -#define RXDESC_SA_FILTER_FAIL	0x00002000
> -#define RXDESC_DESCRIPTOR_ERR	0x00004000
> -#define RXDESC_ERROR_SUMMARY	0x00008000
> -#define RXDESC_FRAME_LEN_OFFSET	16
> -#define RXDESC_FRAME_LEN_MASK	0x3fff0000
> -#define RXDESC_DA_FILTER_FAIL	0x40000000
> -
> -#define RXDESC1_END_RING	0x00008000
> -
> -#define RXDESC_IP_PAYLOAD_MASK	0x00000003
> -#define RXDESC_IP_PAYLOAD_UDP	0x00000001
> -#define RXDESC_IP_PAYLOAD_TCP	0x00000002
> -#define RXDESC_IP_PAYLOAD_ICMP	0x00000003
> -#define RXDESC_IP_HEADER_ERR	0x00000008
> -#define RXDESC_IP_PAYLOAD_ERR	0x00000010
> -#define RXDESC_IPV4_PACKET	0x00000040
> -#define RXDESC_IPV6_PACKET	0x00000080
> -#define TXDESC_UNDERFLOW_ERR	0x00000001
> -#define TXDESC_JABBER_TIMEOUT	0x00000002
> -#define TXDESC_LOCAL_FAULT	0x00000004
> -#define TXDESC_REMOTE_FAULT	0x00000008
> -#define TXDESC_VLAN_FRAME	0x00000010
> -#define TXDESC_FRAME_FLUSHED	0x00000020
> -#define TXDESC_IP_HEADER_ERR	0x00000040
> -#define TXDESC_PAYLOAD_CSUM_ERR	0x00000080
> -#define TXDESC_ERROR_SUMMARY	0x00008000
> -#define TXDESC_SA_CTRL_INSERT	0x00040000
> -#define TXDESC_SA_CTRL_REPLACE	0x00080000
> -#define TXDESC_2ND_ADDR_CHAINED	0x00100000
> -#define TXDESC_END_RING		0x00200000
> -#define TXDESC_CSUM_IP		0x00400000
> -#define TXDESC_CSUM_IP_PAYLD	0x00800000
> -#define TXDESC_CSUM_ALL		0x00C00000
> -#define TXDESC_CRC_EN_REPLACE	0x01000000
> -#define TXDESC_CRC_EN_APPEND	0x02000000
> -#define TXDESC_DISABLE_PAD	0x04000000
> -#define TXDESC_FIRST_SEG	0x10000000
> -#define TXDESC_LAST_SEG		0x20000000
> -#define TXDESC_INTERRUPT	0x40000000
> -
> -#define DESC_OWN		0x80000000
> -#define DESC_BUFFER1_SZ_MASK	0x00001fff
> -#define DESC_BUFFER2_SZ_MASK	0x1fff0000
> -#define DESC_BUFFER2_SZ_OFFSET	16
> -
> -struct xgmac_dma_desc {
> -	__le32 flags;
> -	__le32 buf_size;
> -	__le32 buf1_addr;		/* Buffer 1 Address Pointer */
> -	__le32 buf2_addr;		/* Buffer 2 Address Pointer */
> -	__le32 ext_status;
> -	__le32 res[3];
> -};
> -
> -struct xgmac_priv {
> -	struct xgmac_dma_desc *rx_chain;
> -	struct xgmac_dma_desc *tx_chain;
> -	char *rxbuffer;
> -
> -	u32 tx_currdesc;
> -	u32 rx_currdesc;
> -
> -	void __iomem *base;
> -
> -	struct eth_device edev;
> -	struct device_d *dev;
> -};
> -
> -/* XGMAC Descriptor Access Helpers */
> -static inline void desc_set_buf_len(struct xgmac_dma_desc *p, u32 buf_sz)
> -{
> -	if (buf_sz > MAX_DESC_BUF_SZ)
> -		p->buf_size = cpu_to_le32(MAX_DESC_BUF_SZ |
> -			(buf_sz - MAX_DESC_BUF_SZ) << DESC_BUFFER2_SZ_OFFSET);
> -	else
> -		p->buf_size = cpu_to_le32(buf_sz);
> -}
> -
> -static inline int desc_get_buf_len(struct xgmac_dma_desc *p)
> -{
> -	u32 len = le32_to_cpu(p->buf_size);
> -	return (len & DESC_BUFFER1_SZ_MASK) +
> -		((len & DESC_BUFFER2_SZ_MASK) >> DESC_BUFFER2_SZ_OFFSET);
> -}
> -
> -static inline void desc_init_rx_desc(struct xgmac_dma_desc *p, int ring_size,
> -				     int buf_sz)
> -{
> -	struct xgmac_dma_desc *end = p + ring_size - 1;
> -
> -	memset(p, 0, sizeof(*p) * ring_size);
> -
> -	for (; p <= end; p++)
> -		desc_set_buf_len(p, buf_sz);
> -
> -	end->buf_size |= cpu_to_le32(RXDESC1_END_RING);
> -}
> -
> -static inline void desc_init_tx_desc(struct xgmac_dma_desc *p, u32 ring_size)
> -{
> -	memset(p, 0, sizeof(*p) * ring_size);
> -	p[ring_size - 1].flags = cpu_to_le32(TXDESC_END_RING);
> -}
> -
> -static inline int desc_get_owner(struct xgmac_dma_desc *p)
> -{
> -	return le32_to_cpu(p->flags) & DESC_OWN;
> -}
> -
> -static inline void desc_set_rx_owner(struct xgmac_dma_desc *p)
> -{
> -	/* Clear all fields and set the owner */
> -	p->flags = cpu_to_le32(DESC_OWN);
> -}
> -
> -static inline void desc_set_tx_owner(struct xgmac_dma_desc *p, u32 flags)
> -{
> -	u32 tmpflags = le32_to_cpu(p->flags);
> -	tmpflags &= TXDESC_END_RING;
> -	tmpflags |= flags | DESC_OWN;
> -	p->flags = cpu_to_le32(tmpflags);
> -}
> -
> -static inline void *desc_get_buf_addr(struct xgmac_dma_desc *p)
> -{
> -	return (void *)le32_to_cpu(p->buf1_addr);
> -}
> -
> -static inline void desc_set_buf_addr(struct xgmac_dma_desc *p,
> -				     void *paddr, int len)
> -{
> -	p->buf1_addr = cpu_to_le32(paddr);
> -	if (len > MAX_DESC_BUF_SZ)
> -		p->buf2_addr = cpu_to_le32(paddr + MAX_DESC_BUF_SZ);
> -}
> -
> -static inline void desc_set_buf_addr_and_size(struct xgmac_dma_desc *p,
> -					      void *paddr, int len)
> -{
> -	desc_set_buf_len(p, len);
> -	desc_set_buf_addr(p, paddr, len);
> -}
> -
> -static inline int desc_get_rx_frame_len(struct xgmac_dma_desc *p)
> -{
> -	u32 data = le32_to_cpu(p->flags);
> -	u32 len = (data & RXDESC_FRAME_LEN_MASK) >> RXDESC_FRAME_LEN_OFFSET;
> -	if (data & RXDESC_FRAME_TYPE)
> -		len -= 4;
> -
> -	return len;
> -}
> -
> -/*
> - * Initialize a descriptor ring.  Calxeda XGMAC is configured to use
> - * advanced descriptors.
> - */
> -
> -static void init_rx_desc(struct xgmac_priv *priv)
> -{
> -	struct xgmac_dma_desc *rxdesc = priv->rx_chain;
> -	void *rxbuffer = priv->rxbuffer;
> -	int i;
> -
> -	desc_init_rx_desc(rxdesc, RX_NUM_DESC, ETH_BUF_SZ);
> -	writel((ulong)rxdesc, priv->base + XGMAC_DMA_RX_BASE_ADDR);
> -
> -	for (i = 0; i < RX_NUM_DESC; i++) {
> -		desc_set_buf_addr(rxdesc + i, rxbuffer + (i * ETH_BUF_SZ),
> -				  ETH_BUF_SZ);
> -		desc_set_rx_owner(rxdesc + i);
> -	}
> -}
> -
> -static void init_tx_desc(struct xgmac_priv *priv)
> -{
> -	desc_init_tx_desc(priv->tx_chain, TX_NUM_DESC);
> -	writel((ulong)priv->tx_chain, priv->base + XGMAC_DMA_TX_BASE_ADDR);
> -}
> -
> -static int xgmac_reset(struct eth_device *dev)
> -{
> -	struct xgmac_priv *priv = dev->priv;
> -	int ret;
> -	u32 value;
> -
> -	value = readl(priv->base + XGMAC_CONTROL) & XGMAC_CONTROL_SPD_MASK;
> -
> -	writel(DMA_BUS_MODE_SFT_RESET, priv->base + XGMAC_DMA_BUS_MODE);
> -
> -	ret = wait_on_timeout(100 * MSECOND,
> -		!(readl(priv->base + XGMAC_DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET));
> -
> -	writel(value, priv->base + XGMAC_CONTROL);
> -
> -	return ret;
> -}
> -
> -static int xgmac_open(struct eth_device *edev)
> -{
> -	struct xgmac_priv *priv = edev->priv;
> -	int value;
> -	int ret;
> -
> -	ret = xgmac_reset(edev);
> -	if (ret)
> -		return ret;
> -
> -	/* set the AXI bus modes */
> -	value = DMA_BUS_MODE_ATDS |
> -		(16 << DMA_BUS_MODE_PBL_SHIFT) |
> -		DMA_BUS_MODE_FB | DMA_BUS_MODE_AAL;
> -	writel(value, priv->base + XGMAC_DMA_BUS_MODE);
> -
> -	value = DMA_AXIMODE_AAL | DMA_AXIMODE_BLEN16 |
> -		DMA_AXIMODE_BLEN8 | DMA_AXIMODE_BLEN4;
> -	writel(value, priv->base + XGMAC_DMA_AXI_BUS);
> -
> -	/* set flow control parameters and store and forward mode */
> -	value = (FIFO_MINUS_12K << XGMAC_OMR_RFD_SHIFT) |
> -		(FIFO_MINUS_4K << XGMAC_OMR_RFA_SHIFT) |
> -		XGMAC_OMR_EFC | XGMAC_OMR_TSF | XGMAC_OMR_RSF;
> -	writel(value, priv->base + XGMAC_OMR);
> -
> -	/* enable pause frames */
> -	value = (1024 << XGMAC_FLOW_CTRL_PT_SHIFT) |
> -		(1 << XGMAC_FLOW_CTRL_PLT_SHIFT) |
> -		XGMAC_FLOW_CTRL_UP | XGMAC_FLOW_CTRL_RFE | XGMAC_FLOW_CTRL_TFE;
> -	writel(value, priv->base + XGMAC_FLOW_CTRL);
> -
> -	/* Initialize the descriptor chains */
> -	init_rx_desc(priv);
> -	init_tx_desc(priv);
> -
> -	/* must set to 0, or when started up will cause issues */
> -	priv->tx_currdesc = 0;
> -	priv->rx_currdesc = 0;
> -
> -	/* set default core values */
> -	value = readl(priv->base + XGMAC_CONTROL);
> -	value &= XGMAC_CONTROL_SPD_MASK;
> -	value |= XGMAC_CONTROL_DDIC | XGMAC_CONTROL_ACS |
> -		XGMAC_CONTROL_IPC | XGMAC_CONTROL_CAR;
> -
> -	/* Everything is ready enable both mac and DMA */
> -	value |= XGMAC_CONTROL_RE | XGMAC_CONTROL_TE;
> -	writel(value, priv->base + XGMAC_CONTROL);
> -
> -	value = readl(priv->base + XGMAC_DMA_CONTROL);
> -	value |= DMA_CONTROL_SR | DMA_CONTROL_ST;
> -	writel(value, priv->base + XGMAC_DMA_CONTROL);
> -
> -	return 0;
> -}
> -
> -static int xgmac_send(struct eth_device *edev, void *packet, int length)
> -{
> -	struct xgmac_priv *priv = edev->priv;
> -	u32 currdesc = priv->tx_currdesc;
> -	struct xgmac_dma_desc *txdesc = &priv->tx_chain[currdesc];
> -	int ret;
> -
> -	dma_sync_single_for_device((unsigned long)packet, length, DMA_TO_DEVICE);
> -	desc_set_buf_addr_and_size(txdesc, packet, length);
> -	desc_set_tx_owner(txdesc, TXDESC_FIRST_SEG |
> -		TXDESC_LAST_SEG | TXDESC_CRC_EN_APPEND);
> -
> -	/* write poll demand */
> -	writel(1, priv->base + XGMAC_DMA_TX_POLL);
> -
> -	ret = wait_on_timeout(1 * SECOND, !desc_get_owner(txdesc));
> -	dma_sync_single_for_cpu((unsigned long)packet, length, DMA_TO_DEVICE);
> -	if (ret) {
> -		dev_err(priv->dev, "TX timeout\n");
> -		return ret;
> -	}
> -
> -	priv->tx_currdesc = (currdesc + 1) & (TX_NUM_DESC - 1);
> -	return 0;
> -}
> -
> -static int xgmac_recv(struct eth_device *edev)
> -{
> -	struct xgmac_priv *priv = edev->priv;
> -	u32 currdesc = priv->rx_currdesc;
> -	struct xgmac_dma_desc *rxdesc = &priv->rx_chain[currdesc];
> -	int length = 0;
> -	void *buf_addr;
> -
> -	/* check if the host has the desc */
> -	if (desc_get_owner(rxdesc))
> -		return -1; /* something bad happened */
> -
> -	length = desc_get_rx_frame_len(rxdesc);
> -	buf_addr = desc_get_buf_addr(rxdesc);
> -
> -	dma_sync_single_for_cpu((unsigned long)buf_addr, length, DMA_FROM_DEVICE);
> -	net_receive(edev, buf_addr, length);
> -	dma_sync_single_for_device((unsigned long)buf_addr, length,
> -				   DMA_FROM_DEVICE);
> -
> -	/* set descriptor back to owned by XGMAC */
> -	desc_set_rx_owner(rxdesc);
> -	writel(1, priv->base + XGMAC_DMA_RX_POLL);
> -
> -	priv->rx_currdesc = (currdesc + 1) & (RX_NUM_DESC - 1);
> -
> -	return length;
> -}
> -
> -static void xgmac_halt(struct eth_device *edev)
> -{
> -	struct xgmac_priv *priv = edev->priv;
> -	int value;
> -
> -	/* Disable TX/RX */
> -	value = readl(priv->base + XGMAC_CONTROL);
> -	value &= ~(XGMAC_CONTROL_RE | XGMAC_CONTROL_TE);
> -	writel(value, priv->base + XGMAC_CONTROL);
> -
> -	/* Disable DMA */
> -	value = readl(priv->base + XGMAC_DMA_CONTROL);
> -	value &= ~(DMA_CONTROL_SR | DMA_CONTROL_ST);
> -	writel(value, priv->base + XGMAC_DMA_CONTROL);
> -
> -	/* must set to 0, or when started up will cause issues */
> -	priv->tx_currdesc = 0;
> -	priv->rx_currdesc = 0;
> -}
> -
> -static int xgmac_get_ethaddr(struct eth_device *edev, unsigned char *addr)
> -{
> -	struct xgmac_priv *priv = edev->priv;
> -	u32 hi_addr, lo_addr;
> -
> -	/* Read the MAC address from the hardware */
> -	hi_addr = readl(priv->base + XGMAC_ADDR_HIGH(0));
> -	lo_addr = readl(priv->base + XGMAC_ADDR_LOW(0));
> -
> -	/* Extract the MAC address from the high and low words */
> -	addr[0] = lo_addr & 0xff;
> -	addr[1] = (lo_addr >> 8) & 0xff;
> -	addr[2] = (lo_addr >> 16) & 0xff;
> -	addr[3] = (lo_addr >> 24) & 0xff;
> -	addr[4] = hi_addr & 0xff;
> -	addr[5] = (hi_addr >> 8) & 0xff;
> -
> -	return 0;
> -}
> -
> -static int xgmac_set_ethaddr(struct eth_device *dev, const unsigned char *addr)
> -{
> -	struct xgmac_priv *priv = dev->priv;
> -	u32 data;
> -
> -	data = (addr[5] << 8) | addr[4];
> -	writel(data, priv->base + XGMAC_ADDR_HIGH(0));
> -	data = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
> -	writel(data, priv->base + XGMAC_ADDR_LOW(0));
> -
> -	return 0;
> -}
> -
> -static int hb_xgmac_probe(struct device_d *dev)
> -{
> -	struct resource *iores;
> -	struct eth_device *edev;
> -	struct xgmac_priv *priv;
> -	void __iomem *base;
> -
> -	iores = dev_request_mem_resource(dev, 0);
> -	if (IS_ERR(iores))
> -		return PTR_ERR(iores);
> -	base = IOMEM(iores->start);
> -
> -	/* check hardware version */
> -	if (readl(base + XGMAC_VERSION) != 0x1012)
> -		return -EINVAL;
> -
> -	priv = xzalloc(sizeof(*priv));
> -
> -	priv->dev = dev;
> -	priv->base = base;
> -
> -	priv->rxbuffer = dma_alloc_coherent(RX_BUF_SZ, DMA_ADDRESS_BROKEN);
> -	priv->rx_chain = dma_alloc_coherent(RX_NUM_DESC * sizeof(struct xgmac_dma_desc),
> -					    DMA_ADDRESS_BROKEN);
> -	priv->tx_chain = dma_alloc_coherent(TX_NUM_DESC * sizeof(struct xgmac_dma_desc),
> -					    DMA_ADDRESS_BROKEN);
> -
> -	edev = &priv->edev;
> -	edev->priv = priv;
> -
> -	edev->open = xgmac_open;
> -	edev->send = xgmac_send;
> -	edev->recv = xgmac_recv;
> -	edev->halt = xgmac_halt;
> -	edev->get_ethaddr = xgmac_get_ethaddr;
> -	edev->set_ethaddr = xgmac_set_ethaddr;
> -	edev->parent = dev;
> -
> -	eth_register(edev);
> -
> -	return 0;
> -}
> -
> -static __maybe_unused struct of_device_id xgmac_dt_ids[] = {
> -	{
> -		.compatible = "calxeda,hb-xgmac",
> -	}, {
> -		/* sentinel */
> -	}
> -};
> -
> -static struct driver_d hb_xgmac_driver = {
> -	.name  = "hb-xgmac",
> -	.probe = hb_xgmac_probe,
> -	.of_compatible = DRV_OF_COMPAT(xgmac_dt_ids),
> -};
> -device_platform_driver(hb_xgmac_driver);
> 


-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH 1/5] net: drop Calxeda Highbank xgmac driver support
  2021-08-12 12:19 [PATCH 1/5] net: drop Calxeda Highbank xgmac driver support Ahmad Fatoum
                   ` (4 preceding siblings ...)
  2021-08-12 13:03 ` [PATCH 1/5] net: drop Calxeda Highbank xgmac driver support Ahmad Fatoum
@ 2021-08-18  4:46 ` Sascha Hauer
  5 siblings, 0 replies; 7+ messages in thread
From: Sascha Hauer @ 2021-08-18  4:46 UTC (permalink / raw)
  To: Ahmad Fatoum; +Cc: barebox

On Thu, Aug 12, 2021 at 02:19:40PM +0200, Ahmad Fatoum wrote:
> Support for MACH_HIGHBANK was removed in f0f96c3322d5
> ("ARM: remove Calxeda Highbank support"). There are no device trees
> either barebox or upstream using this network controller, so remove
> the driver as well.
> 
> Fixes: f0f96c3322d5 ("ARM: remove Calxeda Highbank support")
> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> ---
>  drivers/net/Kconfig  |   4 -
>  drivers/net/Makefile |   1 -
>  drivers/net/xgmac.c  | 734 -------------------------------------------
>  3 files changed, 739 deletions(-)
>  delete mode 100644 drivers/net/xgmac.c

Applied, thanks

Sascha

-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox


^ permalink raw reply	[flat|nested] 7+ messages in thread

end of thread, other threads:[~2021-08-18  4:48 UTC | newest]

Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-08-12 12:19 [PATCH 1/5] net: drop Calxeda Highbank xgmac driver support Ahmad Fatoum
2021-08-12 12:19 ` [PATCH 2/5] net: make ARC MAC driver 32-bit only Ahmad Fatoum
2021-08-12 12:19 ` [PATCH 3/5] asm-generic: include bitio.h from io.h Ahmad Fatoum
2021-08-12 12:19 ` [PATCH 4/5] x86: define phys_to_virt and virt_to_phys Ahmad Fatoum
2021-08-12 12:19 ` [PATCH 5/5] net: e1000: split EEPROM and barebox MTD wrapper into separate files Ahmad Fatoum
2021-08-12 13:03 ` [PATCH 1/5] net: drop Calxeda Highbank xgmac driver support Ahmad Fatoum
2021-08-18  4:46 ` Sascha Hauer

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