From: Marco Felsch <m.felsch@pengutronix.de>
To: barebox@lists.infradead.org
Subject: [PATCH v2 1/7] RISC-V: cache: fix local_flush_icache_all enabling
Date: Wed, 5 Oct 2022 13:12:08 +0200 [thread overview]
Message-ID: <20221005111214.148844-1-m.felsch@pengutronix.de> (raw)
Commit fe181ffda9 ("RISC-V: support incoherent I-Cache") added the
support to handle non-coherent caches and introduced the HAS_CACHE
Kconfig symbol. The symbol must be used with CONFIG_ prefixed since this
is the final Kconfig symbol which can be used within the code.
Fixes: fe181ffda9 ("RISC-V: support incoherent I-Cache")
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
---
arch/riscv/include/asm/cache.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h
index 9a0b9326b2..6d69ed49bd 100644
--- a/arch/riscv/include/asm/cache.h
+++ b/arch/riscv/include/asm/cache.h
@@ -8,7 +8,7 @@
static inline void local_flush_icache_all(void)
{
-#ifdef HAS_CACHE
+#ifdef CONFIG_HAS_CACHE
asm volatile ("fence.i" ::: "memory");
#endif
}
--
2.30.2
next reply other threads:[~2022-10-05 11:14 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-05 11:12 Marco Felsch [this message]
2022-10-05 11:12 ` [PATCH v2 2/7] RISC-V: add riscv_vendor_id() support Marco Felsch
2022-10-05 11:12 ` [PATCH v2 3/7] RISC-V: import vendorid list from linux Marco Felsch
2022-10-05 11:12 ` [PATCH v2 4/7] RISC-V: use m/sscratch registers for barebox_riscv_pbl_flags Marco Felsch
2022-10-05 11:12 ` [PATCH v2 5/7] RISC-V: implement cache-management errata for T-Head SoCs Marco Felsch
2022-10-05 11:12 ` [PATCH v2 6/7] RISC-V: squash 64bit defconfigs into rv64i_defconfig Marco Felsch
2022-10-22 7:55 ` Antony Pavlov
2022-10-24 7:53 ` Marco Felsch
2022-10-24 8:20 ` Ahmad Fatoum
2022-10-05 11:12 ` [PATCH v2 7/7] RISC-V: add Allwinner Sun20i D1 Nezha support Marco Felsch
2022-10-07 8:30 ` [PATCH v2 1/7] RISC-V: cache: fix local_flush_icache_all enabling Sascha Hauer
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