From: Marco Felsch <m.felsch@pengutronix.de>
To: barebox@lists.infradead.org
Subject: [PATCH v2 3/7] RISC-V: import vendorid list from linux
Date: Wed, 5 Oct 2022 13:12:10 +0200 [thread overview]
Message-ID: <20221005111214.148844-3-m.felsch@pengutronix.de> (raw)
In-Reply-To: <20221005111214.148844-1-m.felsch@pengutronix.de>
Import the vendor id list from upstream linux.
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
---
arch/riscv/include/asm/vendorid_list.h | 11 +++++++++++
1 file changed, 11 insertions(+)
create mode 100644 arch/riscv/include/asm/vendorid_list.h
diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/asm/vendorid_list.h
new file mode 100644
index 0000000000..cb89af3f07
--- /dev/null
+++ b/arch/riscv/include/asm/vendorid_list.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2021 SiFive
+ */
+#ifndef ASM_VENDOR_LIST_H
+#define ASM_VENDOR_LIST_H
+
+#define SIFIVE_VENDOR_ID 0x489
+#define THEAD_VENDOR_ID 0x5b7
+
+#endif
--
2.30.2
next prev parent reply other threads:[~2022-10-05 11:14 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-05 11:12 [PATCH v2 1/7] RISC-V: cache: fix local_flush_icache_all enabling Marco Felsch
2022-10-05 11:12 ` [PATCH v2 2/7] RISC-V: add riscv_vendor_id() support Marco Felsch
2022-10-05 11:12 ` Marco Felsch [this message]
2022-10-05 11:12 ` [PATCH v2 4/7] RISC-V: use m/sscratch registers for barebox_riscv_pbl_flags Marco Felsch
2022-10-05 11:12 ` [PATCH v2 5/7] RISC-V: implement cache-management errata for T-Head SoCs Marco Felsch
2022-10-05 11:12 ` [PATCH v2 6/7] RISC-V: squash 64bit defconfigs into rv64i_defconfig Marco Felsch
2022-10-22 7:55 ` Antony Pavlov
2022-10-24 7:53 ` Marco Felsch
2022-10-24 8:20 ` Ahmad Fatoum
2022-10-05 11:12 ` [PATCH v2 7/7] RISC-V: add Allwinner Sun20i D1 Nezha support Marco Felsch
2022-10-07 8:30 ` [PATCH v2 1/7] RISC-V: cache: fix local_flush_icache_all enabling Sascha Hauer
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