[PATCH 1/3] ARM: i.MX8M: esdctl: limit i.MX8MP early memory size

[PATCH 1/3] ARM: i.MX8M: esdctl: limit i.MX8MP early memory size

[Lucas Stach]

Limit detected early memory size to 1GB on i.MX8MP, as the default DT
has a reserved memory region at 0x92400000, which will conflict with
our malloc area in some configurations. Until we can properly parse
and exclude the reserved memory regions in the PBL, just avoid getting
near that DRAM address by limiting the detected size.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 arch/arm/mach-imx/esdctl.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c
index a704250297bb..043de477a77d 100644
--- a/arch/arm/mach-imx/esdctl.c
+++ b/arch/arm/mach-imx/esdctl.c
@@ -947,7 +947,17 @@ void __noreturn imx8mn_barebox_entry(void *boarddata)
 
 void __noreturn imx8mp_barebox_entry(void *boarddata)
 {
-	imx8m_barebox_entry(boarddata, 32);
+	/*
+	 * Limit detected early memory size to 1GB on i.MX8MP, as the default
+	 * DT has a reserved memory region at 0x92400000, which will conflict
+	 * with our malloc area in some configurations. Until we can properly
+	 * parse and exclude the reserved memory regions in the PBL, just avoid
+	 * getting near that DRAM address by limiting the detected size.
+	 */
+	barebox_arm_entry(MX8M_DDR_CSD1_BASE_ADDR,
+			  min_t(resource_size_t, SZ_1G,
+				imx8m_barebox_earlymem_size(32)),
+			  boarddata);
 }
 
 void __noreturn imx8mq_barebox_entry(void *boarddata)
-- 
2.39.1

[PATCH 2/3] ARM: i.MX8M: esdctl: use common compatible to detect i.MX8M* DDRC

[Lucas Stach]

All i.MX8M* DDRC nodes are compatible to "fsl,imx8m-ddrc". As the memory
size detection works the same on all of them, there is no need to match
the more specific compatible.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 arch/arm/mach-imx/esdctl.c | 8 +-------
 1 file changed, 1 insertion(+), 7 deletions(-)

diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c
index 043de477a77d..2a2bc5205301 100644
--- a/arch/arm/mach-imx/esdctl.c
+++ b/arch/arm/mach-imx/esdctl.c
@@ -732,13 +732,7 @@ static __maybe_unused struct of_device_id imx_esdctl_dt_ids[] = {
 		.compatible = "fsl,vf610-ddrmc",
 		.data = &vf610_data
 	}, {
-		.compatible = "fsl,imx8mm-ddrc",
-		.data = &imx8mq_data
-	}, {
-		.compatible = "fsl,imx8mn-ddrc",
-		.data = &imx8mn_data
-	}, {
-		.compatible = "fsl,imx8mq-ddrc",
+		.compatible = "fsl,imx8m-ddrc",
 		.data = &imx8mq_data
 	}, {
 		.compatible = "fsl,imx7d-ddrc",
-- 
2.39.1

Re: [PATCH 2/3] ARM: i.MX8M: esdctl: use common compatible to detect i.MX8M* DDRC

[Marco Felsch]

Hi Lucas,

On 23-02-06, Lucas Stach wrote:
> All i.MX8M* DDRC nodes are compatible to "fsl,imx8m-ddrc". As the memory
> size detection works the same on all of them, there is no need to match
> the more specific compatible.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
>  arch/arm/mach-imx/esdctl.c | 8 +-------
>  1 file changed, 1 insertion(+), 7 deletions(-)
> 
> diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c
> index 043de477a77d..2a2bc5205301 100644
> --- a/arch/arm/mach-imx/esdctl.c
> +++ b/arch/arm/mach-imx/esdctl.c
> @@ -732,13 +732,7 @@ static __maybe_unused struct of_device_id imx_esdctl_dt_ids[] = {
>  		.compatible = "fsl,vf610-ddrmc",
>  		.data = &vf610_data
>  	}, {
> -		.compatible = "fsl,imx8mm-ddrc",
> -		.data = &imx8mq_data
> -	}, {
> -		.compatible = "fsl,imx8mn-ddrc",
> -		.data = &imx8mn_data

The i.MX8M Nano uses a 16bit bus width according the data. I don't have
the datasheet right now to check this. But this commit will change it to
32 bit, is this allowed?

Regards,
  Marco

> -	}, {
> -		.compatible = "fsl,imx8mq-ddrc",
> +		.compatible = "fsl,imx8m-ddrc",
>  		.data = &imx8mq_data
>  	}, {
>  		.compatible = "fsl,imx7d-ddrc",
> -- 
> 2.39.1
> 
> 
> 

Re: [PATCH 2/3] ARM: i.MX8M: esdctl: use common compatible to detect i.MX8M* DDRC

[Lucas Stach]

Am Dienstag, dem 07.02.2023 um 11:24 +0100 schrieb Marco Felsch:
> Hi Lucas,
> 
> On 23-02-06, Lucas Stach wrote:
> > All i.MX8M* DDRC nodes are compatible to "fsl,imx8m-ddrc". As the memory
> > size detection works the same on all of them, there is no need to match
> > the more specific compatible.
> > 
> > Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> > ---
> >  arch/arm/mach-imx/esdctl.c | 8 +-------
> >  1 file changed, 1 insertion(+), 7 deletions(-)
> > 
> > diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c
> > index 043de477a77d..2a2bc5205301 100644
> > --- a/arch/arm/mach-imx/esdctl.c
> > +++ b/arch/arm/mach-imx/esdctl.c
> > @@ -732,13 +732,7 @@ static __maybe_unused struct of_device_id imx_esdctl_dt_ids[] = {
> >  		.compatible = "fsl,vf610-ddrmc",
> >  		.data = &vf610_data
> >  	}, {
> > -		.compatible = "fsl,imx8mm-ddrc",
> > -		.data = &imx8mq_data
> > -	}, {
> > -		.compatible = "fsl,imx8mn-ddrc",
> > -		.data = &imx8mn_data
> 
> The i.MX8M Nano uses a 16bit bus width according the data. I don't have
> the datasheet right now to check this. But this commit will change it to
> 32 bit, is this allowed?

Argh, thanks for catching that! This change was a bit overzealous.

Regards,
Lucas
> 
> Regards,
>   Marco
> 
> > -	}, {
> > -		.compatible = "fsl,imx8mq-ddrc",
> > +		.compatible = "fsl,imx8m-ddrc",
> >  		.data = &imx8mq_data
> >  	}, {
> >  		.compatible = "fsl,imx7d-ddrc",
> > -- 
> > 2.39.1
> > 
> > 
> > 

[PATCH 3/3] ARM: dts: i.MX8MP: add DDRC compatibles

[Lucas Stach]

The upstream DT currently only provides the Synopsis core compatible
for the DDRC node. Extend this with more machine specific compatibles
to allow our memory size detection to work.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 arch/arm/dts/imx8mp.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi
index 5da79f13d339..778e84318ce7 100644
--- a/arch/arm/dts/imx8mp.dtsi
+++ b/arch/arm/dts/imx8mp.dtsi
@@ -10,6 +10,10 @@
 	};
 };
 
+&edacmc {
+	compatible = "fsl,imx8mp-ddrc", "fsl,imx8m-ddrc", "snps,ddrc-3.80a";
+};
+
 feat: &ocotp {
 	#feature-cells = <1>;
 	barebox,feature-controller;
-- 
2.39.1

Re: [PATCH 1/3] ARM: i.MX8M: esdctl: limit i.MX8MP early memory size

[Sascha Hauer]

On Mon, Feb 06, 2023 at 10:00:02PM +0100, Lucas Stach wrote:
> Limit detected early memory size to 1GB on i.MX8MP, as the default DT
> has a reserved memory region at 0x92400000, which will conflict with
> our malloc area in some configurations. Until we can properly parse
> and exclude the reserved memory regions in the PBL, just avoid getting
> near that DRAM address by limiting the detected size.

The memory region reserved at 0x92400000 belongs to an audio processing
DSP. This is unused for sure in barebox, so do we really need to handle
this case here?

Besides, who had that glorious of hardcoding that RAM area in the dtsi
file?? Is this address dictated by the hardware? That would mean the DSP
is not usable on machines with only 1GiB of RAM. If it's not dictated
by the hardware, why is it in the dtsi file?

This smells fishy.

Sascha

> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
>  arch/arm/mach-imx/esdctl.c | 12 +++++++++++-
>  1 file changed, 11 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c
> index a704250297bb..043de477a77d 100644
> --- a/arch/arm/mach-imx/esdctl.c
> +++ b/arch/arm/mach-imx/esdctl.c
> @@ -947,7 +947,17 @@ void __noreturn imx8mn_barebox_entry(void *boarddata)
>  
>  void __noreturn imx8mp_barebox_entry(void *boarddata)
>  {
> -	imx8m_barebox_entry(boarddata, 32);
> +	/*
> +	 * Limit detected early memory size to 1GB on i.MX8MP, as the default
> +	 * DT has a reserved memory region at 0x92400000, which will conflict
> +	 * with our malloc area in some configurations. Until we can properly
> +	 * parse and exclude the reserved memory regions in the PBL, just avoid
> +	 * getting near that DRAM address by limiting the detected size.
> +	 */
> +	barebox_arm_entry(MX8M_DDR_CSD1_BASE_ADDR,
> +			  min_t(resource_size_t, SZ_1G,
> +				imx8m_barebox_earlymem_size(32)),
> +			  boarddata);
>  }
>  
>  void __noreturn imx8mq_barebox_entry(void *boarddata)
> -- 
> 2.39.1
> 
> 
> 

-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
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Re: [PATCH 1/3] ARM: i.MX8M: esdctl: limit i.MX8MP early memory size

[Sascha Hauer]

On Wed, Feb 08, 2023 at 09:20:15AM +0100, Sascha Hauer wrote:
> On Mon, Feb 06, 2023 at 10:00:02PM +0100, Lucas Stach wrote:
> > Limit detected early memory size to 1GB on i.MX8MP, as the default DT
> > has a reserved memory region at 0x92400000, which will conflict with
> > our malloc area in some configurations. Until we can properly parse
> > and exclude the reserved memory regions in the PBL, just avoid getting
> > near that DRAM address by limiting the detected size.
> 
> The memory region reserved at 0x92400000 belongs to an audio processing
> DSP. This is unused for sure in barebox, so do we really need to handle
> this case here?
> 
> Besides, who had that glorious of hardcoding that RAM area in the dtsi
                                ^idea

> file?? Is this address dictated by the hardware? That would mean the DSP
> is not usable on machines with only 1GiB of RAM. If it's not dictated
> by the hardware, why is it in the dtsi file?
> 
> This smells fishy.
> 
> Sascha
> 
> > 
> > Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> > ---
> >  arch/arm/mach-imx/esdctl.c | 12 +++++++++++-
> >  1 file changed, 11 insertions(+), 1 deletion(-)
> > 
> > diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c
> > index a704250297bb..043de477a77d 100644
> > --- a/arch/arm/mach-imx/esdctl.c
> > +++ b/arch/arm/mach-imx/esdctl.c
> > @@ -947,7 +947,17 @@ void __noreturn imx8mn_barebox_entry(void *boarddata)
> >  
> >  void __noreturn imx8mp_barebox_entry(void *boarddata)
> >  {
> > -	imx8m_barebox_entry(boarddata, 32);
> > +	/*
> > +	 * Limit detected early memory size to 1GB on i.MX8MP, as the default
> > +	 * DT has a reserved memory region at 0x92400000, which will conflict
> > +	 * with our malloc area in some configurations. Until we can properly
> > +	 * parse and exclude the reserved memory regions in the PBL, just avoid
> > +	 * getting near that DRAM address by limiting the detected size.
> > +	 */
> > +	barebox_arm_entry(MX8M_DDR_CSD1_BASE_ADDR,
> > +			  min_t(resource_size_t, SZ_1G,
> > +				imx8m_barebox_earlymem_size(32)),
> > +			  boarddata);
> >  }
> >  
> >  void __noreturn imx8mq_barebox_entry(void *boarddata)
> > -- 
> > 2.39.1
> > 
> > 
> > 
> 
> -- 
> Pengutronix e.K.                           |                             |
> Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
> 31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
> Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |
> 

-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |