[PATCH 2/6] mtd: nand: orion: set Hamming ECC algorithm in ->attach_chip()

[Michael Grzeschik <grzeschik@puzzle.ch>]

The driver selects software Hamming ECC before nand_scan(), but
rawnand_dt_init() unconditionally overwrites chip->ecc.algo with the
device tree setting. None of the Kirkwood device trees has an ECC
property, so the algorithm ends up as NAND_ECC_ALGO_UNKNOWN and probing
fails:

  WARNING: at drivers/mtd/nand/raw/nand_base.c:5783/nand_set_ecc_soft_ops()!
  WARNING: Unsupported ECC algorithm!

leaving all boards with an orion NAND controller without NAND.

Do the same as the Linux orion_nand driver: keep the software engine as
default before scanning, and pick the Hamming algorithm in
->attach_chip(), which runs after the device tree has been parsed, if
neither the device tree nor anything else chose one.

Assisted-by: Claude:claude-opus-5-5
Signed-off-by: Michael Grzeschik <grzeschik@puzzle.ch>
---
 drivers/mtd/nand/raw/nand_orion.c | 20 +++++++++++++++++++-
 1 file changed, 19 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/raw/nand_orion.c b/drivers/mtd/nand/raw/nand_orion.c
index c7fa4a08e9..68797b9b38 100644
--- a/drivers/mtd/nand/raw/nand_orion.c
+++ b/drivers/mtd/nand/raw/nand_orion.c
@@ -73,6 +73,19 @@ static void orion_nand_read_buf(struct nand_chip *chip, uint8_t *buf, int len)
 		buf[i++] = readb(io_base);
 }
 
+static int orion_nand_attach_chip(struct nand_chip *chip)
+{
+	if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT &&
+	    chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN)
+		chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
+
+	return 0;
+}
+
+static const struct nand_controller_ops orion_nand_controller_ops = {
+	.attach_chip = orion_nand_attach_chip,
+};
+
 static int orion_nand_probe(struct device *dev)
 {
 	struct resource *iores;
@@ -117,8 +130,13 @@ static int orion_nand_probe(struct device *dev)
 	chip->legacy.IO_ADDR_R = chip->legacy.IO_ADDR_W = io_base;
 	chip->legacy.cmd_ctrl = orion_nand_cmd_ctrl;
 	chip->legacy.read_buf = orion_nand_read_buf;
+	/*
+	 * The default ECC engine is software. The algorithm is set in
+	 * ->attach_chip(), after rawnand_dt_init() has overwritten it with the
+	 * (usually absent) device tree setting.
+	 */
 	chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
-	chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
+	chip->legacy.dummy_controller.ops = &orion_nand_controller_ops;
 
 	WARN(width > 16, "%d bit bus width out of range", width);
 	if (width == 16)

-- 
2.53.0