[PATCH 1/2] usb: dwc2: core: add no-csftrst-wait DT property

[PATCH 1/2] usb: dwc2: core: add no-csftrst-wait DT property

[chalianis1]

From: Chali Anis <chalianis1@gmail.com>

Some platforms (e.g. RPi4/bcm2711) do not deassert GRSTCTL_CSFTRST within
the expected window but continue to operate correctly, causing probe to
fail with ETIMEDOUT.

Per the datasheet, GRSTCTL_CSFTRST is self-clearing but requires at least
3 PHY clocks after reset before any PHY domain access. Add a 1us delay to
satisfy this requirement.

Additionally introduce the 'no-csftrst-wait' devicetree property to skip
polling for the bit to clear on platforms where the reset completes but the
status bit is unreliable.

Signed-off-by: Chali Anis <chalianis1@gmail.com>
---
 drivers/usb/dwc2/core.c | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/drivers/usb/dwc2/core.c b/drivers/usb/dwc2/core.c
index 60cc690fdbc0..9a2356ee074e 100644
--- a/drivers/usb/dwc2/core.c
+++ b/drivers/usb/dwc2/core.c
@@ -770,6 +770,7 @@ bool dwc2_iddig_filter_enabled(struct dwc2 *dwc2)
  */
 int dwc2_core_reset(struct dwc2 *dwc2)
 {
+	struct device_node *np = dwc2->dev->of_node;
 	bool wait_for_host_mode = false;
 	uint32_t greset;
 	int ret;
@@ -809,11 +810,16 @@ int dwc2_core_reset(struct dwc2 *dwc2)
 	greset |= GRSTCTL_CSFTRST;
 	dwc2_writel(dwc2, greset, GRSTCTL);
 
-	ret = dwc2_wait_bit_clear(dwc2, GRSTCTL, GRSTCTL_CSFTRST, 10000);
-	if (ret) {
-		dwc2_warn(dwc2, "%s: Timeout! Waiting for Core Soft Reset\n",
+	/* Wait for at least 3 PHY Clocks */
+	udelay(1);
+
+	if (!of_property_read_bool(np, "no-csftrst-wait")) {
+		ret = dwc2_wait_bit_clear(dwc2, GRSTCTL, GRSTCTL_CSFTRST, 10000);
+		if (ret) {
+			dwc2_warn(dwc2, "%s: Timeout! Waiting for Core Soft Reset\n",
 				__func__);
-		return ret;
+			return ret;
+		}
 	}
 
 	if (wait_for_host_mode)

[PATCH 2/2] ARM: dts: bcm2711-rpi: enable USB and skip soft reset wait on RPi4

[chalianis1]

From: Chali Anis <chalianis1@gmail.com>

The dwc2 controller on bcm2711 does not reliably deassert GRSTCTL_CSFTRST
within the expected window, causing probe to fail with ETIMEDOUT. Enable
the USB node and set no-csftrst-wait to bypass the reset bit polling.

Signed-off-by: Chali Anis <chalianis1@gmail.com>
---
 arch/arm/dts/bcm2711-rpi.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/dts/bcm2711-rpi.dtsi b/arch/arm/dts/bcm2711-rpi.dtsi
index 2722133a4afc..892d6a7aecc8 100644
--- a/arch/arm/dts/bcm2711-rpi.dtsi
+++ b/arch/arm/dts/bcm2711-rpi.dtsi
@@ -19,3 +19,7 @@ &uart1 {
 &power {
 	barebox,allow-dummy;
 };
+
+&usb {
+	no-csftrst-wait;
+};

Re: [PATCH 1/2] usb: dwc2: core: add no-csftrst-wait DT property

[Ahmad Fatoum]

Hello Anis,

On 3/31/26 5:17 AM, chalianis1@gmail.com wrote:
> From: Chali Anis <chalianis1@gmail.com>
> 
> Some platforms (e.g. RPi4/bcm2711) do not deassert GRSTCTL_CSFTRST within
> the expected window but continue to operate correctly, causing probe to
> fail with ETIMEDOUT.
> 
> Per the datasheet, GRSTCTL_CSFTRST is self-clearing but requires at least
> 3 PHY clocks after reset before any PHY domain access. Add a 1us delay to
> satisfy this requirement.
> 
> Additionally introduce the 'no-csftrst-wait' devicetree property to skip
> polling for the bit to clear on platforms where the reset completes but the
> status bit is unreliable.

I still wonder why there are no workarounds for this particular issue in
Linux or U-Boot. We seem to do something different when we run into this
reliably, but others don't?

I originally thought, it may be related to the version of the IP,
because both Linux and U-Boot have special handling for >= 4.20, but I
checked on my Rpi4 and DWC2 has v2.80 there (Synopsis ID 4f54280a)

> -	ret = dwc2_wait_bit_clear(dwc2, GRSTCTL, GRSTCTL_CSFTRST, 10000);
> -	if (ret) {
> -		dwc2_warn(dwc2, "%s: Timeout! Waiting for Core Soft Reset\n",
> +	/* Wait for at least 3 PHY Clocks */
> +	udelay(1);
> +
> +	if (!of_property_read_bool(np, "no-csftrst-wait")) {

barebox-specific Device Tree properties should be documented in
Documentation/devicetree/bindings/.

Alternatively, you can check of_machine_is_compatible("brcm,bcm2711")

Cheers,
Ahmad

> +		ret = dwc2_wait_bit_clear(dwc2, GRSTCTL, GRSTCTL_CSFTRST, 10000);
> +		if (ret) {
> +			dwc2_warn(dwc2, "%s: Timeout! Waiting for Core Soft Reset\n",
>  				__func__);
> -		return ret;
> +			return ret;
> +		}
>  	}
>  
>  	if (wait_for_host_mode)
> 
> 

-- 
Pengutronix e.K.                  |                             |
Steuerwalder Str. 21              | http://www.pengutronix.de/  |
31137 Hildesheim, Germany         | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686  | Fax:   +49-5121-206917-5555 |

Re: [PATCH 1/2] usb: dwc2: core: add no-csftrst-wait DT property

[anis chali]

Hello Ahmad,
Le lun. 13 avr. 2026 à 09:50, Ahmad Fatoum <a.fatoum@pengutronix.de> a écrit :
>
> Hello Anis,
>
> On 3/31/26 5:17 AM, chalianis1@gmail.com wrote:
> > From: Chali Anis <chalianis1@gmail.com>
> >
> > Some platforms (e.g. RPi4/bcm2711) do not deassert GRSTCTL_CSFTRST within
> > the expected window but continue to operate correctly, causing probe to
> > fail with ETIMEDOUT.
> >
> > Per the datasheet, GRSTCTL_CSFTRST is self-clearing but requires at least
> > 3 PHY clocks after reset before any PHY domain access. Add a 1us delay to
> > satisfy this requirement.
> >
> > Additionally introduce the 'no-csftrst-wait' devicetree property to skip
> > polling for the bit to clear on platforms where the reset completes but the
> > status bit is unreliable.
>
> I still wonder why there are no workarounds for this particular issue in
> Linux or U-Boot. We seem to do something different when we run into this
> reliably, but others don't?

I checked the initialization sequence but I didn't
find anything interesting.

> I originally thought, it may be related to the version of the IP,
> because both Linux and U-Boot have special handling for >= 4.20, but I
> checked on my Rpi4 and DWC2 has v2.80 there (Synopsis ID 4f54280a)

I implemented the u-boot logic but I had the same code with version check
and I ended by removing it since it works for now without handling the versions.

> > -     ret = dwc2_wait_bit_clear(dwc2, GRSTCTL, GRSTCTL_CSFTRST, 10000);
> > -     if (ret) {
> > -             dwc2_warn(dwc2, "%s: Timeout! Waiting for Core Soft Reset\n",
> > +     /* Wait for at least 3 PHY Clocks */
> > +     udelay(1);
> > +
> > +     if (!of_property_read_bool(np, "no-csftrst-wait")) {
>
> barebox-specific Device Tree properties should be documented in
> Documentation/devicetree/bindings/.
Okay, ack.

> Alternatively, you can check of_machine_is_compatible("brcm,bcm2711")
I choosed to add something in the device tree to not hard code a
specific machine in
dwc2 in that case we let the machine dts or users facing the same
issue to add the dts
property without even submitting patch, but if you prefer manage this
with checking the
machine compatible I can make the change???

> Cheers,
> Ahmad
>
> > +             ret = dwc2_wait_bit_clear(dwc2, GRSTCTL, GRSTCTL_CSFTRST, 10000);
> > +             if (ret) {
> > +                     dwc2_warn(dwc2, "%s: Timeout! Waiting for Core Soft Reset\n",
> >                               __func__);
> > -             return ret;
> > +                     return ret;
> > +             }
> >       }
> >
> >       if (wait_for_host_mode)
> >
> >
>
> --
> Pengutronix e.K.                  |                             |
> Steuerwalder Str. 21              | http://www.pengutronix.de/  |
> 31137 Hildesheim, Germany         | Phone: +49-5121-206917-0    |
> Amtsgericht Hildesheim, HRA 2686  | Fax:   +49-5121-206917-5555 |
>

Thank you for support.

Anis

Re: [PATCH 1/2] usb: dwc2: core: add no-csftrst-wait DT property

[Ahmad Fatoum]

Hi,

On 4/13/26 19:41, anis chali wrote:
> Hello Ahmad,
> Le lun. 13 avr. 2026 à 09:50, Ahmad Fatoum <a.fatoum@pengutronix.de> a écrit :
>>
>> Hello Anis,
>>
>> On 3/31/26 5:17 AM, chalianis1@gmail.com wrote:
>>> From: Chali Anis <chalianis1@gmail.com>
>>>
>>> Some platforms (e.g. RPi4/bcm2711) do not deassert GRSTCTL_CSFTRST within
>>> the expected window but continue to operate correctly, causing probe to
>>> fail with ETIMEDOUT.
>>>
>>> Per the datasheet, GRSTCTL_CSFTRST is self-clearing but requires at least
>>> 3 PHY clocks after reset before any PHY domain access. Add a 1us delay to
>>> satisfy this requirement.
>>>
>>> Additionally introduce the 'no-csftrst-wait' devicetree property to skip
>>> polling for the bit to clear on platforms where the reset completes but the
>>> status bit is unreliable.
>>
>> I still wonder why there are no workarounds for this particular issue in
>> Linux or U-Boot. We seem to do something different when we run into this
>> reliably, but others don't?
> 
> I checked the initialization sequence but I didn't
> find anything interesting.
> 
>> I originally thought, it may be related to the version of the IP,
>> because both Linux and U-Boot have special handling for >= 4.20, but I
>> checked on my Rpi4 and DWC2 has v2.80 there (Synopsis ID 4f54280a)
> 
> I implemented the u-boot logic but I had the same code with version check
> and I ended by removing it since it works for now without handling the versions.

ok, let's go with this workaround then.

>>> +     if (!of_property_read_bool(np, "no-csftrst-wait")) {
>>
>> barebox-specific Device Tree properties should be documented in
>> Documentation/devicetree/bindings/.
> Okay, ack.
> 
>> Alternatively, you can check of_machine_is_compatible("brcm,bcm2711")
> I choosed to add something in the device tree to not hard code a
> specific machine in
> dwc2 in that case we let the machine dts or users facing the same
> issue to add the dts
> property without even submitting patch, but if you prefer manage this
> with checking the
> machine compatible I can make the change???

Either is fine by me.

Cheers,
Ahmad

> 
>> Cheers,
>> Ahmad
>>
>>> +             ret = dwc2_wait_bit_clear(dwc2, GRSTCTL, GRSTCTL_CSFTRST, 10000);
>>> +             if (ret) {
>>> +                     dwc2_warn(dwc2, "%s: Timeout! Waiting for Core Soft Reset\n",
>>>                               __func__);
>>> -             return ret;
>>> +                     return ret;
>>> +             }
>>>       }
>>>
>>>       if (wait_for_host_mode)
>>>
>>>
>>
>> --
>> Pengutronix e.K.                  |                             |
>> Steuerwalder Str. 21              | http://www.pengutronix.de/  |
>> 31137 Hildesheim, Germany         | Phone: +49-5121-206917-0    |
>> Amtsgericht Hildesheim, HRA 2686  | Fax:   +49-5121-206917-5555 |
>>
> 
> Thank you for support.
> 
> Anis
> 


-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

Re: [PATCH 1/2] usb: dwc2: core: add no-csftrst-wait DT property

[Sascha Hauer]

Hi,

On Mon, Apr 13, 2026 at 01:41:28PM -0400, anis chali wrote:
> and I ended by removing it since it works for now without handling the versions.
> 
> > > -     ret = dwc2_wait_bit_clear(dwc2, GRSTCTL, GRSTCTL_CSFTRST, 10000);
> > > -     if (ret) {
> > > -             dwc2_warn(dwc2, "%s: Timeout! Waiting for Core Soft Reset\n",
> > > +     /* Wait for at least 3 PHY Clocks */
> > > +     udelay(1);
> > > +
> > > +     if (!of_property_read_bool(np, "no-csftrst-wait")) {
> >
> > barebox-specific Device Tree properties should be documented in
> > Documentation/devicetree/bindings/.
> Okay, ack.
> 
> > Alternatively, you can check of_machine_is_compatible("brcm,bcm2711")
> I choosed to add something in the device tree to not hard code a
> specific machine in
> dwc2 in that case we let the machine dts or users facing the same
> issue to add the dts
> property without even submitting patch, but if you prefer manage this
> with checking the
> machine compatible I can make the change???

The downside with the dts approach is that we never realize that it's
needed when that person doesn't submit a patch.

I prefer a machine compatible check at least until a pattern evolved
where this is needed.

Sascha

-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |