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From: Antony Pavlov <antonynpavlov@gmail.com>
To: barebox@lists.infradead.org
Cc: Ahmad Fatoum <a.fatoum@pengutronix.de>
Subject: [PATCH v3 01/10] clocksource: timer-riscv: select CSR from device tree
Date: Tue, 25 May 2021 10:19:43 +0300	[thread overview]
Message-ID: <20210525071952.18045-2-antonynpavlov@gmail.com> (raw)
In-Reply-To: <20210525071952.18045-1-antonynpavlov@gmail.com>

barebox timer-riscv driver supports one of user counters:

  * 'cycle', counter for RDCYCLE instruction (CSR 0xc00);
  * 'time', timer for RDTIME instruction (CSR 0xc01).

At the moment in M-mode timer-riscv uses the 'cycle' counter,
and in S-mode timer-riscv uses the 'time' timer.

Alas picorv32 CPU core supports only the 'cycle' counter.
VexRiscV CPU core in M-mode supports only the 'time' timer.

This patch makes it possible to use the 'time' timer
for VexRiscV CPU in M-mode.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
 arch/riscv/dts/erizo.dtsi         |  2 ++
 drivers/clocksource/timer-riscv.c | 24 ++++++++++++------------
 2 files changed, 14 insertions(+), 12 deletions(-)

diff --git a/arch/riscv/dts/erizo.dtsi b/arch/riscv/dts/erizo.dtsi
index 228711bd69..4eb92ae6f1 100644
--- a/arch/riscv/dts/erizo.dtsi
+++ b/arch/riscv/dts/erizo.dtsi
@@ -22,6 +22,8 @@
 
 		timebase-frequency = <24000000>;
 
+		barebox,csr-cycle;
+
 		cpu@0 {
 			device_type = "cpu";
 			compatible = "cliffordwolf,picorv32", "riscv";
diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
index cbbe18d9a6..305d1ecea0 100644
--- a/drivers/clocksource/timer-riscv.c
+++ b/drivers/clocksource/timer-riscv.c
@@ -12,9 +12,8 @@
 #include <clock.h>
 #include <asm/timer.h>
 #include <asm/csr.h>
-#include <asm/system.h>
 
-static u64 notrace riscv_timer_get_count_sbi(void)
+static u64 notrace riscv_timer_get_count_time(void)
 {
 	__maybe_unused u32 hi, lo;
 
@@ -29,7 +28,7 @@ static u64 notrace riscv_timer_get_count_sbi(void)
 	return ((u64)hi << 32) | lo;
 }
 
-static u64 notrace riscv_timer_get_count_rdcycle(void)
+static u64 notrace riscv_timer_get_count_cycle(void)
 {
 	__maybe_unused u32 hi, lo;
 
@@ -44,24 +43,25 @@ static u64 notrace riscv_timer_get_count_rdcycle(void)
 	return ((u64)hi << 32) | lo;
 }
 
-static u64 notrace riscv_timer_get_count(void)
-{
-	if (riscv_mode() == RISCV_S_MODE)
-		return riscv_timer_get_count_sbi();
-	else
-		return riscv_timer_get_count_rdcycle();
-}
-
 static struct clocksource riscv_clocksource = {
-	.read		= riscv_timer_get_count,
 	.mask		= CLOCKSOURCE_MASK(64),
 	.priority	= 100,
 };
 
 static int riscv_timer_init(struct device_d* dev)
 {
+	struct device_node *cpu;
+
 	dev_info(dev, "running at %lu Hz\n", riscv_timebase);
 
+	cpu = of_find_node_by_path("/cpus");
+
+	if (of_property_read_bool(cpu, "barebox,csr-cycle")) {
+		riscv_clocksource.read = riscv_timer_get_count_cycle;
+	} else {
+		riscv_clocksource.read = riscv_timer_get_count_time;
+	}
+
 	riscv_clocksource.mult = clocksource_hz2mult(riscv_timebase, riscv_clocksource.shift);
 
 	return init_clock(&riscv_clocksource);
-- 
2.31.1


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  reply	other threads:[~2021-05-25  7:21 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-25  7:19 [PATCH v3 00/10] RISC-V: add LiteX SoC support; resurrect nmon Antony Pavlov
2021-05-25  7:19 ` Antony Pavlov [this message]
2021-05-25 12:54   ` [PATCH v3 01/10] clocksource: timer-riscv: select CSR from device tree Ahmad Fatoum
2021-05-25  7:19 ` [PATCH v3 02/10] RISC-V: make it possible to run nmon from PBL C code Antony Pavlov
2021-05-25  7:19 ` [PATCH v3 03/10] RISC-V: boards: erizo: make it possible to use nmon Antony Pavlov
2021-05-25  7:19 ` [PATCH v3 04/10] serial: add litex UART driver Antony Pavlov
2021-05-25  7:19 ` [PATCH v3 05/10] litex serial: add setbrg callback Antony Pavlov
2021-05-25  7:36   ` Antony Pavlov
2021-05-25 12:48     ` Ahmad Fatoum
2021-05-25  7:19 ` [PATCH v3 06/10] gpio: add driver for 74xx-ICs with MMIO access Antony Pavlov
2021-05-25  7:19 ` [PATCH v3 07/10] spi: add litex spiflash driver Antony Pavlov
2021-05-25  7:19 ` [PATCH v3 08/10] net: add LiteEth driver Antony Pavlov
2021-05-25  7:19 ` [PATCH v3 09/10] RISC-V: add LiteX SoC and linux-on-litex-vexriscv support Antony Pavlov
2021-05-25  7:47   ` Jan Lübbe
2021-05-25  8:52     ` Antony Pavlov
2021-05-25  7:19 ` [PATCH v3 10/10] RISC-V: add litex_linux_defconfig Antony Pavlov
2021-08-11  8:52 ` [PATCH v3 00/10] RISC-V: add LiteX SoC support; resurrect nmon Ahmad Fatoum
2021-08-17 10:16   ` Antony Pavlov
2021-08-17 10:20     ` Ahmad Fatoum

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