[PATCH 1/8] clk: stm32f4: allow building under COMPILE_TEST and fix the build

[PATCH 1/8] clk: stm32f4: allow building under COMPILE_TEST and fix the build

[Ahmad Fatoum]

From: Ahmad Fatoum <a.fatoum@barebox.org>

No in-tree defconfig combines ARCH_STM32 with this driver, so it has
never been compiled and doesn't build:

  clk-stm32f4.c:1665:20: error: 'struct clk_mux' has no member named 'width'

barebox' struct clk_mux carries a mask like Linux', so assign it
verbatim as upstream does; the tables already hold unshifted masks.

The symbol can't be enabled at all either: its prompt is gated on
COMPILE_TEST and it has no default, and the only in-tree selector of
ARCH_STM32 is ARCH_STM32MP, which uses clk-stm32mp1.c instead.

As I still hope to finish upstreaming my STM32F support one day, let's
just ensure the driver compile tests for now.

Fixes: 27923adcd1b7 ("clk: add clock driver for stm32f4 and stm32f7")
Signed-off-by: Ahmad Fatoum <a.fatoum@barebox.org>
---
 drivers/clk/Kconfig       | 4 ++--
 drivers/clk/clk-stm32f4.c | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index fe7056f8971b..e11361c43895 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -43,8 +43,8 @@ config CLK_SOCFPGA
 if COMMON_CLK
 
 config COMMON_CLK_STM32F
-	bool "STM32F4 and STM32F7 clock driver" if COMPILE_TEST
-	depends on ARCH_STM32
+	bool "STM32F4 and STM32F7 clock driver"
+	depends on ARCH_STM32 || COMPILE_TEST
 	help
 	  Support for stm32f4 and stm32f7 SoC families clocks
 
diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c
index 343ee0e6e9b5..764603cc473a 100644
--- a/drivers/clk/clk-stm32f4.c
+++ b/drivers/clk/clk-stm32f4.c
@@ -1659,7 +1659,7 @@ static struct clk_hw *stm32_register_aux_clk(const char *name,
 
 		mux->reg = base + offset_mux;
 		mux->shift = shift;
-		mux->width = hweight8(mask);
+		mux->mask = mask;
 		mux->flags = 0;
 		mux_hw = &mux->hw;
 		mux_ops = &clk_mux_ops;
-- 
2.47.3

[PATCH 2/8] clk: at91: sam9x60-pll: allow building under COMPILE_TEST and fix the build

[Ahmad Fatoum]

From: Ahmad Fatoum <a.fatoum@barebox.org>

HAVE_AT91_SAM9X60_PLL is only selected by SOC_SAM9X60 and SOC_SAMA7G5,
which no board selects, so the driver has never been compiled and
doesn't build:

  clk-sam9x60-pll.c:78:17: error: implicit declaration of function 'DIV_ROUND_CLOSEST_ULL'
  clk-sam9x60-pll.c:201:16: error: implicit declaration of function 'mult_frac'
  clk-sam9x60-pll.c:442:28: error: implicit declaration of function 'abs'
  clk-sam9x60-pll.c:483:20: error: implicit declaration of function 'DIV_ROUND_CLOSEST'

Include the missing headers and give the symbol a COMPILE_TEST prompt.

Fixes: 18afc26f9caa ("clk: at91: port Linux v5.6 SAM9X60 (new ARM926EJ-S) clock support")
Signed-off-by: Ahmad Fatoum <a.fatoum@barebox.org>
---
 arch/arm/mach-at91/Kconfig         | 2 +-
 drivers/clk/at91/clk-sam9x60-pll.c | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index db79ad2d267a..df20943254a9 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -44,7 +44,7 @@ config HAVE_AT91_I2S_MUX_CLK
 	bool
 
 config HAVE_AT91_SAM9X60_PLL
-	bool
+	bool "SAM9X60 PLL support" if COMPILE_TEST
 
 config HAVE_AT91_SDRAMC
 	bool
diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c
index c4f16061288f..4a1843e06c00 100644
--- a/drivers/clk/at91/clk-sam9x60-pll.c
+++ b/drivers/clk/at91/clk-sam9x60-pll.c
@@ -9,6 +9,8 @@
 #include <linux/clk-provider.h>
 #include <linux/clkdev.h>
 #include <linux/clk/at91_pmc.h>
+#include <linux/math.h>
+#include <linux/math64.h>
 #include <of.h>
 #include <mfd/syscon.h>
 #include <linux/regmap.h>
-- 
2.47.3

[PATCH 3/8] clk: composite: return ERR_PTR on registration failure

[Ahmad Fatoum]

From: Ahmad Fatoum <a.fatoum@barebox.org>

clk_register_composite() returns 0 instead of ERR_PTR(ret) on error, so
callers checking IS_ERR() see a failed registration as success.

Fixes: 9eb9f0004347 ("CLK: Add support for composite clock from Linux kernel")
Reported-by: Claude:opus-4.6
Signed-off-by: Ahmad Fatoum <a.fatoum@barebox.org>
---
 drivers/clk/clk-composite.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
index a23e828f587f..4cf3a91a63b4 100644
--- a/drivers/clk/clk-composite.c
+++ b/drivers/clk/clk-composite.c
@@ -239,7 +239,7 @@ struct clk *clk_register_composite(const char *name,
 
 err:
 	kfree(composite);
-	return 0;
+	return ERR_PTR(ret);
 }
 
 struct clk_hw *clk_hw_register_composite(struct device *dev,
-- 
2.47.3

[PATCH 4/8] clk: fixed-factor: use 64-bit arithmetic in recalc_rate

[Ahmad Fatoum]

From: Ahmad Fatoum <a.fatoum@barebox.org>

(parent_rate / div) * mult loses precision in the intermediate division
and parent_rate * mult can exceed 32 bits. Use u64 multiplication and
do_div like Linux' clk_factor_recalc_rate() does since commit
bab53301c38 ("clk: fixed-factor: round_rate should use do_div").

Fixes: f2e2e596a221 ("clk: initial common clk support")
Reported-by: Claude:opus-4.6
Signed-off-by: Ahmad Fatoum <a.fatoum@barebox.org>
---
 drivers/clk/clk-fixed-factor.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c
index d2c808d40c63..a163c3de28b6 100644
--- a/drivers/clk/clk-fixed-factor.c
+++ b/drivers/clk/clk-fixed-factor.c
@@ -9,13 +9,17 @@
 #include <malloc.h>
 #include <linux/clk.h>
 #include <linux/err.h>
+#include <linux/math64.h>
 
 static unsigned long clk_fixed_factor_recalc_rate(struct clk_hw *hw,
 		unsigned long parent_rate)
 {
 	struct clk_fixed_factor *f = to_clk_fixed_factor(hw);
+	unsigned long long int rate;
 
-	return (parent_rate / f->div) * f->mult;
+	rate = (unsigned long long int)parent_rate * f->mult;
+	do_div(rate, f->div);
+	return (unsigned long)rate;
 }
 
 static long clk_factor_round_rate(struct clk_hw *hw, unsigned long rate,
-- 
2.47.3

[PATCH 5/8] clk: imx: pllv3: use 64-bit arithmetic in fractional PLL recalc_rate

[Ahmad Fatoum]

From: Ahmad Fatoum <a.fatoum@barebox.org>

(parent_rate / mfd) * mfn truncates the intermediate division in
clk_pllv3_av_recalc_rate() and clk_pllv3_sys_vf610_recalc_rate(). Use
u64 multiplication and do_div, as Linux does since commit ba7f4f557eb6
("clk: imx: correct AV PLL rate formula") and 5c2f117a22e4 ("clk: imx:
fix integer overflow in AV PLL round rate"), the latter having widened
the truncated result from u32 to unsigned long.

Fixes: 809549b1bf93 ("ARM i.MX: initial clk support")
Fixes: 7a8d295cdf60 ("i.MX: clk: Add IMX_PLLV3_SYS_VF610 subtype")
Reported-by: Claude:opus-4.6
Signed-off-by: Ahmad Fatoum <a.fatoum@barebox.org>
---
 drivers/clk/imx/clk-pllv3.c | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
index eb806e7f9892..8d41b76df826 100644
--- a/drivers/clk/imx/clk-pllv3.c
+++ b/drivers/clk/imx/clk-pllv3.c
@@ -192,7 +192,12 @@ static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw,
 	u32 mfd = readl(pll->base + PLL_DENOM_OFFSET);
 	u32 div = readl(pll->base) & pll->div_mask;
 
-	return (parent_rate * div) + ((parent_rate / mfd) * mfn);
+	u64 temp64 = (u64)parent_rate;
+
+	temp64 *= mfn;
+	do_div(temp64, mfd);
+
+	return parent_rate * div + (unsigned long)temp64;
 }
 
 static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate,
@@ -293,7 +298,12 @@ static unsigned long clk_pllv3_sys_vf610_recalc_rate(struct clk_hw *hw,
 	u32 mfd = readl(pll->base + SYS_VF610_PLL_OFFSET + PLL_DENOM_OFFSET);
 	u32 div = (readl(pll->base) & pll->div_mask) ? 22 : 20;
 
-	return (parent_rate * div) + ((parent_rate / mfd) * mfn);
+	u64 temp64 = (u64)parent_rate;
+
+	temp64 *= mfn;
+	do_div(temp64, mfd);
+
+	return parent_rate * div + (unsigned long)temp64;
 }
 
 static long clk_pllv3_sys_vf610_round_rate(struct clk_hw *hw, unsigned long rate,
-- 
2.47.3

[PATCH 6/8] clk: divider: use 64-bit division in _div_round_up and divider_get_val

[Ahmad Fatoum]

From: Ahmad Fatoum <a.fatoum@barebox.org>

The parent_rate + rate - 1 addition in DIV_ROUND_UP can overflow on
32-bit platforms. Use DIV_ROUND_UP_ULL, as Linux does since commit
9556f9dad8f5 ("clk: divider: handle integer overflow when dividing
large clock rates").

Fixes: 7d664f98d1ba ("clk: clk-divider: divider calculation in clk_set_rate needs DIV_ROUND_UP")
Fixes: b75025a39c77 ("clk: divider: Fix best div calculation for power-of-two and table dividers")
Reported-by: Claude:opus-4.6
Signed-off-by: Ahmad Fatoum <a.fatoum@barebox.org>
---
 drivers/clk/clk-divider.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 62d63ef39c7e..97dc9679c91c 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -161,7 +161,7 @@ static int _div_round_up(const struct clk_div_table *table,
 			 unsigned long parent_rate, unsigned long rate,
 			 unsigned long flags)
 {
-	int div = DIV_ROUND_UP(parent_rate, rate);
+	int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
 
 	if (flags & CLK_DIVIDER_POWER_OF_TWO)
 		div = __roundup_pow_of_two(div);
@@ -292,7 +292,7 @@ int divider_get_val(unsigned long rate, unsigned long parent_rate,
 {
 	unsigned int div, value;
 
-	div = DIV_ROUND_UP(parent_rate, rate);
+	div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
 
 	if (!_is_valid_div(table, div, flags))
 		return -EINVAL;
-- 
2.47.3

[PATCH 7/8] clk: divider: round up when searching for the best divider

[Ahmad Fatoum]

From: Ahmad Fatoum <a.fatoum@barebox.org>

clk_divider_bestdiv() compares candidates with a truncating division,
while divider_recalc_rate() rounds up. The search thus accepts a divider
whose reported rate is 1 Hz above the request, making clk_round_rate()
non-idempotent. Use DIV_ROUND_UP_ULL() there as well, as Linux commit
b11d282dbea2 ("clk: divider: fix rate calculation for fractional
rates") does; its other hunks barebox already has.

On i.MX6, clk_round_rate(ipu1_di0, 65 MHz) now yields 64800000 instead
of 40500000.

Fixes: e27c0b64db01 ("clk: add divider_recalc_rate helper")
Reported-by: Claude:opus-5
Signed-off-by: Ahmad Fatoum <a.fatoum@barebox.org>
---
 drivers/clk/clk-divider.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 97dc9679c91c..8e630ccde4e6 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -213,7 +213,7 @@ static int clk_divider_bestdiv(struct clk *clk, unsigned long rate,
 		}
 		parent_rate = clk_round_rate(clk_get_parent(clk),
 				MULT_ROUND_UP(rate, i));
-		now = parent_rate / i;
+		now = DIV_ROUND_UP_ULL((u64)parent_rate, i);
 		if (now <= rate && now > best) {
 			bestdiv = i;
 			best = now;
-- 
2.47.3

[PATCH 8/8] clk: divider: fix calculation of maximal parent rate for a given divider

[Ahmad Fatoum]

From: Ahmad Fatoum <a.fatoum@barebox.org>

This is an adoption of the corresponding Linux commit:

| commit da321133b53caf7889ed3ca1dabe4cc368db2604
| Author: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
| Date:   Sat Feb 21 11:40:23 2015 +0100
|
|     clk: divider: fix calculation of maximal parent rate for a given divider
|
|     The rate provided at the output of a clk-divider is calculated as:
|
|     	DIV_ROUND_UP(parent_rate, div)
|
|     since commit b11d282dbea2 (clk: divider: fix rate calculation for
|     fractional rates). So to yield a rate not bigger than r parent_rate
|     must be <= r * div.
|
|     The effect of choosing a parent rate that is too big as was done before
|     this patch results in wrongly ruling out good dividers.
|
|     Note that this is not a complete fix as __clk_round_rate might return a
|     value >= its 2nd parameter. Also for dividers with
|     CLK_DIVIDER_ROUND_CLOSEST set the calculation is not accurate. But this
|     fixes the test case by Sascha Hauer that uses a chain of three dividers
|     under a fixed clock.
|
|     Fixes: b11d282dbea2 (clk: divider: fix rate calculation for fractional rates)
|     Suggested-by: Sascha Hauer <s.hauer@pengutronix.de>
|     Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
|     Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
|     Signed-off-by: Michael Turquette <mturquette@linaro.org>

The "not a complete fix" caveat applies here as well: barebox'
clk_round_rate() falls back to clk_get_rate() for a clock without a
round_rate op, and clk_mux_round_rate() returns the closest parent rate, so
both can return more than they were asked for and clk_divider_bestdiv() can
still end up without a candidate. CLK_DIVIDER_ROUND_CLOSEST doesn't exist in
barebox, so that half of the caveat doesn't apply.

With the previous commit, the i.MX6 IPU pixel clocks now hit their
requested rates exactly, e.g. on a SABRE Lite:

  clk_round_rate ipu1_di0 65000000  ->  65000000 (was 40500000)
  clk_round_rate ipu1_di0 148500000 -> 148500000 (was 148500001)

Fixes: d4aaca3647fe ("clk: clk-divider: sync with kernel code")
Reported-by: Claude:opus-5
Signed-off-by: Ahmad Fatoum <a.fatoum@barebox.org>
---
 drivers/clk/clk-divider.c | 9 +--------
 1 file changed, 1 insertion(+), 8 deletions(-)

diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 8e630ccde4e6..2c97742cec0e 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -112,12 +112,6 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
 				   divider->flags, divider->width);
 }
 
-/*
- * The reverse of DIV_ROUND_UP: The maximum number which
- * divided by m is r
- */
-#define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)
-
 static bool _is_valid_table_div(const struct clk_div_table *table,
 							 unsigned int div)
 {
@@ -211,8 +205,7 @@ static int clk_divider_bestdiv(struct clk *clk, unsigned long rate,
 			*best_parent_rate = parent_rate_saved;
 			return i;
 		}
-		parent_rate = clk_round_rate(clk_get_parent(clk),
-				MULT_ROUND_UP(rate, i));
+		parent_rate = clk_round_rate(clk_get_parent(clk), rate * i);
 		now = DIV_ROUND_UP_ULL((u64)parent_rate, i);
 		if (now <= rate && now > best) {
 			bestdiv = i;
-- 
2.47.3