[PATCH 1/2] ARM64: mmu: map normal memory Inner Shareable

[PATCH 1/2] ARM64: mmu: map normal memory Inner Shareable

[Ahmad Fatoum]

From: Ahmad Fatoum <a.fatoum@barebox.org>

Commit 77446c78219e ("ARM: aarch64: mmu: use PTE_* definitions from
U-Boot") back in 2018 was meant to only switch to the U-Boot macro names,
but it also changed CACHED_MEM from Inner Shareable (PMD_SECT_S, 3 << 8)
to Outer Shareable. TCR was left at Inner Shareable, so since then, the
page table walker reads our translation tables Inner Shareable, while we
write them Outer Shareable.

All of Linux[1], U-Boot's generic ARMv8 code[2] (except for SoC memory maps,
like i.MX8M, which uses Outer Shareable), TF-A[3] and OP-TEE[4] all map
normal memory Inner Shareable. TF-A and OP-TEE run on the same core and
access the memory we pass them without cache maintenance, which the Arm
ARM[5] only guarantees to be coherent if the shareability matches.

Neither mismatch is assumed to have caused issues: we clean and invalidate
page table entries after each update anyway and the Cortex-A53, likely
our most used ARMv8 core, has a PIPT data cache without shareability in
its tags[6], so both mappings hit the same lines.

Hardware-coherent DMA, which we only rely on for Layerscape and virtio
and soon Agilex 5 would be affected if an SoC didn't extend the Inner
Shareable domain to the coherent masters, but this is assumed to be
fine as Linux would also use Inner Shareable for them.

Therefore, let's switch CACHED_MEM back to Inner Shareable.

[1]: Linux v6.18, PTE_SHARED and TCR_SHARED in
     arch/arm64/include/asm/pgtable-hwdef.h
[2]: U-Boot v2026.10, get_tcr() and mmu_map_region() in
     arch/arm/cpu/armv8/cache_v8.c
[3]: TF-A v2.15.0, xlat_desc() in lib/xlat_tables_v2/xlat_tables_core.c
     and setup_mmu_cfg() in lib/xlat_tables_v2/aarch64/xlat_tables_arch.c
[4]: OP-TEE 4.10.0, mattr_to_desc() and core_init_mmu_regs() in
     core/arch/arm/mm/core_mmu_lpae.c
[5]: Arm DDI 0487M.d, B2.11 Mismatched memory attributes, B2-331f.
[6]: Arm DDI 0500J, Cortex-A53 TRM, 2.1.6 Data side memory system, 2-4
     and 6.7.1 Data cache tag and data encoding, 6-14

Fixes: 77446c78219e ("ARM: aarch64: mmu: use PTE_* definitions from U-Boot")
Assisted-by: Claude:opus-5.5
Signed-off-by: Ahmad Fatoum <a.fatoum@barebox.org>
---
While a fix, I am not in a hurry to get this merged. next is fine to get
some more testing.
---
 arch/arm/cpu/mmu_64.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/cpu/mmu_64.h b/arch/arm/cpu/mmu_64.h
index ad7c1bde5631..6cc28908b59a 100644
--- a/arch/arm/cpu/mmu_64.h
+++ b/arch/arm/cpu/mmu_64.h
@@ -5,7 +5,7 @@
 typedef u64 mmu_addr_t;
 
 #define CACHED_MEM      (PTE_BLOCK_MEMTYPE(MT_NORMAL) | \
-			 PTE_BLOCK_OUTER_SHARE | \
+			 PTE_BLOCK_INNER_SHARE | \
 			 PTE_BLOCK_AF)
 #define UNCACHED_MEM    (PTE_BLOCK_MEMTYPE(MT_DEVICE_nGnRnE) | \
 			 PTE_BLOCK_OUTER_SHARE | \
-- 
2.47.3

[PATCH 2/2] habv4: drop cache maintenance around HAB SiP calls

[Ahmad Fatoum]

From: Ahmad Fatoum <a.fatoum@barebox.org>

On i.MX8M, barebox runs in non-secure EL2 and queries the HAB status and,
except on i.MX8MQ, the HAB events via SMC. So far, we cleaned and
invalidated the caller's variables before the SMC and only invalidated
them afterwards.

TF-A doesn't do any cache maintenance itself on the buffers and the
BootROM doesn't do any either: The BootROM disables the MMU it had setup
and cleans and invalidates the D-cache before jumping to the boot image.

The results are thus written through TF-A's mapping of DRAM
(SCTLR_EL3.{M,C} = 1, MT_MEMORY | MT_RW | MT_NS), i.e. Normal
Write-Back, Inner Shareable, Non-secure, and may still be dirty in the
cache when the SMC returns. Now that barebox maps normal memory the same
way, no maintenance is needed at all and no alignment requirements exist
for buffers.

Dropping the cache maintenance also fixes a bug: The invalidate after
the SMC was wrong, as it may discard updates not yet cleaned from the
cache, such as unrelated stack data in the same lines.

This was not observed to cause issues thus far, presumably because the
Cortex-A53 on the i.MX8M cleans dirty lines on DC IVAC when invalidating
them[1].

So let's drop the maintenance. With the MMU disabled, our accesses would
be Device-nGnRnE and need it again, so make HABV4 depend on MMU for
ARMv8 systems instead.

[1]: Arm DDI 0500J, Cortex-A53 TRM, 6.2.4 Data cache maintenance
     considerations, 6-3

Fixes: 6c4d5bb5acfe ("i.MX: HABv4: implement interface for i.MX8MQ")
Fixes: 3177ed294444 ("habv4: use hab rom implementation of report_event")
Assisted-by: Claude:opus-5.5
Signed-off-by: Ahmad Fatoum <a.fatoum@barebox.org>
---
While a fix, I am not in a hurry to get this merged. next is fine to get
some more testing.
---
 arch/arm/mach-imx/Kconfig |  2 +-
 drivers/hab/habv4.c       | 33 ++-------------------------------
 2 files changed, 3 insertions(+), 32 deletions(-)

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 5a5931f1a33d..0910eaa439c8 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -907,7 +907,7 @@ config HABV4
 	select HAB
 	select NVMEM
 	select IMX_OCOTP
-	depends on ARCH_IMX6 || ARCH_IMX8M
+	depends on ARCH_IMX6 || (ARCH_IMX8M && MMU)
 	help
 	  High Assurance Boot, as found on i.MX28/i.MX6/i.MX8M.
 
diff --git a/drivers/hab/habv4.c b/drivers/hab/habv4.c
index 83ee06a6aa46..e6244c96556e 100644
--- a/drivers/hab/habv4.c
+++ b/drivers/hab/habv4.c
@@ -7,16 +7,13 @@
 
 #define pr_fmt(fmt)  "HABv4: " fmt
 
-#include <common.h>
 #include <hab.h>
 #include <init.h>
 #include <types.h>
 #include <mmu.h>
-#include <dma.h>
 #include <zero_page.h>
 #include <linux/sizes.h>
 #include <linux/arm-smccc.h>
-#include <asm/cache.h>
 
 #include <mach/imx/generic.h>
 #include <mach/imx/imx8mq.h>
@@ -196,24 +193,10 @@ static enum hab_status hab_sip_report_event(enum hab_status status,
 {
 	struct arm_smccc_res res;
 
-	v8_flush_dcache_range((unsigned long)bytes,
-			      (unsigned long)bytes + sizeof(*bytes));
-
-	if (event)
-		v8_flush_dcache_range((unsigned long)event,
-				      (unsigned long)event + *bytes);
-
 	arm_smccc_smc(FSL_SIP_HAB, FSL_SIP_HAB_REPORT_EVENT,
 		      (unsigned long)index, (unsigned long)event,
 		      (unsigned long)bytes, 0, 0, 0, &res);
 
-	v8_inv_dcache_range((unsigned long)bytes,
-			    (unsigned long)bytes + sizeof(*bytes));
-
-	if (event)
-		v8_inv_dcache_range((unsigned long)event,
-				    (unsigned long)event + *bytes);
-
 	return (enum hab_status)res.a0;
 }
 
@@ -222,22 +205,10 @@ static enum hab_status hab_sip_report_status(enum hab_config *config,
 {
 	struct arm_smccc_res res;
 
-	if (state)
-		v8_flush_dcache_range((unsigned long)state,
-				      (unsigned long)state + sizeof(*config));
-	if (config)
-		v8_flush_dcache_range((unsigned long)config,
-				      (unsigned long)config + sizeof(*state));
-
 	arm_smccc_smc(FSL_SIP_HAB, FSL_SIP_HAB_REPORT_STATUS,
 		      (unsigned long) config,
 		      (unsigned long) state, 0, 0, 0, 0, &res);
-	if (state)
-		v8_inv_dcache_range((unsigned long)state,
-				    (unsigned long)state + sizeof(*config));
-	if (config)
-		v8_inv_dcache_range((unsigned long)config,
-				    (unsigned long)config + sizeof(*state));
+
 	return (enum hab_status)res.a0;
 }
 
@@ -587,7 +558,7 @@ static uint8_t *hab_get_event(const struct habv4_rvt *rvt, int index, size_t *le
 	if (err != HAB_STATUS_SUCCESS)
 		return NULL;
 
-	buf = dma_alloc(*len);
+	buf = malloc(*len);
 	if (!buf)
 		return NULL;
 
-- 
2.47.3